LOCOS Encyclopedia: Wikipedia & Grokipedia

LOCOS

current hub

Read side by side

LOCOS

View on Wikipedia

from Wikipedia

This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these messages)

This article includes a list of general references, but it lacks sufficient corresponding inline citations. Please help to improve this article by introducing more precise citations. (April 2016) (Learn how and when to remove this message)

This article relies largely or entirely on a single source. Relevant discussion may be found on the talk page. Please help improve this article by introducing citations to additional sources.
Find sources: "LOCOS" – news · newspapers · books · scholar · JSTOR (April 2016)

(Learn how and when to remove this message)

Typical LOCOS structure.
1) Silicon 2) Silicon dioxide

LOCOS, short for LOCal Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO₂ interface at a lower point than the rest of the silicon surface. As of 2008 it was largely superseded by shallow trench isolation.

This technology was developed to insulate MOS transistors from each other and limit transistor cross-talk. The main goal is to create a silicon oxide insulating structure that penetrates under the surface of the wafer, so that the Si-SiO₂ interface occurs at a lower point than the rest of the silicon surface. This cannot be easily achieved by etching field oxide. Thermal oxidation of selected regions surrounding transistors is used instead. The oxygen penetrates in depth of the wafer, reacts with silicon and transforms it into silicon oxide. In this way, an immersed structure is formed. For process design and analysis purposes, the oxidation of silicon surfaces can be modeled effectively using the Deal–Grove model.^[1]

References

[edit]

^ Liu, M.; Peng, J.; et al. (2016). "Two-dimensional modeling of the self-limiting oxidation in silicon and tungsten nanowires". Theoretical and Applied Mechanics Letters. 6 (5): 195–199. arXiv:1911.08908. doi:10.1016/j.taml.2016.08.002.

LOCOS

View on Grokipedia

from Grokipedia

Local Oxidation of Silicon (LOCOS) is a microfabrication technique in semiconductor device manufacturing that electrically isolates active components, such as transistors, on a silicon wafer by selectively growing thick silicon dioxide layers in field regions while protecting active areas with a mask.^[1] Developed in 1970 by J. A. Appels, E. Kooi, M. M. Paffen, J. J. H. Schatorjé, and W. H. C. G. Verkuylen at Philips Research Laboratories, LOCOS built on earlier discoveries in silicon passivation and planar processing to enable higher integration densities in MOS integrated circuits compared to junction isolation methods.^[1] The process starts with thermal growth of a thin pad oxide (10-20 nm) on the silicon substrate to relieve stress, followed by deposition of a silicon nitride layer (100-200 nm) that acts as an oxidation barrier due to its impermeability to oxygen and water vapor.^[1]^[2] Photolithography and etching pattern the nitride to define active regions, after which an optional channel-stop implant (e.g., boron) is introduced in field areas to prevent inversion; thick field oxide (typically 300-600 nm) is then grown via wet thermal oxidation in steam at temperatures above 950°C, selectively oxidizing exposed silicon.^[1]^[2] Post-oxidation, the nitride and pad oxide are removed, yielding isolated device regions, though the process induces compressive stress from the nitride and a lateral "bird's beak" encroachment under mask edges, which reduces active area usability and limits scaling below 0.5 μm feature sizes.^[1]^[2] While largely supplanted by shallow trench isolation (STI) in advanced CMOS technologies for better planarity and reduced encroachment, LOCOS variants persist in niche applications like power LDMOS devices, sub-50 nm isolation, and silicon carbide fabrication due to its simplicity and high-quality thermal oxide.^[3]^[4]^[5]

Overview

Definition and Purpose

Local Oxidation of Silicon (LOCOS) is a microfabrication technique employed to selectively form silicon dioxide (SiO₂) in designated areas on a silicon substrate, creating insulating regions that separate active device areas. Developed as a method to achieve precise control over oxidation, LOCOS utilizes a masking layer, typically silicon nitride, to prevent oxide growth in active regions while allowing thermal oxidation to proceed in exposed field areas. This results in the formation of thick field oxide layers that electrically isolate components on the wafer.^[1] The primary purpose of LOCOS is to enable device isolation in integrated circuits (ICs), preventing electrical interference between adjacent active regions such as transistors, diodes, and capacitors. By defining isolated active areas, LOCOS reduces parasitic capacitance, leakage currents, and surface recombination effects, which are critical for maintaining signal integrity and device performance in densely packed circuits. This isolation technique enhances overall IC reliability and supports higher integration densities by minimizing unwanted electrical coupling.^[2]^[1] In the context of semiconductor manufacturing, LOCOS is integrated into the front-end-of-line (FEOL) processing stage, where it defines the boundaries between field regions and active areas early in the fabrication sequence. This step lays the foundation for subsequent device formation, ensuring that transistors and other elements operate independently without cross-talk. LOCOS relies on the fundamental mechanism of thermal oxidation, where silicon reacts with an oxidizing ambient to grow SiO₂ selectively.^[6]^[7]

Basic Principle

The basic principle of LOCOS (LOCal Oxidation of Silicon) centers on the selective thermal oxidation of silicon, exploiting the stark difference in oxidation rates between exposed silicon surfaces and masked regions to create thick isolating oxide layers confined to designated areas. Silicon readily undergoes oxidation when exposed to oxygen or water vapor at high temperatures, forming silicon dioxide (SiO₂) that electrically isolates active device regions. In contrast, silicon nitride (Si₃N₄), deposited as a masking layer, effectively blocks oxidant diffusion due to its impermeability to oxygen and water vapor, preventing oxide growth beneath it and enabling precise control over isolation boundaries.^[1] The fundamental chemical reactions driving this process are the thermal oxidation of silicon, which occur in either dry or wet ambients. In dry oxidation, the reaction is Si + O₂ → SiO₂, while in wet oxidation (using steam), it is Si + 2H₂O → SiO₂ + 2H₂; both proceed at elevated temperatures typically above 900°C to achieve sufficient reaction kinetics and oxide quality.^[7] These reactions result in a volume expansion of approximately 2.2 times as silicon converts to SiO₂, generating significant compressive stress that must be managed to avoid defects in the silicon lattice. The process is thermally activated, with oxidation rates increasing exponentially with temperature, often performed between 900°C and 1200°C to balance growth speed and stress relaxation through viscous flow of the oxide.^[1] To accommodate this stress while maintaining mask integrity, a thin pad oxide layer (10-20 nm thick) is interposed between the silicon substrate and the Si₃N₄ mask (100-200 nm thick). The pad oxide, grown thermally prior to nitride deposition, serves as a compliant buffer that absorbs mechanical strain from the expanding field oxide, reducing the risk of cracking or dislocation in the underlying silicon. However, its relative permeability allows limited lateral diffusion of oxidants beneath the nitride edges during the high-temperature oxidation, leading to a characteristic "bird's beak" profile where the oxide encroaches slightly under the mask for smoother transitions. This controlled lateral oxidation is inherent to the masking effect and ensures robust isolation without excessive undercutting.^[1]

History

Invention

The LOCOS (LOCal Oxidation of Silicon) isolation technique was developed in the late 1960s and first presented in 1969 at the 3rd Conference on Solid State Devices in Exeter, UK, by J. A. Appels, E. Kooi, M. M. Paffen, J. J. H. Schatorjé, and W. H. C. G. Verkuylen at the Philips Research Laboratories in Eindhoven, Netherlands.^[8] This development emerged during the late 1960s as metal-oxide-semiconductor (MOS) integrated circuits began scaling toward higher densities, necessitating improved isolation methods beyond rudimentary approaches. The invention was detailed in the seminal paper "Local oxidation of silicon and its application in semiconductor-device technology," published in Philips Research Reports, Volume 25, pages 118–132. In this work, the team introduced selective thermal oxidation masked by silicon nitride to create thick field oxides for device separation, marking a pivotal shift in fabrication strategies.^[1] The primary motivation for LOCOS stemmed from the shortcomings of prior p-n junction isolation techniques, which relied on reverse-biased diffused junctions and resulted in substantial parasitic capacitances that degraded circuit speed and power efficiency in MOS ICs. Additionally, these early methods exacerbated latch-up vulnerabilities—a parasitic thyristor effect in complementary MOS structures—due to inadequate spacing and electrical coupling between active regions, hindering reliable high-density integration.^[1] By enabling thicker, more planar isolation with reduced lateral dopant diffusion, LOCOS addressed these challenges, facilitating the evolution of MOS technology.

Development and Variants

Following its invention in the late 1960s, LOCOS saw early adoption in the 1970s for NMOS and bipolar integrated circuit processes, where it provided reliable device isolation in scaling from 10 μm to 5 μm feature sizes.^[9] By the 1980s, refinements enabled its integration into CMOS technologies, supporting denser layouts down to 1-2 μm nodes through optimizations in oxide thickness and mask alignment to mitigate encroachment effects.^[1] To address limitations like the bird's beak encroachment that hindered further scaling, several variants emerged in the late 1970s and 1980s. Fully-recessed LOCOS involved etching a shallow trench into the silicon prior to field oxidation, allowing the oxide to grow below the original surface level and reducing lateral oxide extension to under 0.5 μm while improving surface planarity.^[10] Poly-buffered LOCOS (PBL), introduced in the mid-1980s, incorporated a thin polysilicon layer beneath the nitride mask to absorb oxidation-induced stress, shortening the bird's beak by up to 50% compared to conventional LOCOS and enabling isolation widths as small as 1.5 μm without significant defect generation.^[11] Sealed Interface LOCOS (SILO), developed around 1980, employed a nitrided silicon interface layer to seal the silicon-nitride boundary, minimizing white ribbon defects and interface traps while achieving bird's beak lengths of approximately 0.2 μm.^[12] As feature sizes approached sub-micron dimensions in the early 1990s, extensions like poly-encapsulated LOCOS (PELOX) were proposed to enhance recess depth and planarity. PELOX filled the recessed cavity with polysilicon before oxidation, providing up to 0.3 μm of oxide recess and supporting 0.35 μm CMOS processes with reduced parasitic capacitance.^[13] However, persistent issues with non-planar topography and stress-induced dislocations led to LOCOS variants being phased out below 0.5 μm nodes, as they complicated multilevel interconnect fabrication and increased variability in advanced CMOS scaling.^[1]

Fabrication Process

Preparation Steps

The preparation of a silicon wafer for the local oxidation of silicon (LOCOS) process begins with a clean n-type silicon substrate, typically oriented in the <100> direction with a resistivity of 5-10 Ω-cm and a thickness of approximately 525 μm.^[14] This starting material ensures uniform electrical properties and minimizes defects that could affect subsequent processing.^[1] A thin thermal pad oxide layer, usually 10-20 nm thick, is then grown on the wafer surface via wet oxidation at around 850°C in a steam ambient to provide stress relief between the silicon substrate and the overlying nitride layer, preventing cracking during high-temperature oxidation steps.^[14] This pad oxide also serves as an etch-stop layer in later nitride removal processes.^[1] Next, a silicon nitride (Si₃N₄) film, 100-200 nm thick, is deposited using low-pressure chemical vapor deposition (LPCVD) at approximately 785°C, acting as an oxidation mask to protect active device regions from field oxide growth.^[14] The nitride's impermeability to oxygen enables selective oxidation in exposed areas.^[1] Photolithography is employed to pattern the nitride layer, using a mask to define isolation (field) regions, followed by dry etching—typically reactive ion etching in a plasma tool—to open windows that expose the underlying silicon and pad oxide in those areas.^[14] This step precisely delineates the boundaries between active and isolation zones.^[1] An optional boron ion implantation may be performed in the exposed field regions, with a dose of 4 × 10¹³ cm⁻² at 180 keV, to form p-type channel stops in field regions, adjusting the threshold voltage to prevent parasitic inversion and enhance isolation.^[14] This implant mitigates parasitic transistor effects in the field oxide areas.^[1]

Oxidation and Etching

The thermal oxidation phase in the LOCOS process entails heating the masked silicon wafer in a steam or dry oxygen ambient at temperatures above 950°C for 2-4 hours, enabling selective growth of a thick field oxide layer (typically 300-500 nm) exclusively in the exposed silicon regions unprotected by the nitride mask.^[15] This oxidation leverages the impermeability of the silicon nitride to oxygen and water vapor, confining the reaction to bare silicon surfaces while the pad oxide beneath the nitride facilitates stress relief.^[1] A characteristic lateral extension, termed the bird's beak, occurs under the nitride edges due to oxidant diffusion and oxide volume expansion, tapering the field oxide profile and encroaching slightly into active areas.^[15] A notable phenomenon during this oxidation is the Kooi effect, where a thin silicon nitride layer forms at the silicon-silicon dioxide interface through reaction with ammonia produced from interactions between the oxidizing ambient and nitride mask.^[16] This interfacial nitridation, often visible as a "white ribbon" in cross-sections, arises primarily at the bird's beak region and can introduce stress-related defects if not mitigated, though it generally enhances interface stability in standard conditions.^[17] Post-oxidation processing begins with selective removal of the silicon nitride mask using hot phosphoric acid (H₃PO₄) at 150-180°C, which etches nitride at rates significantly higher than oxide (over 100:1 selectivity). The exposed pad oxide is then stripped with buffered hydrofluoric acid (HF), typically a 6:1 mixture of ammonium fluoride and HF, to reveal the active silicon surface without damaging the underlying substrate or field oxide. Optional chemical-mechanical polishing or etch-back may follow to planarize the topography, though this is not always necessary in basic LOCOS implementations.^[18]

Advantages and Limitations

Key Advantages

The LOCOS process offers a straightforward fabrication sequence that utilizes minimal masks and processing steps, such as pad oxide growth, nitride deposition and patterning, field oxidation, and subsequent stripping, which contributes to higher manufacturing yields and lower costs relative to diffusion-based isolation techniques.^[1]^[19] The thermally grown field oxide in LOCOS delivers superior electrical isolation properties, characterized by low defect density and effective passivation of the silicon surface, which significantly reduces parasitic leakage currents compared to deposited oxides.^[1] LOCOS demonstrates strong compatibility with standard CMOS fabrication flows, enabling reliable integration and scaling to feature sizes as small as 1 μm in advanced processes.^[20] Fully recessed variants of LOCOS enhance this performance by achieving higher field threshold voltages, typically around 13 V, thereby improving overall isolation effectiveness without compromising planarity.^[21]

Principal Limitations

One of the primary limitations of the LOCOS process is the bird's beak effect, in which lateral oxide growth occurs beneath the edges of the silicon nitride mask during field oxidation, encroaching into the active device regions by up to 0.5 μm per side for typical field oxide thicknesses around 0.5 μm.^[21] This non-planar intrusion limits the minimum spacing between active areas, thereby reducing the overall packing density and scalability of integrated circuits, particularly as feature sizes approach sub-micron dimensions. Another significant drawback arises from the high stress introduced by the silicon nitride (Si₃N₄) mask layer, with the nitride having intrinsic tensile stress of approximately 1 GPa, which, combined with volume expansion during oxidation, induces compressive stresses of up to 1 GPa in the underlying silicon at the mask edges and beneath the nitride.^[22] This stress concentrates at the mask edges and beneath the nitride, promoting the generation of dislocations in the underlying silicon substrate, which can propagate into active regions and lead to increased leakage currents or yield degradation in devices.^[23] The Kooi effect further compromises device reliability by forming a thin silicon oxynitride layer at the silicon/silicon dioxide interface near the nitride mask edges during the initial oxidation steps.^[1] This interface nitride acts as a micromask in subsequent gate oxide growth, resulting in significant localized thinning of the gate dielectric compared to the active area, which elevates electric field strengths and accelerates time-dependent dielectric breakdown. Additionally, the sloped profile of the field oxide from the bird's beak enables the formation of parasitic field-effect transistors along isolation edges, potentially triggering latch-up events in CMOS circuits under high-voltage conditions.^[1]

Applications and Alternatives

Use in Integrated Circuits

LOCOS plays a primary role in integrated circuit fabrication by defining active areas for metal-oxide-semiconductor field-effect transistors (MOSFETs) in complementary metal-oxide-semiconductor (CMOS) processes, where it creates thick silicon dioxide regions to electrically isolate n-wells, p-wells, and bipolar junctions, preventing unwanted current leakage between devices.^[1] This isolation ensures reliable operation of densely packed transistors by confining conductive channels to specified regions while suppressing parasitic effects at device boundaries.^[24] In the front-end-of-line (FEOL) fabrication sequence, LOCOS is typically implemented early, immediately following well implantation and formation to establish isolation before subsequent steps like gate formation and source/drain doping. The process involves patterning a silicon nitride mask over thin pad oxide, followed by thermal oxidation to grow the field oxide, which achieves an isolation depth determined by its thickness of approximately 0.3-0.5 μm in standard CMOS technologies.^[1] This thickness provides sufficient barrier height for typical operating voltages while maintaining compatibility with planar processing.^[25] LOCOS was extensively applied in memory chips, such as dynamic random-access memory (DRAM) devices, throughout the 1980s and 1990s, enabling scalable cell isolation in generations up to 256 Mbit densities with 0.6 μm feature pitches.^[1] In logic integrated circuits (ICs), it served as the standard isolation method for CMOS-based designs during the same period, supporting high-density gate arrays and microprocessors by accommodating minimum spacing requirements down to sub-micron levels.^[26] Additionally, LOCOS supports analog and power devices requiring high-voltage isolation, often in combination with deep trench structures to handle breakdown voltages exceeding 50 V in bipolar-CMOS-DMOS (BCD) technologies.^[27]

Transition to Shallow Trench Isolation

As semiconductor manufacturing scaled toward sub-0.5 μm feature sizes in the 1990s, the bird's beak encroachment in LOCOS isolation became a significant barrier, consuming active silicon area and creating non-planar surfaces that complicated subsequent lithography and etching steps.^[1] This lateral oxide growth under the nitride mask reduced device density and increased parasitic capacitance, making LOCOS unsuitable for denser integrated circuits.^[28] In contrast, shallow trench isolation (STI) addressed these issues by etching vertical trenches directly into the silicon, enabling tighter spacing between active regions and a flatter topography essential for advanced scaling.^[29] The STI process begins with etching shallow trenches, typically 0.2–0.4 μm deep, into the silicon substrate using reactive ion etching after patterning a pad oxide and nitride layer.^[29] The trench sidewalls are then lined with a thin thermal oxide to passivate the silicon and prevent defects, followed by filling the trenches with high-density plasma (HDP) oxide, which provides excellent gap-fill properties for high-aspect-ratio structures. Finally, chemical-mechanical polishing (CMP) is applied to remove excess oxide and nitride, yielding a planar surface that supports uniform gate formation and multilevel interconnects.^[30] STI gained widespread adoption in the late 1990s, with IBM implementing it in their 0.25 μm CMOS processes for logic and memory applications to achieve higher densities. This transition marked the standard for mainstream CMOS technologies below 0.35 μm, though LOCOS continues to be used in niche high-voltage applications, such as power LDMOS transistors, as of 2024, due to its simpler thermal oxidation and robustness under high fields. By the early 2000s, STI had largely supplanted LOCOS in advanced nodes, driven by the need for planarity in sub-100 nm scaling. LOCOS variants also continue to find use in specialized areas, including radiation-hardened 4H-SiC power devices and advanced processes for sub-50 nm isolation, as of 2024.^[31]^[32]^[33]^[3]

Knowledge Base

Talk Channels

Special Pages

LOCOS

LOCOS

LOCOS

References

See also

LOCOS

Overview

Definition and Purpose

Basic Principle

History

Invention

Development and Variants

Fabrication Process

Preparation Steps

Oxidation and Etching

Advantages and Limitations

Key Advantages

Principal Limitations

Applications and Alternatives

Use in Integrated Circuits

Transition to Shallow Trench Isolation

References