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Die preparation
Die preparation
Die preparation
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Wafer glued on blue tape and cut into pieces, with some individual dies removed

Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation typically consists of two steps: wafer mounting and wafer dicing.

Wafer mounting

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Wafer mounting is a step that is performed during the die preparation of a wafer as part of the process of semiconductor fabrication. During this step, the wafer is mounted on a plastic tape that is attached to a ring. Wafer mounting is performed right before the wafer is cut into separate dies. The adhesive film upon which the wafer is mounted ensures that the individual dies remain firmly in place during 'dicing', as the process of cutting the wafer is called.

The picture on the right shows a 300 mm wafer after it was mounted and diced. The blue plastic is the adhesive tape. The wafer is the round disc in the middle. In this case, a large number of dies were already removed.

Semiconductor-die cutting

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Main article: Die singulation

In the manufacturing of micro-electronic devices, die cutting, dicing or singulation is a process of reducing a wafer containing multiple identical integrated circuits to individual dies each containing one of those circuits.

During this process, a wafer with up to thousands of circuits is cut into rectangular pieces, each called a die. In between those functional parts of the circuits, a thin non-functional spacing is foreseen where a saw can safely cut the wafer without damaging the circuits. This spacing is called the scribe line or saw street. The width of the scribe is very small, typically around 100 μm. A very thin and accurate saw is therefore needed to cut the wafer into pieces. Usually the dicing is performed with a water-cooled circular saw with diamond-tipped teeth.

Types of blades

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The most common make up of blade used is either a metal or resin bond containing abrasive grit of natural or more commonly synthetic diamond, or borazon in various forms. Alternatively, the bond and grit may be applied as a coating to a metal former. See diamond tools.

Further reading

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

Die preparation

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from Grokipedia
Die preparation, also known as die prep, is a critical stage in that involves separating a processed into individual dies (chips) through precision processes such as wafer thinning, singulation, and handling, preparing them for subsequent assembly and . This process follows front-end and is essential for enabling the production of integrated circuits used in , where wafer diameters have grown to 300 mm or larger, increasing complexity and yield risks. The primary steps in die preparation begin with wafer mounting, where the wafer is secured to a dicing frame using to prevent damage during handling, followed by wafer thinning (or backgrinding), which reduces the wafer thickness—often to 50–100 µm or thinner—via mechanical grinding, chemical-mechanical polishing (CMP), or etching techniques like the process that preserves edge strength to minimize breakage. Singulation, the core separation step, then divides the thinned wafer into dies using methods such as mechanical blade with diamond-impregnated wheels, for high-precision cuts, stealth dicing via subsurface modification, or plasma to avoid mechanical stress on delicate low-k layers. Post-singulation, dies undergo with to remove debris, inspection for defects like chipping or , and pick-and-place operations that transfer qualified dies to carriers like tape-and-reel for further processing. Die preparation significantly impacts overall yield and cost, as even a 1% defect rate can reduce the number of usable dies from a , while challenges like , mechanical cracking in ultra-thin dies (≤50 µm), and handling of advanced formats (e.g., /3D) drive ongoing innovations. The global market for die prep equipment and services was valued at approximately $1.2 billion in 2023 and is projected to reach $1.8 billion by 2030, fueled by demand for smaller, more efficient devices. Leading equipment suppliers include Disco Corporation, which dominates with technologies like the process and stealth dicing, alongside firms such as Kulicke & Soffa and ASMPT.

Introduction

Definition and scope

Die preparation refers to the sequence of manufacturing steps designed to separate individual dies from a processed , transforming a monolithic substrate into discrete components ready for further integration. A is a thin, circular disc—typically 525–775 micrometers thick depending on the diameter and ranging from 100 to 300 millimeters in diameter—composed of high-purity with numerous identical integrated circuits patterned across its surface through prior fabrication processes. The core steps encompass thinning to achieve desired die thicknesses (often 50–100 micrometers for advanced applications), mounting the wafer onto dicing tape for mechanical support, dicing to physically sever the dies along predefined streets, to eliminate residues and contaminants, and preliminary to identify and sort viable dies. The scope of die preparation is confined to the transitional back-end processes immediately following front-end , where circuit formation occurs, but preceding full packaging and testing stages that involve encapsulation and electrical . This phase addresses the challenges of handling fragile, sub-micron-featured structures post-fabrication, with primary goals of minimizing physical damage such as chipping or cracking, optimizing yield by preserving as many functional dies as possible from the , and conditioning the dies for reliable assembly into modules like system-in-packages or 3D-stacked devices. By focusing on precision and , die preparation ensures economic viability in high-volume production, where even marginal yield improvements can significantly impact costs. Historically, die preparation originated in the 1960s as technology advanced beyond discrete components, coinciding with the formulation of in 1965, which forecasted exponential increases in density. Early processes handled small s of about 25 millimeters in diameter, supporting rudimentary ICs with limited counts, but evolved alongside scaling trends to manage feature sizes below 1 micrometer and diameters expanding to 300 millimeters by the , with ongoing development of 450-millimeter wafers to boost throughput, as of 2025. This progression has been driven by the need to accommodate denser, thinner dies without compromising integrity, aligning with sustained integration under .

Importance in semiconductor manufacturing

Die preparation is a pivotal stage in , significantly influencing overall production yield by ensuring the integrity of individual dies separated from the . Defects arising from inadequate or , such as chipping, cracking, or contamination, can substantially diminish the number of functional dies per , with poor execution leading to yield losses that compromise the of the entire fabrication . For example, in () production, conventional blade contributes to an average yield loss of 9%, highlighting the need for precise control to maximize usable output. These issues are exacerbated in advanced nodes where die sizes shrink, amplifying the impact of even minor defects on overall yield. From an economic perspective, die preparation accounts for a notable share of back-end costs, with inefficiencies directly affecting profitability in high-volume production of devices like CPUs and chips. Advanced dicing techniques, such as or plasma methods, can reduce costs by minimizing material waste and improving throughput through higher die counts and reduced rework. A key factor is kerf loss—the width of material removed during cuts—which typically measures 20-50 μm for blade dicing, limiting the number of dies extracted from each ; narrower kerfs in optimized processes, down to 15 μm, enhance economic viability by increasing die yield without sacrificing quality. Technically, die preparation mitigates challenges like in , which can induce warpage or fractures due to material removal and gradients, ensuring structural reliability for subsequent integration. This stage is essential for scalability in 3D ICs and heterogeneous integration, where precise and support stacking and interconnects critical for performance gains. By 2025, die preparation facilitates adoption of sub-2 nm nodes and chiplet-based packaging, addressing the demands of AI and . Industry trends emphasize under Industry 4.0 frameworks, incorporating real-time monitoring and AI-driven adjustments to further elevate yield and adaptability in evolving ecosystems.

Pre-Dicing Preparation

Wafer thinning

Wafer thinning is a critical step in die preparation that reduces the thickness of wafers from the standard 775 μm for mm wafers to 50-100 μm, enabling die stacking in three-dimensional integrated circuits (3D ICs). This process enhances thermal performance by shortening heat dissipation paths and increases integration density through vertical stacking, which supports higher counts and improved in advanced packaging. The primary methods for wafer thinning include mechanical backgrinding, which employs diamond-impregnated wheels to rapidly remove bulk material, followed by chemical-mechanical (CMP) to achieve a smooth with minimal roughness. During backgrinding, the is typically mounted on a carrier or tape, and a high-speed spindle rotates the against the wafer backside, with removal rates ranging from 10 to 50 μm/min. Coolants, such as deionized water, are applied to dissipate heat and prevent thermal-induced warping. For ultra-thin wafers below 100 μm, temporary bonding to a rigid carrier is essential, providing mechanical support during grinding and subsequent processing to avoid breakage. Key parameters in the thinning process influence residual stress and structural integrity, modeled by the biaxial stress equation: σ=Eϵ1−ν\sigma = \frac{E \epsilon}{1 - \nu} where σ\sigma is the residual stress, EE is Young's modulus (approximately 169 GPa for silicon), ϵ\epsilon is the strain, and ν\nu is Poisson's ratio (approximately 0.28). Challenges include controlling warpage to less than 50 μm across the wafer to ensure uniform stacking, as excessive bowing can misalign dies during assembly. Additionally, mechanical grinding introduces a subsurface damage layer 1-5 μm deep, consisting of microcracks and dislocations, which is mitigated through etch-back processes like wet chemical etching. Plasma etching variants offer a damage-free alternative for final thinning, providing isotropic removal without mechanical stress, though at slower rates of about 20 μm/min. In 2024, Infineon developed a 20 μm thick 300 mm silicon power wafer, reducing power loss by over 15% compared to conventional designs.

Wafer mounting

Wafer mounting is a critical step in die preparation that secures the semiconductor to a support structure, providing mechanical stability during the subsequent process. This procedure typically begins after , where the fragile, reduced-thickness wafer requires immobilization to prevent warping, cracking, or breakage. The process involves applying a specialized dicing tape to the backside of the wafer and affixing the assembly to a rigid frame, enabling precise handling and alignment for cutting. Dicing tapes are adhesive films, commonly UV-curable or thermal-release types, with total thicknesses ranging from 80 to 130 μm, including a base film and layer of 10-20 μm. These tapes exhibit initial strengths of approximately 1-5 N per 25 mm width to firmly hold the during processing, with selection criteria depending on factors such as wafer thickness, die dimensions, and . UV-curable variants maintain high tack during but undergo a significant reduction in —often to about 10% of the original strength—following exposure, facilitating easy die release without residue. Thermal-release tapes, alternatively, detach via controlled heating up to 150°C. Support frames are typically metal rings or plastic hoops with diameters of 6-8 inches for 200 mm wafers or larger for 300 mm substrates, ensuring compatibility with automated equipment. The mounting process entails precise steps to ensure uniform contact and minimal defects. The wafer is aligned and placed onto the pre-stretched dicing tape under vacuum conditions, which creates differential pressure to balloon the tape gently against the wafer backside, eliminating air gaps and promoting . For non-UV tapes, optional curing via heat or time allows the to fully bond, often stabilizing within 4 hours. Handling ultra-thin wafers below 100 μm thickness necessitates temporary carrier systems, such as bonded carrier wafers or rigid substrates, to provide additional support and mitigate breakage risks during transfer and mounting. Recent advancements in mounting include anti-static electrostatic tapes that minimize particle on sensitive devices, and -release tapes designed for integration with advanced methods on larger 450 mm wafers. These innovations, such as UV tapes with low ionic residues and compatibility with full-cut processes, enhance yield by reducing transfer and debris compared to conventional films.

Dicing Process

Cutting techniques

Cutting techniques in die preparation involve separating individual dies from a mounted through precise methods that minimize material loss, thermal damage, and defects. These techniques are applied after and mounting, ensuring the remains securely held on dicing tape during the process. Mechanical encompasses traditional approaches like sawing and scribe-and-break. sawing uses a rotating -impregnated blade to make linear cuts along predefined streets on the surface, typically at feed rates of 20-100 mm/s to balance speed and precision. This method is widely used for and compound semiconductors due to its reliability and compatibility with standard thicknesses. In the scribe-and-break technique, a or first scribes shallow grooves (typically 3-5 μm deep) along to create stress concentrations. For saw-based scribing, the groove can extend to 50-80% of the thickness, reducing the cross-section before a mechanical snap or bending force propagates cracks along these lines, fracturing the brittle material without full-thickness cutting. This approach is particularly suited for thin, fragile substrates like III-V compounds, , or ceramics, where sawing might induce excessive chipping. Advanced techniques address limitations of mechanical methods, such as kerf loss and heat-affected zones. Laser stealth focuses a near-infrared (1060-1080 nm) inside the to form a modified layer of micro-perforations at targeted depths, initiating crack propagation upon tape expansion without surface or damage. This dry process eliminates , recast layers, and cleaning needs, enabling higher yields for small dies (<1 mm²) in applications like and . Plasma dicing employs dry etching in a vacuum chamber using the Bosch process to anisotropically remove material along masked streets, achieving kerf-free cuts with material loss under 10 μm. This method provides superior die strength by avoiding mechanical or thermal stress, making it ideal for high-quality devices such as power semiconductors, LEDs, and RF filters. Key parameters for these techniques include spindle speeds of 20,000-60,000 RPM for sawing to maintain blade stability, controlled feed rates to prevent chipping, and coolant flow (typically deionized water at high pressure) to dissipate heat and keep temperatures below 100°C. The kerf width ww is approximately equal to the blade thickness tt (typically 20-50 μm), plus a small additional loss due to diamond grit and process factors; narrower kerfs maximize die density. Yield optimization focuses on street widths of 50-100 μm between dies, allowing thinner blades and advanced techniques to increase dies per while maintaining edge quality. Hybrid laser-saw methods, combining laser grooving with mechanical sawing, have gained adoption by 2025 for high-volume and automotive chips, offering reduced chipping and higher throughput in advanced packaging. As of 2025, hybrid approaches including femtosecond are increasingly adopted for next-generation applications, further reducing chipping in advanced nodes.

Types of blades

In mechanical dicing of semiconductor wafers, blades are primarily categorized by their bonding materials and structures, with nickel electroformed and resin-bonded types being the most common for achieving high precision and minimal damage. Nickel electroformed blades consist of a thin nickel layer electroplated onto a substrate, embedding diamond particles for cutting, and are favored for their rigidity and ability to produce fine kerfs in standard silicon wafers. These blades typically range in thickness from 20 to 50 μm, enabling high-precision cuts with kerf widths as narrow as 25 μm, which is essential for densely packed integrated circuits. Their electroforming process ensures uniform diamond distribution, reducing vibration and improving straightness during high-speed sawing of silicon up to 300 μm thick. Resin-bonded blades use a matrix to hold abrasives, offering a softer bond that minimizes chipping and subsurface damage, particularly in brittle compound semiconductors like (GaAs). These blades are available in hubbed designs, where a metal core provides structural support for stability in automated systems, or hubless configurations, which allow for thinner profiles and easier integration into spindle tools but require careful handling to prevent flexing. The resin bond's elasticity helps absorb shocks during cuts on materials prone to cracking, such as GaAs wafers used in , achieving chipping sizes below 10 μm under optimized conditions. Diamond grit specifications in dicing blades are tailored to balance cutting speed, surface finish, and blade life, with mesh sizes of 325 to 600 commonly used for fine cuts on wafers requiring minimal kerf loss. Finer grits (e.g., 600 mesh, approximately 20-25 μm particles) yield smoother edges with reduced chipping but slower material removal, while coarser grits (e.g., 325 mesh, around 40-45 μm) accelerate dicing for thicker substrates. Diamond concentration, measured as volume percentage in the bond, typically ranges from 50% to 100%, where higher concentrations (e.g., 100%) enhance aggressiveness and heat dissipation but increase cost; a 75% concentration often optimizes performance for silicon and GaAs, extending blade life by 20-30% compared to lower levels. Blade wear during dicing is modeled using adaptations of Archard's wear law, V=kFLHV = k \frac{F L}{H}, where VV is the volume of material removed from the blade, FF is the cutting force, LL is the sliding distance, HH is the of the blade material, and kk is the dependent on bond hardness and coolant flow. This model predicts radial wear rates of 1-5 μm per linear meter of cut for blades on , guiding replacement intervals to maintain cut quality. Selection of blade types hinges on wafer material compatibility, with harder bonds like nickel electroformed preferred for durable () to withstand abrasion, while resin bonds suit softer GaAs to limit fractures. For thermally sensitive dies in 2025 electric vehicle chips, emerging cryogenic blades operating at -50°C reduce thermal cracking in by enhancing material brittleness and minimizing heat-affected zones, though they require specialized cooling systems.

Post-Dicing Handling

Die cleaning

Die cleaning is a critical step in the die preparation process that occurs immediately after wafer dicing to remove contaminants and ensure the integrity of individual dies for subsequent and assembly. The primary contaminants introduced during dicing include saw debris, consisting of particles typically ranging from 1 to 10 μm in size generated from the kerf—the material removed during cutting—as well as blade wear that contributes metallic fragments and abrasive particles. Additional residues arise from dicing tape adhesives and fluids used to manage and reduce chipping, which can leave organic films and chemical remnants on die surfaces if not addressed. Common methods for die cleaning leverage wet and dry techniques tailored to contaminant types. Ultrasonic cleaning in deionized (DI) water, operating at frequencies of 40 to 120 kHz for 5 to 10 minutes, effectively dislodges particulate through bubbles that implode to create micro-jets, minimizing damage to delicate die edges. For organic residues such as tape adhesives, employs oxygen plasma to oxidize and volatilize contaminants, providing a dry, residue-free removal without handling. Megasonic cleaning, using higher frequencies above 1 MHz, targets sub-micron particles by generating stable for gentler agitation, particularly useful for thinned dies prone to stress. The typical process flow begins with of the dicing tape frame, which gently separates the dies to prevent mechanical damage and facilitate access for cleaning agents. This is followed by sequential rinse cycles in DI or mild solvents to flush away loose debris, combined with drying steps using blow-off or spin drying to achieve particle counts below 10 particles per cm² on die surfaces, ensuring compatibility with downstream handling. Recent advancements focus on sustainability and efficiency in cleaning processes. Eco-friendly solvents, such as bio-based alternatives to (IPA), are increasingly adopted to reduce emissions and water usage while maintaining efficacy in removing coolant remnants. Additionally, cryogenic aerosol cleaning using CO₂ or jets enables zero-liquid, damage-free removal of particles in 2025 fabrication facilities, supporting high-throughput operations for advanced nodes by minimizing environmental impact and die stress.

Inspection and sorting

Following the dicing and cleaning processes, individual dies undergo to assess their structural and functionality, ensuring only viable components proceed to packaging. Visual primarily relies on (AOI) systems, which employ high-resolution cameras and structured lighting to detect surface defects such as cracks, chipping, and scratches on the die edges and faces. These systems achieve defect detection resolutions down to the micron scale, typically rejecting dies with chipping or cracks exceeding 10-100 μm, depending on the process and die specifications, to prevent reliability issues in downstream assembly. For subsurface evaluation, UV fluorescence techniques illuminate the die under ultraviolet light, causing material inconsistencies like hidden microcracks or damage from dicing to fluoresce and become visible, enabling non-destructive assessment without physical contact. Electrical testing complements visual methods by verifying the die's basic functionality prior to packaging, using probe stations to make temporary electrical contacts with die pads for continuity checks and parametric measurements. These tests are limited in scope at this stage, focusing on gross functionality rather than full-speed operation, as comprehensive validation occurs post-packaging; however, they identify open circuits or shorts early. Yield mapping software integrates inspection data from both visual and electrical tests, correlating defect locations across the original wafer to identify patterns in specific zones, such as edge effects or process hotspots, thereby informing process improvements. Sorting mechanisms automate the and separation of inspected dies using pick-and-place robots equipped with vision-guided systems to handle fragile components precisely. Good dies are transferred to tapes or trays for subsequent handling, while defective ones are diverted to reject bins, minimizing risks. This process is quantified using metrics like gross die per (GDPW), approximated as π(D/2)2A−πD2A\frac{\pi (D/2)^2}{A} - \frac{\pi D}{\sqrt{2 A}}
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