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Intel 8259
Intel 8259
Intel 8259
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Closeup of an Intel 8259A IRQ chip from a PC XT.
Pinout

The Intel 8259 is a programmable interrupt controller (PIC) designed for the Intel 8080 and Intel 8085 microprocessors. The initial part was the 8259; the later 8259A was upward compatible and usable with the 8086 or 8088 processor. The 8259 combines multiple interrupt input sources into a single interrupt output to the host microprocessor, extending the interrupt levels available in a system beyond the one or two levels found on the processor chip. The 8259A was the interrupt controller for the ISA bus in the original IBM PC and IBM PC AT.

The 8259 was introduced as part of Intel's MCS 85 family in 1976. The 8259A was included in the original PC introduced in 1981 and maintained by the PC/XT when introduced in 1983. A second 8259A was added with the introduction of the PC/AT. The 8259 has coexisted with the Intel APIC Architecture since its introduction in symmetric multiprocessor PCs. Modern PCs have begun to phase out the 8259A in favor of the Intel APIC Architecture. However, while not anymore a separate chip, the 8259A interface is still provided by the Platform Controller Hub or southbridge on modern x86 motherboards.[1]

Functional description

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The main signal pins on an 8259 are as follows: eight interrupt request input lines named IRQ0 through IRQ7, an interrupt request output line named INTR, interrupt acknowledgment line named INTA, D0 through D7 for communicating the interrupt level or vector offset. Other connections include CAS0 through CAS2 for cascading between 8259s.

Up to eight slave 8259s may be cascaded to a master 8259 to provide up to 64 IRQs. 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.

End of interrupt (EOI) operations support specific EOI, non-specific EOI, and auto-EOI. A specific EOI specifies the IRQ level it is acknowledging in the ISR. A non-specific EOI resets the IRQ level in the ISR. Auto-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged.

Edge and level interrupt trigger modes are supported by the 8259A. Fixed priority and rotating priority modes are supported.

The 8259 may be configured to work with an 8080/8085 or an 8086/8088. On the 8086/8088, the interrupt controller will provide an interrupt number on the data bus when an interrupt occurs. The interrupt cycle of the 8080/8085 will issue three bytes on the data bus (corresponding to a CALL instruction in the 8080/8085 instruction set).

The 8259A provides additional functionality compared to the 8259 (in particular buffered mode and level-triggered mode) and is upward compatible with it.

Programming considerations

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DOS and Windows

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NEC D8259AC, used on the original IBM PC motherboard.

Programming an 8259 in conjunction with DOS and Microsoft Windows has introduced a number of confusing issues for the sake of backwards compatibility, which extends as far back as the original PC introduced in 1981.

The first issue is more or less the root of the second issue. DOS device drivers are expected to send a non-specific EOI to the 8259s when they finish servicing their device. This prevents the use of any of the 8259's other EOI modes in DOS, and excludes the differentiation between device interrupts rerouted from the master 8259 to the slave 8259.

The second issue deals with the use of IRQ2 and IRQ9 from the introduction of a slave 8259 in the PC/AT. The slave 8259's INT output is connected to the master's IR2. The IRQ2 line of the ISA bus, originally connected to this IR2, was rerouted to IR1 of the slave. Thus the old IRQ2 line now generates IRQ9 in the CPU. To allow backwards compatibility with DOS device drivers that still set up for IRQ2, a handler is installed by the BIOS for IRQ9 that redirects interrupts to the original IRQ2 handler.

In the PC/clone family of platforms, the BIOS (and thus also DOS) traditionally maps the master 8259 interrupt requests (IRQ0–IRQ7) to interrupt vector offset 8 (corresponding to INT 08–INT 0Fh), and when present, the PC/AT’s slave 8259 is mapped to interrupt vector offset 112 (INT 70–INT 77h). This was done despite the first 32 (INT 00-INT 1F) interrupt vectors being reserved by the processor for internal exceptions.

This meant that, on later chips, handlers for lower-numbered vectors needed to differentiate between three causes:

  • faults, exceptions, and traps caused incidentally;
  • interrupts caused by IRQ or NMI, potentially including spurious IRQs; and
  • deliberate calls from software executing INT, breakpoint, or indirect far CALL/JMP instructions, as might be used to interact with the BIOS, operating system, or device drivers.

Because of this, most operating systems that don’t make use of the BIOS will configure the interrupt controller(s) to avoid the reserved vector range entirely. In protected mode, the OS can restrict use of INT instructions to specific vectors only (e.g., Linux exposes INT 80h for system calls), and any attempt to use a disallowed vector will raise a protection fault.

This avoids some of the need for cause determination in interrupt vector handlers, although spurious interrupts and IRQ-sharing can still complicate matters. Fortunately, most peripheral devices can be queried with regards to outstanding IRQs, and if no source can be found an interrupt can be treated as spurious or ignored altogether.

Other operating systems

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Since most other operating systems allow for changes in device driver expectations, other 8259 modes of operation, such as Auto-EOI, may be used. This is especially important for modern x86 hardware in which a significant amount of time may be spent on I/O address space delay when communicating with the 8259s. This also allows a number of other optimizations in synchronization, such as critical sections, in a multiprocessor x86 system with 8259s.

Edge and level triggered modes

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Since the ISA bus does not support level triggered interrupts, level triggered mode may not be used for interrupts connected to ISA devices. This means that on PC/XT, PC/AT, and compatible systems the 8259 must be programmed for edge triggered mode. On MCA systems, devices use level triggered interrupts and the interrupt controller is hardwired to always work in level triggered mode. On newer EISA, PCI, and later systems the Edge/Level Control Registers (ELCRs) control the mode per IRQ line, effectively making the mode of the 8259 irrelevant for such systems with ISA buses. The ELCR is programmed by the BIOS at system startup for correct operation.

The ELCRs are located 0x4d0 and 0x4d1 in the x86 I/O address space. They are 8-bits wide, each bit corresponding to an IRQ from the 8259s. When a bit is set, the IRQ is in level triggered mode; otherwise, the IRQ is in edge triggered mode.

Spurious interrupts

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The 8259 generates spurious interrupts in response to a number of conditions.

The first is an IRQ line being deasserted before it is acknowledged. This may occur due to noise on the IRQ lines. In edge triggered mode, the noise must maintain the line in the low state for 100 ns. When the noise diminishes, a pull-up resistor returns the IRQ line to high, thus generating a false interrupt. In level triggered mode, the noise may cause a high signal level on the systems INTR line. If the system sends an acknowledgment request, the 8259 has nothing to resolve and thus sends an IRQ7 in response. This first case will generate spurious IRQ7's.

A similar case can occur when the 8259 unmask and the IRQ input de-assertion are not properly synchronized. In many systems, the IRQ input is deasserted by an I/O write, and the processor doesn't wait until the write reaches the I/O device. If the processor continues and unmasks the 8259 IRQ before the IRQ input is deasserted, the 8259 will assert INTR again. By the time the processor recognizes this INTR and issues an acknowledgment to read the IRQ from the 8259, the IRQ input may be deasserted, and the 8259 returns a spurious IRQ7.

The second is the master 8259's IRQ2 is active high when the slave 8259's IRQ lines are inactive on the falling edge of an interrupt acknowledgment. This second case will generate spurious IRQ15's, but is rare.

PC/XT and PC/AT

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Main article: Interrupt request (PC architecture)

The PC/XT ISA system had one 8259 controller, while PC/AT and later systems had two 8259 controllers, master and slave. IRQ0 through IRQ7 are the master 8259's interrupt lines, while IRQ8 through IRQ15 are the slave 8259's interrupt lines. The labels on the pins on an 8259 are IR0 through IR7. IRQ0 through IRQ15 are the names of the ISA bus's lines to which the 8259s are attached.

Variants

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Model Number Technology Temperature Range Package Date of Release Price (USD)[list 1]
ID8259 -40 °C to +85 °C[2] March/April 1979[3] $23.15
M8259 Military March/April 1979[4] $95.00
82C59A[5] CMOS July/August 1984
8259 28 Pin PLCC[list 2][6]
  1. ^ In quantities of 100 and up
  2. ^ Sampling Q1 1986

See also

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References

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

Intel 8259

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from Grokipedia
The Intel 8259 is a programmable interrupt controller (PIC) developed by Intel Corporation in 1976 as part of its MCS-85 family of microcomputer components for 8-bit systems. Designed primarily for use with microprocessors like the Intel 8085, it manages up to eight vectored priority interrupts by accepting requests from peripheral devices, resolving priorities according to programmable modes (such as fully nested or rotating), and delivering interrupt vectors directly to the CPU via the data bus. The chip features an interrupt request register (IRR), in-service register (ISR), and interrupt mask register (IMR) to track and control interrupt status, supports individual masking of interrupt lines, and is cascadable to expand capacity to 64 interrupt levels without extra hardware. Fabricated using NMOS technology, it operates on a single +5V power supply, requires no external clock, and is housed in a 28-pin dual in-line package (DIP). In 1979, Intel released the 8259A as an improved variant, adding compatibility with 16-bit processors such as the 8086 and 8088, along with enhanced modes including buffered operation for multi-chip configurations and level-sensitive (as opposed to edge-triggered) interrupt triggering. Fully upward compatible with the original 8259, the 8259A allowed existing software to run unchanged while introducing features like automatic end-of-interrupt (EOI) commands and specific edge/level trigger programming per interrupt line. This version gained prominence in personal computing history through its integration into the original IBM PC motherboard in 1981, where a single 8259A chip provided 8 interrupt request (IRQ) lines, later expanded in the IBM PC/AT using two cascaded chips (one master and one slave) for up to 16 lines, essential for handling inputs from devices like keyboards, timers, and disk controllers. The design's flexibility in priority resolution and vectoring minimized CPU overhead in real-time, interrupt-driven applications, influencing system architectures until the adoption of more advanced controllers like the Intel 8259-compatible APIC in the mid-1990s.

History and Development

Origins and Release

The was developed in the mid-1970s by as a key support component within the MCS-80 and MCS-85 families of systems, specifically to address the limitations of handling in early 8-bit microprocessors like the 8080 and 8085. These families represented Intel's push toward integrated large-scale integration (LSI) solutions for building complete microprocessor-based systems, where the 8259 served as a dedicated peripheral to offload management from the CPU, allowing for more efficient multitasking in resource-constrained environments. Officially released in , the 8259 appeared in Intel's product catalog that year, with initial datasheets and design documentation published to support its integration into development kits and single-board computers. Prior to its widespread adoption in personal computers during the early , the chip was primarily targeted at embedded and industrial applications, marking a shift from discrete logic-based systems to programmable, scalable solutions. Its initial availability aligned with the launch of the in March 1976, enabling rapid prototyping in Intel's Intellec Microcomputer Development System (MDS-800). The primary design motivations for the 8259 centered on providing programmable prioritization in 8-bit systems, where the CPU could only handle a limited number of sources without significant software overhead. It supported up to eight vectored priority interrupt levels, with cascading capabilities allowing expansion to 64 levels through multiple interconnected chips, all while operating on a single +5V supply in a 28-pin DIP package using nMOS technology. This flexibility was essential for real-time systems requiring dynamic reconfiguration of interrupt priorities without hardware changes. Early applications of the 8259 in the late focused on industrial controllers and minicomputers, where it managed interrupts for control, , and I/O operations in environments like chemical production lines, pipeline monitoring, automated test stands, and systems. Integrated into Intel's iSBC single-board computers—such as the iSBC 80/10, 80/20, and 80/30—it facilitated real-time responses in distributed processing networks, gas pump , and early robotic controls, predating use by several years and establishing it as a foundational element in industrial .

Evolution and Adoption

These updates culminated in the 8259A variant, introduced in 1979, which provided upward compatibility while incorporating enhancements such as improved interrupt handling modes (including fully nested, special mask, and automatic end-of-interrupt modes), better support for edge- or level-sensitive inputs, and greater compatibility with the 8086 and 8088 processors, resulting in faster response times and reduced susceptibility to electrical noise in system environments. A pivotal adoption milestone occurred in 1981 with the integration of the 8259A into the Personal Computer (model 5150), where it served as the primary interrupt controller on the system board, managing eight prioritized levels for the 8088 and enabling efficient handling of inputs from peripherals like the timer, keyboard, and expansion cards. This design choice established the 8259A as the for x86 interrupt management in personal , with six of its interrupt lines (IRQ2–IRQ7) routed to I/O slots to support feature cards, thereby facilitating modular system expansion. The 8259A significantly influenced industry standards by enabling vectored interrupts within real-mode environments, which streamlined hardware event prioritization and response in resource-constrained systems. This capability shaped interrupt handling in and early operating systems, allowing software to vector directly to service routines via programmable offsets, a mechanism that became foundational for x86-based multitasking and I/O operations without requiring extensive CPU polling. By the late 1980s, the 8259A and its derivatives had been installed in tens of millions of systems worldwide, including IBM PCs, compatible clones from manufacturers like Compaq and Dell, and various embedded applications, reflecting its pervasive role in the explosive growth of personal computing.

Technical Overview

Purpose and Role in Systems

The Intel 8259 serves as a programmable interrupt controller (PIC) designed to manage hardware interrupts in microprocessor-based systems, acting as an intermediary between peripheral devices and the central processing unit (CPU). Interrupts represent asynchronous events—such as signals from a keyboard, timer, or disk controller—that require immediate CPU attention, temporarily suspending normal program execution to invoke a dedicated service routine. By prioritizing and routing these interrupts to the CPU's interrupt request (INTR) pin, the 8259 ensures timely responses without requiring the CPU to poll devices continuously, thereby improving overall system efficiency and responsiveness. In broader system architectures, the 8259 offloads interrupt management tasks from the CPU, allowing the processor to focus on primary computations while the controller handles prioritization among up to eight lines (IR0 through IR7). It supports flexible schemes such as fixed-priority (fully nested) mode, where IR0 holds the highest priority and IR7 the lowest, or rotating priority mode to equitably distribute servicing in multi-tasking or environments. For scalability in complex systems, the 8259 enables cascading configurations, where a master unit connects to up to eight slave units via a three-line cascade bus, expanding capacity to 64 vectored priority interrupts while maintaining centralized control. The 8259 integrates seamlessly with 8-bit CPUs like the or by asserting the INTR signal upon detecting a pending highest-priority , prompting the CPU to initiate an acknowledge (INTA) . During this cycle, the 8259 releases an 8-bit vector onto the data bus, enabling the CPU to directly address the corresponding service routine in its vector table. This vectored approach, combined with support for edge-triggered inputs, facilitates precise and hardware-efficient dispatching tailored to the system's . Support for 16-bit processors like the 8086/8088, including two-INTA cycles and level-triggered inputs, is provided by the 8259A variant.

Key Features and Specifications

The Programmable Interrupt Controller (PIC) supports up to eight vectored priority interrupts, allowing for efficient management of interrupt requests in microprocessor-based systems. It features programmable priority modes, including fully nested mode for hierarchical prioritization, automatic rotation for , and specific priority for custom priority assignment, enabling flexible handling of interrupt sources. It also supports manual end-of-interrupt (EOI) commands, where software issues specific or non-specific EOI to reset the in-service register; automatic EOI handling is available in the 8259A variant. The device is cascadable, supporting expansion to 64 interrupt levels when multiple 8259 units are chained together without requiring extra logic. Electrically, the 8259 operates on a single +5V supply with a tolerance of 4.5V to 5.5V, housed in a 28-pin (DIP). Its maximum power dissipation is 1W, with an range of 0°C to 70°C (standard); -40°C to 85°C for industrial variants. Input low voltage is specified at a maximum of 0.8V, while input high voltage requires at least 2.0V, ensuring compatibility with standard TTL logic levels. Supply current under normal operation is approximately 85mA, with low input load currents to minimize external component requirements.
ParameterSymbolMinTypMaxUnitNotes
Active Pulse Widtht_JLJH100--nsMinimum duration for IR input
Acknowledge Pulse Width (RD or INTA)t_RLRH / t_ALAL--235nsFor 8259A standard speed
Data Setup Time to Writet_DVWH240--nsData valid before WR falling edge
Interrupt Output Propagation Delayt_JHIH--350nsFrom IR to INT assertion
Data Valid from Read/Acknowledget_RLDV-200-nsAfter RD or INTA rising edge
These timing parameters define the device's interface speed, with propagation delays around 80ns for internal signal paths in typical operations, supporting system clocks up to several MHz without additional buffering. The timings are based on the 8259A; the original 8259 has similar characteristics. Originally designed for NMOS and PMOS microprocessors such as the and 8085, the 8259 integrates seamlessly with these CPUs via mechanisms. The enhanced 8259A variant maintains full compatibility while improving timing margins, and CMOS adaptations like the 82C59A extend its use to low-power applications with reduced dissipation (down to 1mA/MHz) and wider temperature tolerance for industrial environments.

Architecture

Internal Block Diagram

The Intel 8259 Programmable Interrupt Controller features a modular internal designed to manage up to eight interrupt levels efficiently. At its core are several key blocks that handle detection, prioritization, and signaling to the CPU. The Interrupt Request Register (IRR) latches incoming signals from the eight input pins (IR0 through IR7), capturing requests from peripheral devices. The In-Service Register (ISR) tracks that are currently being processed by the CPU, ensuring proper sequencing. A priority resolver, often implemented as a , evaluates the IRR to select the highest-priority based on programmable settings, while interfacing with the ISR to update service status. Control logic oversees initialization, end-of-interrupt (EOI) operations, and overall chip coordination, responding to CPU commands via dedicated control signals. Data flow within the 8259 begins at the IR0–IR7 pins, where external interrupt requests are fed into the IRR for temporary storage. The IRR contents are then scanned by the priority resolver, which determines the active interrupt and generates the interrupt signal on the INT output pin to notify the CPU. Upon CPU acknowledgment via the INTA (interrupt acknowledge) pulses, the priority resolver updates the ISR, and vector information is released through the data bus buffer to the CPU's address/data lines. For cascaded configurations, the master 8259 uses the CAS0–CAS2 output lines to select and address up to seven slave units, allowing expansion to 64 interrupt levels; slaves receive these signals as inputs to identify their role in the hierarchy. Key signals facilitate precise control and integration. The SP/EN pin serves dual purposes: as a slave program input to designate the chip's role in a cascaded system or as an enable for an optional buffer in buffered mode configurations. The A0 address line, combined with chip select (CS), read (RD), and write (WR) signals, deciphers whether the CPU is accessing command registers or status information, routing data bus transactions accordingly. These elements interconnect seamlessly: for instance, the IRR feeds directly into the priority resolver, which in turn links to the ISR and output logic to drive the INT pin, while control logic modulates the entire process based on external commands.

Registers and Programming Model

The Intel 8259 (PIC) employs a register-based accessed through 8-bit I/O ports, where commands are written to control the device's operation and status is read to monitor conditions. In a typical single-PIC setup for an 8086-based , the master PIC uses I/O ports 20h (for ICWs and OCW2/OCW3) and 21h (for OCW1), with writes dedicated to command registers and reads providing access to in-service register (ISR) or register (IRR) status. These registers, including the initialization command words (ICWs) and operation command words (OCWs), configure vectoring, priority handling, and masking, interfacing with internal components like the IRR and ISR to manage up to eight levels. Initialization begins with ICW1, written when address line A0 is low and bit D4 is set to 1, which resets the edge-triggered sense circuit, clears the interrupt mask register (IMR), and sets the priority of (IR) input 7 to level 7. The bit fields of ICW1 are defined as follows:
BitNameFunction
D7-D5ReservedMust be 0
D4Must be 1 to initiate ICW1
D3LTIM1 = Level-triggered mode; 0 = Edge-triggered mode
D2ADI1 = Address interval of 4 bytes; 0 = Address interval of 8 bytes (for 8080/8085 systems)
D1SNGL1 = Single PIC mode; 0 = Cascaded mode (multiple PICs)
D0IC41 = ICW4 required; 0 = No ICW4 needed
ICW2 specifies the 8-bit base address for vectors, providing the upper byte (typically 08h to 0Fh for standard x86 systems) while the lower bits are supplied by the PIC during interrupt acknowledgment. For 8086 mode, bits A11-A8 of the vector are fixed at 0010 (for type 2 ), with the remaining bits derived from ICW2 and the selected IR level. In cascaded configurations (SNGL=0 in ICW1), ICW3 configures the master-slave relationship: the master PIC uses bits D0-D2 to indicate connected slaves (1 for each active slave ID, up to eight), while each slave PIC writes its own 3-bit ID (D0-D2) to identify itself to the master. If IC4=1 in ICW1, ICW4 follows to set advanced modes, with bits including D4 (mPM: 1 for 8086 mode, enabling automatic command word insertion during acknowledge); D3 (SFNM: 1 for special fully nested mode); D2 (BUF: 1 for buffered mode, enabling slave select); D1 (M/S: 1 for master in buffered mode); and D0 (AEOI: 1 for automatic end-of-interrupt). After initialization, the PIC operates via OCWs to manage ongoing interrupt handling. OCW1, written with A0 high, loads the IMR to mask individual IR inputs, where each bit (D0-D7, corresponding to IR0-IR7) set to 1 disables that channel and 0 enables it. OCW2, written with A0 low, controls end-of-interrupt (EOI) processing and priority rotation: bits D7 (R: 1 for rotation on non-specific EOI) and D5 (EOI: 1 to issue EOI) combine with D2-D0 (L2-L0: specific IR level if D6=1 for specific EOI) or D3-D1 for rotation commands like rotate on non-specific EOI (11xx xxx1). OCW3, also with A0 low, enables special modes and status reads: bits D4 (P: 1 for poll command), D3 (RIS: 1 to read ISR on next RD, 0 for IRR), D2 (RR: 1 to read next command register), D1 (ESMM: 1 to enable special mask mode), and D0 (SMM: 1 to set special mask mode). Reading from the command port (A0 low) after OCW3 configuration yields the selected register contents, aiding in interrupt status polling without processor intervention.

Operation

Interrupt Processing Flow

The interrupt processing in the Intel 8259 Programmable Interrupt Controller (PIC) begins when a peripheral device asserts one or more of its lines (IR0 through IR7), which are latched into the corresponding bits of the Interrupt Request Register (IRR). The priority resolver then examines the IRR, the In-Service Register (ISR), and the Interrupt Mask Register (IMR) to determine if the highest-priority pending request is unmasked and not already in service; if so, the corresponding ISR bit is set (or confirmed during acknowledgment), and the 8259 asserts the INT signal to the CPU. This evaluation ensures fixed-priority handling, where IR7 has the highest priority and IR0 the lowest, preventing lower-priority interrupts from overriding active ones. Upon receiving the INT signal, the CPU suspends its current program and issues interrupt acknowledgment pulses (INTA). For the 8086/8088 processors, two INTA pulses are used: the first pulse (falling edge) locks in the interrupt level (in edge-triggered mode) or confirms it (in level-triggered mode) and sets the ISR bit if not already set, while the second pulse prompts the 8259 to place an 8-bit vector on the data bus (D0–D7). The vector is formed by adding the binary-encoded priority level of the interrupting input (0 for IR0 to 7 for IR7) to a programmable 8-bit base address previously loaded into the PIC via Initialization Command Word 2 (ICW2). The CPU then uses this vector to fetch the interrupt service routine address from its vector table and begins execution. In cascaded configurations, where multiple 8259s are chained to expand beyond eight interrupts, the master PIC connects to the CPU, and up to eight slave PICs connect via the master's SP/EN, CAS0–2, and IR lines. During the second INTA cycle, if the interrupting source is a slave, the master asserts the corresponding CAS0–CAS2 lines (derived from its IRR) to select the appropriate slave, which then places its 8-bit interrupt vector on the data bus. The ISR bits in both master and slave are updated accordingly, requiring coordinated end-of-interrupt handling. To conclude interrupt processing and re-enable the interrupt level, an End-of-Interrupt (EOI) command must be issued via Operation Command Word 2 (OCW2). In non-Automatic EOI (AEOI) mode, the software explicitly sends a specific EOI (clearing the ISR bit for a designated level) or non-specific EOI (clearing the highest-priority ISR bit); in AEOI mode, the ISR bit is automatically cleared at the trailing edge of the final INTA pulse. For cascaded setups, EOI commands are sent to both the slave and master to fully release the chain. Error conditions can arise during processing, such as in level-triggered mode where an asserted IR line deasserts before the falling edge of the first INTA pulse; in this case, the 8259 defaults to servicing IR7 as a fallback, potentially leading to spurious handling. Priority conflicts are resolved by the fixed scheme, but unresolved masking or in-service states can lock out valid requests until cleared, though the design minimizes such issues through resolver logic.

Initialization and Configuration

The initialization of the Intel 8259 begins with a mandatory sequence of Initialization Command Words (ICWs) written to its to establish the basic operating parameters. The process starts by writing ICW1 to select the initialization mode, typically using the value 11h for edge-triggered interrupts (LTIM=0), a 4-byte vector interval (ADI=1), cascaded operation (SNGL=0), and requiring ICW4 (IC4=1); this command resets the edge/level sense circuitry, clears the interrupt mask register (IMR), and sets the highest-priority input (IR7) to priority 7. Following ICW1, ICW2 is written to specify the base address of the , such as 08h for systems using the 8086 processor where vectors occupy addresses 08h through 0Fh for the first eight interrupts. If the system employs a cascaded configuration, ICW3 follows to define the master-slave relationships, and finally ICW4 sets environmental options like processor mode, with 01h commonly used for 8086 compatibility (mPM=1, indicating 8086/8088 mode, while disabling auto EOI and other advanced features). After the ICWs establish the foundation, further configuration occurs via Operation Command Words (OCWs) to tailor handling without reinitializing the device. OCW1 is used to set the interrupt mask register, allowing selective enabling or disabling of individual requests (IR0 through IR7) by writing a byte where each bit corresponds to a mask (1=masked/disabled, 0=enabled), thus preventing unwanted from reaching the CPU. OCW3 provides additional setup options, such as enabling automatic rotation of priorities after service (via the rotate on non-specific EOI command in conjunction with OCW2) or activating poll mode (P=1) to allow the CPU to read the highest-priority pending directly from the in-service register instead of generating an . In multi-PIC cascaded systems, the master-slave setup during ICW3 ensures proper hierarchy for up to 64 interrupts across multiple 8259 devices. The master PIC writes ICW3 with bits set to indicate which of its IR lines connect to slaves—for instance, 04h (binary 00000100) if a single slave is attached to IR2—while each slave writes its corresponding ICW3 with a 3-bit ID matching the master's connection, such as 02h (binary 00000010) to identify itself as connected to the master's IR2. This configuration propagates interrupt signals from slaves to the master, which then signals the CPU with a single . A critical aspect of successful initialization is adhering strictly to the ICW sequence, as omitting ICW1 or writing commands out of order—such as sending ICW2 before ICW1—can result in , including failure to recognize subsequent commands or erroneous priority assignments. Once initialized and configured, the 8259 seamlessly integrates into the system's interrupt processing flow, handling incoming requests according to the established priorities and masks.

System Integration

Usage in IBM PC/XT

In the original PC and XT models, the Intel 8259A served as the sole , mapped to I/O ports 20h for command operations and 21h for the interrupt mask register. This single-chip configuration supported eight lines (IRQ0 through IRQ7), with the programming the vector base to offset 08h, resulting in interrupt vectors 08h through 0Fh presented to the 8088 . Standard IRQ assignments included IRQ0 for the system timer via the 8253 PIT, IRQ1 for the keyboard controller, IRQ2 reserved for future expansion, IRQ3 and IRQ4 for secondary and primary serial ports respectively, IRQ5 for the hard in XT models, IRQ6 for the controller, and IRQ7 for the parallel printer port. The 8259A connected directly to the 8088 CPU's INTR pin, operating exclusively in edge-triggered mode with active-high inputs and no cascading to a secondary controller, which limited the system to these eight prioritized interrupts (IRQ0 highest priority, IRQ7 lowest). During hardware reset, the 8259A entered a default state requiring explicit initialization, after which it would assert INTR upon an unmasked IRQ to prompt the CPU for vector information during the interrupt acknowledge cycle. The played a central role in setup during the (POST), initializing the 8259A in ICW1-ICW4 standard mode to establish the vector offset, enable automatic end-of-interrupt (AEOI) where appropriate, and configure the mask for unused lines such as IRQ2 and IRQ5 in base PC configurations. Specifically, the POST routine wrote initialization command words to ports 20h and 21h, tested the controller by temporarily masking all interrupts, and then unmasked essential lines like IRQ0 for the , which the serviced at 18.2 Hz to maintain system timing and support DOS tick counting. This eight-IRQ constraint created significant design challenges for early DOS applications and peripherals, as adding devices like sound cards or network adapters often necessitated IRQ sharing—risking conflicts and requiring careful polling fallbacks—or reconfiguration of existing assignments, which complicated software compatibility and expansion in resource-limited environments.

Usage in PC/AT and Later

The IBM PC/AT, introduced in 1984, expanded the interrupt handling capability of its predecessor by incorporating two Intel 8259A Programmable Interrupt Controllers (PICs) in a cascaded configuration to support up to 15 usable requests (IRQs). The master PIC is mapped to I/O ports 20h (command/control) and 21h (data/mask), while the slave PIC uses ports A0h and A1h. The slave's output connects to the master's IRQ2 input (IR2), effectively cascading the slave's eight IRQs (IRQ8–IRQ15) through this channel, leaving IRQ2 unavailable for direct use and providing a total of 15 functional IRQs. In , the initializes the master PIC vectors to 08h–0Fh (corresponding to IRQ0–IRQ7), and the slave to 70h–77h (IRQ8–IRQ15). This dual-PIC architecture integrated with the microprocessor, which featured enhanced handling compared to the 8088 in earlier models, including support for operations. The 8259As were primarily configured in edge-triggered mode, where are signaled by a rising edge on the input line, suitable for most peripherals like the , keyboard, and serial ports. However, the controllers could be programmed for level-sensitive mode on specific IRQs to accommodate devices such as controllers, which maintain an asserted line until serviced, requiring the input to remain high until the end-of-interrupt (EOI) command. The PC/AT's 8259 configuration became the for x86-compatible systems throughout the 1980s and early 1990s, influencing designs until the introduction of the (APIC) in the mid-1990s with PCI-based systems and multiprocessor support. To ensure compatibility in , where the first 32 interrupt vectors (00h–1Fh) are reserved for CPU exceptions, operating systems typically remap the master PIC's IRQs 0–7 to vectors 20h–27h and the slave's IRQs 8–15 to 28h–2Fh. Software initialization must account for both controllers, often programming the slave first to set its vector offset and cascade identity, followed by the master to avoid spurious s during reconfiguration.

Programming Considerations

Edge vs. Level Triggered Modes

The Programmable Interrupt Controller (PIC) supports two distinct (IRQ) triggering modes: edge-triggered and level-triggered, which determine how signals on the IR0–IR7 inputs are detected and latched into the Interrupt Request Register (IRR). These modes are selected globally for all eight interrupt inputs during initialization via bit 3 (LTIM) of the Initialization Command Word 1 (ICW1): LTIM=0 configures edge-triggered mode, while LTIM=1 configures level-triggered mode. In edge-triggered mode, an is recognized only on a low-to-high (rising) transition of the voltage on an IRx input, after which the corresponding IRR bit is set and remains latched until the is acknowledged and cleared, regardless of subsequent signal changes. This mode is particularly suitable for pulse-based signals from devices such as keyboards, where the keyboard controller generates a brief pulse to signal keypress data availability, ensuring the PIC captures the event without requiring the signal to be held. In contrast, level-triggered mode detects a sustained high (logic 1) level on an IRx input, setting the corresponding IRR bit as long as the input remains high; the IRR bit is cleared only when the input returns low or the is serviced. This configuration is ideal for bus-sharing scenarios or devices like parallel printers that maintain a high signal on the interrupt line until the condition is resolved, such as when print data is ready and the line is held asserted by multiple potential requesters without needing precise timing. However, in level-triggered operation, if the interrupting device does not deassert its signal before the End of Interrupt (EOI) command is issued, the IRR bit may be re-set immediately, potentially causing repeated until software intervention clears the source. The choice between modes involves key trade-offs affecting reliability and design. Edge-triggered mode facilitates line sharing among non-simultaneous devices without latching conflicts, as the is captured on transition alone, but it risks missing if a occurs during PIC servicing or is too brief to detect reliably. Level-triggered mode ensures no missed for persistent conditions, providing robustness for shared buses where devices may assert indefinitely, but it introduces the potential for spurious or repeated if the signal is not properly managed by software polling or device clearing after service. Overall, the IRR latching behavior in each mode—transient capture versus continuous monitoring—directly influences and response in multi-device environments, with configuration locked after ICW1 programming during the standard initialization sequence.

Handling Spurious Interrupts and OS-Specific Issues

Spurious interrupts in the 8259 arise from electrical noise on lines or from uncleared latches within the controller, leading to an erroneous assertion of the INT signal to the CPU without a corresponding valid request. These events typically manifest as a default IRQ7 on the master PIC or IRQ15 on the slave PIC, occurring if an input request (IR) deasserts before the first interrupt acknowledge (INTA) pulse from the CPU. Detection relies on checking the In-Service Register (ISR): if the INT line is asserted but no corresponding ISR bit is set for the interrupting IRQ, the event is spurious, distinguishing it from a genuine IRQ7 where the ISR bit would be active. To mitigate such interrupts, software enables detection via Operation Control Word 3 (OCW3) by setting the Poll Command bit (P=1) to treat the next read as an INTA cycle for status inspection, or by configuring the Read Register bit (RR=1) with the ISR select bit (RIS=1) to read the ISR directly. Clearing follows with a non-specific End-of-Interrupt (EOI) command via OCW2 (EOI=1, SL=0, R=0), which resets the highest-priority ISR bit without specifying an IRQ, preventing lockup while avoiding unnecessary servicing of the phantom . In environments, the initializes the 8259 to map IRQs 0–7 to interrupt vectors 08h–0Fh, with handlers for these vectors implemented as routines that manage device-specific processing, such as timer ticks for INT 08h or operations for INT 0Fh. Spurious interrupts, often manifesting as calls to the IRQ7 handler, are typically handled by a simple return instruction in the handler, issuing a non-specific EOI to clear the PIC without further processing, avoiding system instability in real-mode applications. For Windows 3.x and 95, Virtual Device Drivers (VxDs) operate in and virtualize the 8259 through the (VPICD), which remaps IRQs to avoid conflicts between real-mode DOS sessions and operations. Level-triggered modes, common for ISA devices, are managed by VxDs via VPICD in these systems, while in the family and later, the Hardware Abstraction Layer (HAL) provides management, with VxDs or equivalent intercepting PIC signals, emulating EOI for spurious cases, and routing valid interrupts to the appropriate virtual machine without asserting hardware INT lines unnecessarily. In and systems, the kernel's i8259.c driver detects spurious interrupts during the mask-and-acknowledge phase by verifying masked IRQs (e.g., IRQ7 or IRQ15) against the ISR; if no service bit is set, it logs the event once per IRQ via and increments an error counter without servicing, while supporting auto-EOI mode to automatically clear interrupts without explicit commands. Polling occurs via reads to the PIC command registers to check pending status, enabling efficient mitigation in kernel space.

Variants and Legacy

8259A and Subsequent Revisions

The 8259A, released in 1979 and incorporated into the original PC design in 1981, serves as an enhanced iteration of the original 8259 . It maintains full upward compatibility with the 8259 while introducing the buffered mode, configurable via the BUF bit in Initialization Command Word 4 (ICW4), which repurposes the SP/EN pin as an output to enable buffer transceivers in cascaded configurations. The 8259A also features improved acknowledge (INTA) timing, with data valid from INTA reduced to approximately 50 ns in optimized variants compared to longer delays in the original 8259, alongside refined slave select logic using CAS0–CAS2 lines for more efficient multi-PIC cascading up to 64 levels. These enhancements optimize performance in multi- environments without altering core functionality. Subsequent revisions of the 8259A focused on performance and reliability refinements rather than architectural overhauls. The 8259A-2, released around , targeted higher-speed applications with reduced access times, such as a read (RD) pulse of 160 ns versus 235 ns in the standard 8259A, enabling better integration with faster microprocessors like the 80286. The D8259A variant adhered to military specifications, incorporating robust fabrication processes for operation in extreme conditions while preserving pin-for-pin compatibility. Additionally, the 82C59A revision emphasized power efficiency, achieving standby currents as low as 10 µA maximum and operating currents of 1 mA/MHz, making it suitable for battery-powered or low-power systems; it supports clock speeds up to 12.5 MHz with INTA response times as low as 40 ns. All revisions utilize the same 28-pin (DIP), ensuring seamless for the original 8259. The 8259A family's design facilitated its rapid adoption as the standard interrupt controller in x86-based systems, powering the handling in the PC/XT architecture and subsequent PC clones throughout the .

Modern Relevance and Replacements

Despite its obsolescence in mainstream , the Intel 8259 Programmable (PIC) maintains relevance through emulation in modern x86 environments. In UEFI-based systems, the Legacy 8259 Protocol abstracts control of the 8259 PIC between EFI and legacy BIOS , enabling IRQ remapping for compatibility with older software during boot processes. This support ensures that traditional vectors remain accessible, particularly for real-mode operations required in early boot stages. Additionally, the specification accommodates dual-8259 configurations via the Multiple APIC Description Table (MADT)'s PCAT_COMPAT , mapping Global System Interrupts (GSIs) 0-15 to 8259 IRQs unless overridden, thus preserving legacy handling in hybrid environments. Virtualization platforms continue to emulate the 8259 for compatibility with legacy applications, such as environments. , a widely used , includes support for i8259 PIC emulation alongside IOAPIC and local APIC, allowing kernel-based acceleration for accurate reproduction of behavior in virtual machines. This emulation is essential for tools like , which rely on components to run 1980s-era software that expects 8259-style prioritization and vectoring. The 8259 has been largely replaced by more advanced interrupt mechanisms since the 1990s, particularly in multiprocessor systems. The Intel Advanced Programmable Interrupt Controller (APIC), introduced to support , superseded the 8259 by providing scalable interrupt delivery across multiple CPUs, eliminating the limitations of the 8259's fixed 8-vector cascaded architecture. For PCI devices, (MSI), defined in the PCI 2.2 specification, offer an alternative to traditional line-based interrupts routed through the 8259, using memory writes to signal events directly to the APIC without dedicated pins. In modern Windows environments under , the 8259 is typically disabled once the OS enables APIC mode, with OSPM masking legacy PIC interrupts and routing all events through the I/O APIC to avoid conflicts. The transition away from the 8259 accelerated following the processor's release in 1993, as APIC integration became standard in multiprocessor configurations by the mid-1990s. However, 8259 compatibility remained necessary for real-mode boot processes in -based systems until the widespread adoption of in the 2010s, when began phasing out legacy support—fully removing it in platforms like Ice Lake by 2019. Today, the 8259 persists in niche applications within embedded and retro . In retro projects, FPGA implementations recreate the 8259 for authentic , such as in custom 8-bit systems or FPGA platforms that replicate original PC interrupt logic. Embedded systems occasionally repurpose 8259-compatible designs for low-cost interrupt handling, while hobbyist hacks on platforms like use GPIO to mimic 8259 signaling for interfacing legacy peripherals.

References

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