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Zilog eZ80
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Zilog eZ80
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Zilog eZ80
A square black eZ80 microprocessor sits on a green printed circuit board with other electronic components
eZ80 in a TI-84 Plus CE with 256 KB on-chip RAM
General information
Launched2001[1]
Marketed byZilog
Designed byZilog
Common manufacturer
  • Zilog
Performance
Max. CPU clock rateto 50 MHz
Data width8
Address width24
Architecture and classification
Instruction setZ80[a]
Extensions
  • ADL
History
PredecessorsZilog Z80
Zilog Z180

The Zilog eZ80 is an 8-bit microprocessor designed by Zilog as an updated version of the company's first product, the highly-successful Zilog Z80. The eZ80 is binary compatible with the Z80 instruction set, but it operates almost three times faster at the same clock frequency. eZ80 features an optional mode that expands memory addressing to 16 megabytes.

Design

[edit]
Zilog eZ80 registers in ADL mode
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
0 0 0 0 0 0 0 0 Accumulator (A) Flags (F) AF
BCU B C BC
DEU D E DE
HLU H L HL
Alternate (shadow) registers
0 0 0 0 0 0 0 0 Accumulator' (A') Flags' (F') AF'
BCU' B' C' BC'
DEU' D' E' DE'
HLU' H' L' HL'
Index registers
IXU IXH IXL IX
IYU IYH IYL IY
Stack Pointer SPL
Other registers
Interrupt vector (base) 0 0 0 0 0 0 0 0 I
Memory base 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBASE
  Refresh counter R
Program counter
Program Counter PC
Status flags
  S Z - H - P/V N C Flags
  ADL IEF1 IEF2 MADL Bit flags

The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes the program counter, it flushes the instructions that the CPU is currently processing. Available at up to 50 MHz (2004), the performance is comparable to a Z80 clocked at 150 MHz if fast memory is used (i.e. no wait states for opcode fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16 MB of memory without a memory management unit, by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example, the HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually.[2] Although the eZ80 handles 24-bit math and moves, it only supports 8-bit operations for logic functions such as AND, OR, and XOR.

The processor has a 24-bit arithmetic unit and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike the older Z280 and Z380 it does not have (or need) a cache memory. Instead, it is intended to work with fast SRAM directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times.

The chip has a memory interface that is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256 KB flash memory and 16 KB SRAM) but there are also external buses on all models.

Variants

[edit]

The eZ80 family includes several variants offering different levels of integration. These single-chip computers retain an external address and data bus so they can function as general-purpose microprocessors despite their focus on specific applications.

The eZ80Acclaim! line integrates up to 128 KB of flash memory and 8 KB of SRAM, operating at speeds up to 20 MHz.[3][4]

The eZ80AcclaimPlus! adds an Ethernet controller and TCP/IP stack to the eZ80Acclaim! features, reaching speeds of up to 50 MHz.[5]

Use in commercial products

[edit]

The TI-84 Plus CE graphing calculator utilizes the eZ80 in 24-bit address mode at 48 MHz.[6] The eZ80L92 processor powers the ST Robotics robot controller, running at 50 MHz.[7]

Notes

[edit]

References

[edit]

Further reading

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Zilog eZ80

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from Grokipedia
The Zilog eZ80 is a family of high-performance 8-bit microprocessors developed by as an enhanced successor to the Z80, offering full binary compatibility with Z80 and code while introducing a 24-bit linear (ADL) that expands the addressable memory space to 16 MB. Introduced in as part of the eZ80Acclaim! product line, the eZ80 features a pipelined with single-cycle instruction fetch, enabling clock speeds up to 50 MHz and performance of up to 25 MIPS—approximately four times faster than the original Z80 at equivalent clock rates—through optimizations like reduced cycle times for common instructions (1–7 cycles in Z80 mode and 3–5 cycles in ADL mode). Its instruction set is a superset of the Z80's, incorporating over 600 instructions including arithmetic, logical, , and block transfer operations, plus unique additions such as a 16-bit multiply (MLT) instruction and extended I/O commands like INIRX for efficient data handling. The eZ80 supports flexible addressing modes, including immediate, register indirect, indexed (using IX/IY registers with displacement), relative, and extended 24-bit formats, allowing seamless mixing of legacy 16-bit Z80 code with new 24-bit applications via the MBASE register for memory paging. Integrated into various microcontroller variants, such as the eZ80F91 Ethernet MPU with 256 KB on-chip Flash, 8 KB SRAM, and 10/100 Base-T connectivity, or the eZ80L92 Flash MCU for compact embedded designs, the family targets applications in networking, industrial control, and Internet-connected devices requiring low-power efficiency and 32 general-purpose I/O pins.

Overview

Development and Release

The Zilog eZ80 was introduced in April 2001 as a direct successor to the original Z80 microprocessor, marking 's effort to extend the architecture's relevance in evolving embedded systems. Developed to overcome the Z80's constraints in speed and memory addressing for contemporary applications, the eZ80 maintained full binary compatibility with its predecessor while introducing enhancements like a pipelined design and support for up to 16 MB of linear . This was driven by the need to support networked and communication-intensive tasks, such as serving web pages over TCP/IP for remote monitoring and control, thereby revolutionizing how embedded devices interacted with the era. Initial production and announcement occurred in , with the eZ80 positioned as a system-on-a-chip solution tailored for cost-sensitive markets requiring reliable 8-bit processing. Zilog emphasized the eZ80's role within the broader Z80 family extensions, aiming to prolong the ecosystem's longevity amid the shift toward more complex, connected embedded applications. By preserving the Z80's instruction set, the eZ80 allowed developers to leverage decades of existing software and tools without redesign, facilitating seamless upgrades in industrial and consumer devices. A key milestone came in 2004, when released variants of the eZ80 capable of operating at up to 50 MHz clock speeds, significantly boosting performance for demanding embedded tasks while upholding compatibility. This upgrade reflected Zilog's ongoing commitment to refining the for higher throughput in memory-intensive environments, solidifying the eZ80's place as a bridge between legacy 8-bit systems and modern requirements.

Compatibility and Improvements over Z80

The eZ80 maintains full binary compatibility with the original Z80 microprocessor, enabling seamless execution of existing Z80 software without modification or recompilation. This upward compatibility extends to the Z80 instruction set, including all opcodes, registers, and addressing modes in Z80 mode, allowing the eZ80 to serve as a in legacy systems such as embedded controllers and classic applications. Zilog's documentation confirms that Z80 and Z180 programs run directly on the eZ80 with minimal adjustments, preserving the vast ecosystem of Z80 code developed over decades. Key enhancements over the Z80 focus on performance and memory capabilities while retaining core architectural fidelity. At the same clock frequency, the eZ80 executes instructions up to four times faster than the Z80, primarily due to an optimized three-stage instruction pipeline (fetch, decode, execute) that overlaps operations, enabling a throughput of one instruction per cycle for many common instructions and reducing overall cycle counts. For instance, operations like load and arithmetic instructions that take multiple cycles on the Z80 benefit from this efficiency, achieving effective speeds equivalent to a Z80 running at four times the in typical workloads. Additionally, the eZ80 introduces 24-bit addressing in its Address Load (ADL) mode, expanding the addressable memory from the Z80's 64 KB limit to 16 MB, which supports larger codebases and data structures in modern embedded designs without requiring segmented . The eZ80 supports dynamic mode switching between Z80 mode (16-bit addressing for legacy compatibility) and ADL mode (24-bit addressing for extended capabilities), facilitated by instruction suffixes such as .S for Z80 mode and .L for ADL mode, or persistent changes via jumps and calls. This dual-mode operation allows developers to mix legacy Z80 code with enhanced routines, using the Z80 mode's 16-bit stack pointer (SPS) for backward-compatible stacks and the ADL mode's 24-bit stack pointer (SPL) for larger memory operations, all without introducing new instructions—only extended register interpretations. Furthermore, the eZ80's architectural improvements yield lower power consumption per instruction compared to the Z80 at equivalent speeds, as the enhanced and efficiency reduce the energy required for computation, enabling better battery life in power-constrained applications.

Architecture

Instruction Set and Addressing Modes

The eZ80 retains the complete Z80 instruction set, comprising 158 instructions that encompass 8-bit logic operations, 16-bit arithmetic, and capabilities, ensuring full binary compatibility with existing Z80 software. This set includes the original Z80's arithmetic, logical, data transfer, and control instructions, with no new opcodes added to maintain seamless legacy support. However, the eZ80 enhances execution efficiency through optimized internal paths, notably enabling single-cycle instruction fetches in its extended , which reduces overhead compared to the original Z80's multi-cycle fetches. A key architectural feature of the eZ80 is its dual addressing modes, which balance with expanded access. In Z80 mode, the processor operates with 16-bit addressing, limiting the to 64 KB as in the original Z80, suitable for legacy applications. Conversely, Address Large (ADL) mode extends this to 24-bit addressing, supporting a 16 MB via banked segments, allowing modern embedded systems to handle larger code and data requirements without altering core program logic. Mode selection is controlled by a dedicated mode bit (MADL) in the CPU state or through instruction suffixes—.S for Z80 mode and .L for ADL mode—enabling dynamic switching within software. Memory banking is supported in Z80 mode via the 8-bit register, which selects among 256 banks of 64 KB each to extend the to 16 MB while maintaining compatibility. In ADL mode, the processor uses direct 24-bit linear addressing for the full 16 MB space without banking. To support these modes, the eZ80 includes specialized instructions for efficient operations across banks, such as LDIRX, LDDRX, and similar extended block transfer variants that handle inter-bank data movement with automatic . Conditional execution instructions can also depend on the current mode, allowing code to branch or adapt based on whether Z80 or ADL addressing is active, thereby optimizing performance in mixed-mode environments while upholding Z80 instruction semantics.

Registers and Data Processing

The eZ80 retains the Z80's register architecture for compatibility while introducing extensions for enhanced performance, particularly in its Address Long (ADL) mode that supports 24-bit operations. The core consists of eight 8-bit general-purpose registers in the main set: the accumulator A and the pairs B/C, D/E, H/L, which can be accessed individually or as 16-bit pairs BC, DE, and HL. An alternate register set (A', B', C', D', E', H', L', and corresponding pairs BC', DE', HL') provides a duplicate for rapid context switching, preserving Z80 compatibility through instructions like EX and EXX that swap the main and alternate sets. In ADL mode, these registers extend to 24 bits via upper-byte extensions: for example, the HL pair becomes a 24-bit register by appending HLU (the high-order byte) to form H L HLU, similarly for BCU with BC and DEU with DE. The index registers IX and IY, along with their alternate counterparts IX' and IY', also extend to 24 bits in ADL mode using IXU and IYU upper bytes, enabling indexed addressing across a 16 MB linear . The stack pointer SP operates as a 16-bit register (SPS) in Z80 but switches to a 24-bit register (SPL) in ADL mode, adjusting stack operations like PUSH and POP to handle 3-byte entries instead of 2-byte ones. The ADL mode is controlled by a dedicated mode bit in the CPU state, set via instructions such as SETMIX (to enable ADL) or RSMIX (to disable it), which dynamically alters register widths and addressing behavior without residing in the . The flags register F (and its alternate F') mirrors the Z80 design with six active bits: S (sign), Z (zero), H (half-carry), P/V (parity/overflow), N (add/subtract), and C (carry), updated by arithmetic, logical, and bit operations; bits 3 and 5 remain unused for compatibility. Data processing occurs through an 8-bit external data path but leverages a 24-bit internal arithmetic logic unit (ALU) capable of handling operands in 8-bit, 16-bit, or 24-bit formats, depending on the mode. Core arithmetic instructions include ADD, SUB, ADC, and SBC for addition and subtraction (with carry options), which operate on the extended registers in ADL mode while setting the N flag to 0 for addition and 1 for subtraction; multiplication is supported via the MLT instruction, performing an 8-bit by 8-bit operation to yield a 16-bit result stored in the HL pair. These operations prioritize efficiency in extended modes, allowing seamless transitions between 16-bit Z80-compatible processing and 24-bit computations for larger data handling. Interrupt handling follows Z80 semantics, using the stack for saving PC and flags during maskable (IM 0, 1, or 2) or non-maskable . The alternate register set can be used by software for additional context switching if needed. In vectored interrupt mode (IM 2), the 8-bit I register is combined with an 8-bit external or on-chip vector to form a 16-bit pointer into a jump table, but in ADL mode, this resolves to full 24-bit addresses for the interrupt service routine entry point. The RETI and RETN instructions restore the and flags from the stack while signaling the end of the .

Design Features

Pipeline and Performance

The eZ80 employs a three-stage comprising fetch, decode, and execute stages, which overlaps instruction processing to enhance throughput. The fetch stage retrieves opcodes from in a single cycle when using the Address Large (ADL) mode, while the decode stage interprets instructions and the execute stage performs ALU operations, accesses, and other tasks. This design flushes the on program counter changes, such as jumps or interrupts, but minimizes stalls in sequential execution. Although the eZ80 lacks an on-chip data cache, it supports zero-wait-state operation with fast external SRAM, optimizing performance for embedded systems. Clock speeds for the eZ80 reach up to 50 MHz in standard configurations, providing a substantial boost over the original Z80's typical 4–20 MHz range. At equivalent clock frequencies and with zero-wait-state , the eZ80 achieves up to four times the execution speed of the Z80, thanks to its pipelined , wider opcode decoding, and reduced internal latencies. This efficiency stems from architectural enhancements like single-cycle multiply-accumulate operations and streamlined addressing modes, yielding effective performance comparable to higher-clocked Z80 systems in optimized environments. Throughput improvements are evident in the eZ80's ability to rival 16-bit microprocessors in processing power, with the enabling up to four times the Z80's speed at the same clock due to fewer wait states and broader instruction handling. For instance, common instructions like ADD A, r complete in one cycle, while block transfers benefit from pipelined prefetching. These gains support embedded workloads without exhaustive details, focusing on reliable, low-latency operation. Power consumption remains low for embedded applications, typically ranging from 100 to 200 mW at 50 MHz and 3.3 V supply, varying with wait states (0–7) and active peripherals—e.g., around 40 mA (132 mW) in minimal configurations without cooling requirements. This efficiency arises from the optimized pipeline and 8/16/24-bit selectable data widths, balancing performance and energy use.

Memory Interface and Peripherals

The eZ80 microprocessor maintains Z80 compatibility in its external memory bus interface while extending it to support 24-bit addressing for up to 16 MB of addressable space, utilizing an 8-bit data bus with a separate 24-bit address bus. This bus structure allows seamless integration with legacy Z80 peripherals and memory, with the addition of an 8-bit MBASE register that prepends bank selection in Z80 mode to enable dynamic switching across 256 individual 64 KB memory banks without interrupting CPU execution. In ADL mode, the bus operates with full 24-bit linear addressing, leveraging extended registers like the 24-bit program counter (PC) and stack pointer (SP) for direct access to the entire memory range. The memory interface includes four programmable chip selects (CS0 through CS3), each configurable for ROM, RAM, or I/O regions on 64 KB or 256-byte boundaries, providing glueless external memory support with priority ordering (CS0 highest). Each features an independent wait-state generator capable of inserting 0 to 7 wait states to accommodate slower external memories or peripherals, and an external WAIT input pin allows further timing adjustments. Integrated variants of the eZ80, such as those in the eZ80Acclaim family, incorporate up to 256 KB of on-chip and 16 KB of SRAM, which can be relocated within the 16 MB space using upper address registers, enhancing system integration while preserving the core's external bus flexibility. For I/O operations, the eZ80 provides a dedicated 64 KB I/O port space addressed via 16-bit port numbers, accessible through Z80-compatible IN, OUT, and TSTIO instructions using registers like BC or DE for indirect addressing. Microcontroller implementations optionally include a DMA controller to handle block transfers between memory and peripherals, such as Ethernet MAC buffers, bypassing the CPU core for efficient data movement. Additional optional peripherals in these variants encompass two UARTs supporting rates up to 115.2 kbps with 16-byte FIFOs and IrDA compatibility, four 16-bit timers for PWM and capture functions, and up to 32 GPIO pins configurable for with capabilities. Bus employs standard Z80-derived BUSREQ and BUSACK signals, enabling external masters like DMA controllers to request bus control after the current instruction completes, with priority given to the CPU over and DMA requests to minimize execution stalls. handling integrates with this , using vectored modes (0, 1, or 2) and separate 16-bit or 24-bit stack pointers depending on the , ensuring low-latency response without prolonged bus contention.

Variants

eZ80 Core Microprocessors

The eZ80 core microprocessors represent Zilog's standalone CPU offerings based on the eZ80 architecture, designed for integration into custom systems requiring high-performance 8-bit processing without extensive on-chip peripherals. These variants emphasize the core's enhanced capabilities, including up to 50 MHz operation and support for both 16-bit Z80-compatible addressing (64 KB space) and 24-bit ADL mode (16 MB linear addressing), while targeting flexible board-level designs. The basic eZ80, exemplified by the eZ80190 variant, functions as a pure CPU core operating at up to 50 MHz with minimal on-chip resources, including 8 KB high-speed data SRAM and no integrated , making it suitable for custom designs where external memory and peripherals are provided. It includes essential features like 32 general-purpose I/O pins, six counter/timers, and a , but focuses on core execution efficiency with single-cycle instruction fetches. The eZ80190 is housed in a 100-pin LQFP package and operates on a 3.3 V core supply with 5 V tolerant I/O pins. Development for eZ80 core microprocessors is supported by Zilog's ZDS II IDE, which provides assembly and compiler tools, along with JTAG-based debugging via the Zilog Debug Interface (ZDI) for real-time code execution and breakpoints. These tools enable seamless programming in both Z80 and ADL modes, with assemblers supporting directives like .ASSUME ADL for 24-bit addressing.

eZ80Acclaim Microcontroller Families

The eZ80Acclaim! family comprises a series of flash-based microcontrollers built around the eZ80 core, designed as complete system-on-chip (SoC) solutions for embedded applications requiring integrated memory and peripherals. These devices emphasize power efficiency and compatibility with legacy Z80 code while extending addressable memory to 16 MB in native mode. Representative models include the eZ80F92 and eZ80F93, which feature 128 KB of on-chip flash memory and 8 KB of SRAM, operating at up to 20 MHz. The eZ80L92 is a compact variant operating at up to 50 MHz with 24 general-purpose I/O pins, two UARTs, SPI and I²C interfaces, IrDA support, six 16-bit counter/timers, a real-time clock, and a watchdog timer, housed in a 100-pin LQFP package with a 3.0–3.6 V supply and 5 V tolerant inputs, targeted at low-power embedded designs such as industrial control and communication devices. Higher-end variants like the eZ80F91 provide 256 KB flash and 16 KB SRAM (including dedicated Ethernet buffer space) at speeds up to 50 MHz. The eZ80AcclaimPlus! line builds on the eZ80Acclaim! foundation, enhancing connectivity for networked embedded systems through pre-integrated software and hardware optimizations. Centered on the eZ80F91, it supports up to 50 MHz operation with 256 KB flash and 16 KB SRAM, incorporating a full TCP/IP (ZTP) that includes IPv4, TCP, UDP, HTTP, and DHCP for streamlined / enablement. The 10/100 Base-T Ethernet MAC with interface enables direct connection to PHY transceivers, reducing external component needs. Common peripherals across the families include two UARTs with multidrop support, dual ports (up to 400 kbps), SPI interfaces, and multi-channel PWM timers for motor control and signal generation. Additional features encompass a (RTC), , and up to 32 general-purpose I/O pins, many 5V-tolerant. Low-power modes such as HALT (reducing current to ~75 mA at 50 MHz) and SLEEP (~2.5 µA with voltage brown-out disabled) facilitate battery-operated designs, with selective peripheral shutdown for further optimization. Targeted at automotive, networking, and sectors, these support applications like industrial automation, point-of-sale systems, and facility monitoring. All devices in the family are RoHS compliant, with lead-free packaging introduced in production models since 2006.

Applications

Commercial Products

The TI-84 Plus CE , released in 2015, incorporates the eZ80 running at 48 MHz in Address and Data Long (ADL) mode to support advanced features such as a full-color 320x240 display and access to up to 16 MB of addressable memory. This configuration allows for enhanced graphical rendering and larger program storage compared to earlier Z80-based models in the TI-84 series. The adoption of the eZ80 in these calculators marked a key transition from the original Z80 processor in TI's graphing lineup, enabling higher performance in consumer education tools while preserving through TI's customized , which optimizes use of the eZ80's extended 24-bit registers.

Embedded and Industrial Uses

The eZ80 and its derivatives, such as the eZ80Acclaim family, have been adopted in professional embedded systems where with Z80 code ensures reliable operation in legacy environments. These devices excel in applications requiring high performance within an 8-bit , including industrial and control systems, due to their pipelined and support for up to 24-bit addressing modes. The eZ80F92 and eZ80F93 microcontrollers, for instance, feature integrated peripherals like UARTs, timers, and an external bus interface that facilitate real-time processing in demanding embedded scenarios. In industrial settings, the eZ80 powers legacy upgrades for systems such as HVAC controllers and printers, where cost-effective enhancements to existing Z80-based infrastructure are needed without extensive redesign. The eZ80AcclaimPlus variants, including the eZ80F91, are particularly prominent in networking modules, integrating an Ethernet MAC and support for the Zilog TCP/IP (ZTP) protocol stack to enable TCP/IP connectivity in embedded devices. This makes them suitable for industrial communication gateways that bridge serial interfaces to Ethernet networks, supporting protocols like HTTP and SMTP for remote monitoring and control. Additional applications include vending machines, point-of-sale (POS) terminals, security systems, and automation. Despite the shift toward more advanced architectures, the eZ80 remains common in 8-bit embedded niches, with maintaining production for cost-effective IoT gateways in industrial deployments as of 2024. Its variants' peripherals, like multiple UARTs and IrDA support, further enable these reliable, low-power uses in harsh environments.

Current Status

Production and Availability

The Zilog eZ80 family has remained in active production as of 2025, with —acquired by in 2018—continuing manufacturing for embedded applications despite the end-of-life (EOL) status of select models. For instance, certain variants of the eZ80L92 were transitioned to EOL due to low demand, as announced in Product Change Notification ZAC25-0066 dated October 20, 2025, affecting specific part numbers such as EZ80L92AZ020SG, EZ80L92AZ050EG, and EZ80L92AZ050SG, with last-time-buy orders accepted until January 20, 2026, and shipments continuing through April 20, 2026. though distributors like continued stocking remaining inventory into the 2020s. Broader eZ80 offerings, such as the eZ80F91 and eZ80F92, persist as active products on Littelfuse's portfolio, supporting legacy upgrades from the classic Z80 line. As of 2025, eZ80 components are widely available through major distributors for legacy support and new designs in niche 8-bit systems. and report in-stock quantities for key SKUs like the EZ80L92AZ050SG and EZ80F920200ZCOG, with pricing starting around $9-16 per unit and no immediate stockouts noted. maintains production of select eZ80 SKUs, positioning them as drop-in alternatives to discontinued Z80 parts, while recommending Z8 Encore! or other families for new projects requiring similar functionality. The eZ80 supply chain faced challenges from the 2020-2023 global semiconductor shortage, which impacted 8-bit microcontrollers broadly, leading to lead times of up to 52 weeks for comparable devices from suppliers like Microchip and in 2023. Zilog products experienced similar delays, with distributor reports indicating extended waits for eZ80 orders during peak shortage periods, though stabilization occurred by late 2024 as capacity increased. By 2025, lead times have normalized to 10-14 weeks on average for remaining eZ80 inventory. No full discontinuation of the eZ80 line has been announced as of November 2025, with emphasizing its role in the long-term 8-bit embedded market for industrial controls and IoT edge devices. Ongoing availability through authorized channels ensures continued support for existing deployments, driven by demand in legacy systems.

Legacy and Emulation

The eZ80's legacy endures through software emulation projects that enable testing and preservation of Z80-compatible on modern platforms. A notable example is the Rust-based ez80 crate, an extending the iz80 Z80 emulator to support eZ80 instructions, which successfully passes the comprehensive ZEXALL instruction for verifying Z80 and eZ80 behavior. This tool facilitates development and debugging of eZ80 software without dedicated hardware, contributing to the processor's accessibility in contemporary programming environments. Community-driven initiatives further highlight the eZ80's role in retro computing revival. Hackaday projects, such as the 2024 eZ80 CPU module for the RC2014 modular computer platform, integrate the eZ80 with legacy Z80 bus standards, allowing seamless upgrades in vintage-style systems while leveraging the eZ80's enhanced addressing and speed. These efforts support running classic operating systems like directly on eZ80 hardware, as demonstrated by compact systems such as the Min-eZ, a 50 MHz eZ80-based board executing unmodified Z80 applications with modern peripherals like storage. Similarly, the eZ80's backward compatibility enables emulation and execution of software in community setups, preserving 1980s-era games and programs through Z80 instruction support. The eZ80 bridges decades-old Z80 codebases to 21st-century hardware, aiding the migration of industrial from obsolete systems. Its multiple addressing modes, including Z80-compatible 16-bit operation alongside 24-bit ADL mode, allow developers to port legacy Z80 or Z180 applications with minimal modifications, often by simply recompiling or adjusting mappings. This capability has proven valuable in embedded applications where long-term reliability demands continuity with 1970s-era software stacks. Modern integrations extend the eZ80's influence via FPGA implementations and open-source development tools for high-performance retro computing. FPGA-based Z80-compatible cores, adaptable to eZ80 extensions, power accelerated emulators for retro PCs, enabling high-speed execution of vintage software while maintaining instruction-level fidelity. Open-source assemblers and IDEs, such as the multiplatform eZ80 development toolkit and SPASM-ng, provide robust support for eZ80 assembly programming, fostering ongoing experimentation and in retro and embedded domains.

References

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  31. https://hackaday.io/project/196330-ez80-cpu-for-rc2014-and-other-backplanes
  32. https://www.tindie.com/products/circlem/min-ez-a-small-50-mhz-ez80-cased-system/
  33. https://www.edn.com/implementing-mixed-memory-modes-on-the-ez80-cpu/
  34. https://www.chibiakumas.com/ez80/ez80DevTools.php
  35. http://ez80.readthedocs.io/en/latest/tutorial/intro.html
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