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AMD K6-2
AMD K6-2
AMD K6-2
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K6-2
General information
LaunchedMay 28, 1998
DiscontinuedEnd of 2003[1]
Common manufacturer
Performance
Max. CPU clock rate200 MHz to 570 MHz
FSB speeds66 MHz to 100 MHz
Cache
L1 cache64 KiB
Architecture and classification
Technology node250 nm
MicroarchitectureK6
Instructionsx86
Extensions
Physical specifications
Cores
  • 1
Sockets
Products, models, variants
Core names
  • Chomper
  • Chomper Extended
History
PredecessorK6
SuccessorsK6-III, Duron
AMD K6-2 266 MHz

The K6-2 is an x86 microprocessor introduced by AMD on May 28, 1998,[2] and available in speeds ranging from 266 to 550 MHz. An enhancement of the original K6, the K6-2 introduced AMD's 3DNow! SIMD instruction set and an upgraded system-bus interface called Super Socket 7, which was backward compatible with older Socket 7 motherboards. It was manufactured using a 250 nanometer process, ran at 2.2 volts, and had 9.3 million transistors.

History

[edit]
The AMD K6-2 architecture.
Die shot of an AMD K6-2 500AFX processor

The K6-2 was designed as a competitor to Intel's flagship processor, the significantly more expensive Pentium II. Performance of the two chips was similar: the previous K6 tended to be faster for general-purpose computing, while the Intel part was faster in x87 floating-point applications. To battle the Pentium II's dominance on floating point calculations the K6-2 was the first CPU to introduce a floating point SIMD instruction set (dubbed 3DNow! by AMD), which significantly boosted performance. However programs needed to be specifically tailored for the new instructions and despite beating Intel's SSE instruction set to market, 3DNow achieved only limited popularity.

Super Socket 7, which increased the processor bus from 66 MHz to 100 MHz, allowed the K6-2 to withstand the effects of ever-increasing CPU multipliers fairly gracefully and in later life it remained surprisingly competitive. Nearly all K6-2s were designed to use 100 MHz Super Socket 7 mainboards, allowing the system-bus to keep pace with the K6-2's clock-frequency.

The K6-2 was a very financially successful chip and enabled AMD to earn the revenue it would need to introduce the forthcoming Athlon. The introductory K6-2 300 was by far the best-selling variant. It rapidly established an excellent reputation in the marketplace and offered a favorable price/performance ratio versus Intel's Celeron 300A. While the K6-2 had mediocre floating-point performance compared to the Celeron, it offered faster system RAM access (courtesy of the Super 7 mainboard), as well as 3DNow graphics extensions.

As the market moved on, AMD released a long series of faster K6-2 parts, the best-selling ones being the 350, 400, 450, and 500. By the time the 450 and the 500 were mainstream parts, the K6-2 family had already moved to the budget PC segment, where it still competed successfully against Intel's Celeron.

K6-2+

[edit]

Despite the name, the little-known K6-2+ was based on the AMD K6-III+ design (model 13) with 128 KiB of integrated L2 cache and built on a 0.18 micrometre process (essentially a K6-III+ with half the L2 cache). The K6-2+ was specifically designed as a low-power mobile CPU. Some motherboard companies such as Gigabyte and FIC provided BIOS updates for their desktop motherboards to allow for usage of these processors; for other officially not supported mainboards, the community created unofficial BIOS updates on their own.[3][4]

Most K6-2+ motherboards did not support a clock multiplier setting greater than 5.5 since 550 MHz was the highest official speed of the K6-2+ (100*5.5 = 550) but a little known feature of both the K6-2 and K6-2+ was that it interpreted the motherboard clock multiplier setting 2 as 6. This allowed many users to run their K6-2+ 550 MHz and often even a K6-2+ 500 MHz at a speed of 600 MHz simply by setting the motherboard clock multiplier to 2.[5]

Features

[edit]

Models

[edit]

K6-2 (Chomper, 250 nm)

[edit]
AMD K6-2 Microprocessor
AMD K6-2, Chomper-XT.
AMD-K6-2 with integrated heat spreader removed
  • Package number: 26050
  • CPUID: Family 5, Model 8, Stepping 0
  • L1-Cache: 32 + 32 KiB (Data + Instructions)
  • MMX, 3DNow!
  • 9.3 million transistors
  • Super Socket 7
  • Front-side bus: 66, 100 MHz
  • VCore: 2.2V
  • First release: May 28, 1998
  • Manufacturing process: 250 nm
  • Clockrate: 233, 266, 300, 333, 350 & 366 MHz

K6-2 (Chomper Extended (CXT), 250 nm)

[edit]
  • Package number: 26351
  • CPUID: Family 5, Model 8, Stepping 12
  • L1-Cache: 32 + 32 KiB (Data + Instructions)
  • MMX, 3DNow!
  • Super Socket 7
  • Front-side bus: 66, 95, 97, 100 MHz
  • VCore: 2.0(mobile)/2.2/2.3/2.4V
  • First release: November 16, 1998
  • Manufacturing process: 250 nm
  • Clockrate: 200, 233, 266, 300, 333, 350, 366, 380, 400, 427.5, 450, 475, 500, 533 & 550 MHz

References

[edit]

Further reading

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

AMD K6-2

View on Grokipedia
from Grokipedia
The is a family of 32-bit x86 microprocessors developed by Advanced Micro Devices (AMD) and introduced in mid-1998 as an evolutionary upgrade to the original K6 processor, featuring integrated support for MMX instructions and the new 3DNow! SIMD extension for enhanced floating-point multimedia and 3D graphics performance. Built on a 0.25-micrometer process with 9.3 million transistors, it operates at clock speeds ranging from 266 MHz to 550 MHz, uses a 321-pin Ceramic Pin Grid Array (CPGA) package, and is compatible with and Super7 platforms supporting speeds up to 100 MHz. The K6-2 employs a 6-issue superscalar RISC86 with 10 parallel execution units, , , and an 8192-entry branch prediction table achieving over 95% accuracy, enabling efficient handling of x86 instructions through decoupled decode and execution pipelines. Its on-chip cache consists of 64 KB of L1 memory (32 KB instruction and 32 KB dual-ported data, both 2-way set-associative with 32-byte lines and MESI coherency), alongside a 64-entry instruction TLB and 128-entry data TLB for supporting up to 4 GB of physical address space via 4 KB or 4 MB pages. The integrated /854-compatible and 3DNow! extensions allow up to four single-precision floating-point operations per clock cycle across eight 64-bit MMX/3DNow! registers, with instructions like PFADD, PFMUL, and PFRSQRT optimized for and video decoding. Power management includes states such as Stop Grant, Stop Clock, and Halt, with core voltages of 2.2 V (standard) or 1.9 V (low-power variants) and dissipation up to 18.4 W at higher speeds. Released amid intense competition with Intel's , the K6-2 quickly gained market traction by July 1998, with major OEMs like , , and announcing desktop systems based on it, contributing to 's record sales and return to profitability later that year through rapid adoption in Windows-compatible PCs. Its design emphasized with existing motherboards, allowing cost-effective upgrades without new hardware, while the 3DNow! technology provided a performance edge in graphics-intensive applications over Intel's MMX-only at similar price points. By late 1998, had shipped millions of K6 family processors, exceeding $1.25 billion in revenue, with the K6-2 playing a pivotal role in 's strategy to challenge Intel's dominance in the sub-$1,000 PC segment. Variants like the K6-2+ (introduced in 2000 on a 0.18-micrometer process with 128 KB L2 cache) extended the line's lifespan for mobile and embedded uses, but the original K6-2 remained notable for bridging the late 1990s transition from to architectures.

Development and Release

Background and Origins

The served as the direct predecessor to the K6-2, having been introduced in April 1997 as a 32-bit x86-compatible processor derived from the NexGen Nx686 core, which included support for Intel's MMX multimedia instructions but lacked dedicated enhancements for 3D graphics processing. This design stemmed from AMD's acquisition of NexGen Microsystems, announced in October 1995 and completed in January 1996 for $857 million in stock, a move that integrated NexGen's advanced superscalar architecture—featuring , speculative instruction handling, and up to four instructions retired per cycle—into AMD's product lineup, ultimately leading to the rebranding and refinement of the Nx686 as the K6 to bolster AMD's competitiveness in the x86 market. The development of the K6-2 was primarily motivated by the need to counter Intel's , launched in May 1997 with its proprietary interface that required expensive new motherboards and increased system costs for consumers. In response, focused on enhancing the K6 lineage to deliver cost-effective upgrades compatible with existing platforms, while prioritizing improved multimedia performance to appeal to budget-conscious users in the growing PC market. This strategy allowed to extend the life of the affordable Super Socket 7 ecosystem without the transition expenses associated with Intel's newer form factors. Internally, the K6-2 core was codenamed "Chomper," reflecting its evolutionary refinements over the original K6 design. Amid AMD's financial difficulties in the mid-1990s, characterized by repeated quarterly losses due to production challenges and intense competition, the K6-2 was positioned as a critical product to generate revenue and stabilize the company, ultimately providing the resources necessary to fund the development of the subsequent (K7) architecture.

Launch and Production Timeline

The was officially launched on May 28, 1998, during the Electronic Entertainment Expo in , with initial models available at clock speeds of 266 MHz and 300 MHz. These entry-level variants targeted the budget PC segment, offering compatibility with existing motherboards while introducing enhancements for multimedia workloads. A key highlight of the launch was the integration of 3DNow! technology, a set of SIMD instructions designed to accelerate 3D graphics and processing, positioning the K6-2 as a cost-effective alternative to higher-end competitors. Production ramped up quickly following the announcement, with emphasizing the processor's performance in gaming and entertainment applications through targeted marketing. On November 16, 1998, AMD expanded the K6-2 lineup with the introduction of the Chomper Extended (CXT) core revision, which supported higher clock speeds reaching up to 550 MHz in later iterations. This update enabled models such as the 366 MHz, 380 MHz, and 400 MHz variants, broadening the family's appeal for mid-range systems. Manufacturing volumes peaked during 1999 and 2000, driven by strong market adoption, with popular speeds including 300 MHz, 350 MHz, 400 MHz, 450 MHz, and 500 MHz accounting for the majority of sales. AMD shipped over 8.5 million K6-2 units in 1998 alone, with unit volumes more than doubling in the first half of 1999 compared to the prior year amid surging demand for affordable processors. However, rapid growth led to supply chain challenges in 1999, including production yield issues and shortages, particularly for the 400 MHz model, as demand outpaced manufacturing capacity. The discontinuation of K6 family production, including the K6-2, was announced on August 15, 2001, with regular manufacturing set to end in June 2002 and final customer shipments completing by the end of 2003. This marked the transition to AMD's newer and architectures as the company shifted focus to higher-performance segments.

Design and Architecture

Microarchitecture Details

The AMD K6-2 employs a 32-bit x86 superscalar architecture derived from the RISC86 microarchitecture, featuring decoupled decode and execution stages, , , and to enhance instruction throughput. The core, known internally as Chomper, supports up to six-issue superscalar operation, with a 6-stage (fetch, decode, dispatch, execute, and retire stages), enabling efficient handling of integer workloads. The integrates a 10-stage compatible with /854 standards, incorporating dedicated , multiplier, and divide/ capabilities for improved precision and performance in computational tasks. Central to the core's execution flow are ten parallel execution units that facilitate concurrent processing: two integer arithmetic logic units (ALUs) for general computations, one load unit and one store unit for memory operations (each two-stage pipelined), two MMX ALUs, one MMX/3DNow! multiplier, one 3DNow! ALU, and one 3DNow! shifter, with integrated floating-point capabilities optimized for multimedia and vector instructions. These units allow the scheduler to dispatch up to six RISC86 operations per cycle, with data forwarding mechanisms reducing dependencies and stalls. The also inherits MMX support from the prior K6 design, mapping multimedia registers onto the floating-point stack for compatibility. Branch prediction employs a dynamic two-level adaptive scheme, including an 8192-entry branch history table for pattern-based predictions, a 16-entry branch target cache, a 16-entry return address stack, and a 512-entry target buffer to handle jumps and calls with over 95% accuracy, thereby minimizing flushes. The K6-2 supports clock multipliers ranging from 4x to 6x relative to a 66–100 MHz , allowing core speeds from 266 MHz up to 550 MHz in standard configurations. Power consumption typically ranges from 12 to 18.4 , varying with clock speed and operating at a 2.2 V core voltage to balance performance and thermal efficiency. The standard core integrates 9.3 million transistors on a 0.25-micron process.

Manufacturing Process and Packaging

The AMD K6-2 processor was fabricated using a 250 nm CMOS process technology for both its initial Chomper core and the subsequent Chomper Extended (CXT) core revisions. This five-layer-metal process featured a die size of 81 mm², enabling efficient integration of the processor's 9.3 million transistors. The design operated at a core voltage of 2.2 V with aluminum interconnects, contributing to its power efficiency and compatibility with Socket 7 systems. The transition to the from the preceding 350 nm K6 represented a significant scaling effort by , as the earlier node struggled to achieve clock speeds beyond 233 MHz due to yield limitations and constraints. This shrink allowed for higher densities, improved yields at elevated speed bins, and better overall scaling, facilitating models up to 550 MHz. For physical packaging, desktop variants utilized a 321-pin Pin Grid Array (CPGA) ceramic package, while mobile versions later adopted a thinner CPGA variant to reduce profile and enhance portability. An embedded variant, the K6-2E, employed the same 250 nm process but was qualified for extended temperature ranges up to 85 °C, making it suitable for industrial applications in the 321-pin ceramic package.

Key Features and Innovations

Instruction Set Extensions

The AMD K6-2 processor introduced 3DNow!, a SIMD instruction set extension comprising 21 new instructions optimized for accelerating 3D graphics rendering and multimedia processing. These instructions enable parallel operations on two 32-bit single-precision floating-point values packed into each 64-bit MMX register (mm0 through mm7), leveraging the existing MMX infrastructure without requiring additional hardware registers or operating system modifications. By extending the x86 architecture, 3DNow! addressed the limitations of prior floating-point units in handling graphics workloads, delivering up to four floating-point operations per clock cycle in pipelined execution. Key instructions include PFADD, which performs parallel floating-point addition on packed values; PFMAX, which computes the parallel maximum between corresponding elements while handling special cases like zero and negative ; and FEMMS, which efficiently flushes the MMX state by setting floating-point tag bits to empty, facilitating rapid transitions between and floating-point modes. Other notable additions encompass PFCMPEQ for parallel equality comparisons, PFRCP and PFRSQRT for fast reciprocal and reciprocal approximations used in and normalization, and PREFETCH for hinting data loads into the cache to reduce latency in pipelines. These extensions were hardware-decoded as short instructions, ensuring efficient integration with the K6-2's RISC86 . The K6-2 provided full backward compatibility with the standard x86 instruction set and Intel's MMX extensions carried over from the original K6 design, allowing seamless execution of legacy software. Detection of 3DNow! support occurs via the instruction (extended function 8000_0001h, bit 31 in ), enabling applications to dynamically utilize the extensions without compatibility issues. 3DNow! was specifically tailored to enhance performance in graphics APIs like Microsoft's 6.0 and Silicon Graphics' , with optimized libraries from partners such as for Glide and implementations, enabling smoother 3D web browsing and game rendering on budget systems. However, its broader adoption was constrained by the evolving software ecosystem, as developers increasingly prioritized Intel's competing SSE extensions for cross-platform compatibility, limiting 3DNow!-specific optimizations in mainstream applications.

Cache Hierarchy and Memory Support

The AMD K6-2 processor incorporates a split Level 1 (L1) cache totaling 64 KiB, divided into a 32 KiB instruction cache and a 32 KiB cache, both configured as two-way set associative with 32-byte cache lines and sectored organization (64-byte sectors sharing tags). The instruction cache includes a dedicated 20 KiB predecode buffer to optimize x86 instruction decoding, while the cache is dual-ported and supports write-back operations under the MESI (Modified, Exclusive, Shared, Invalid) coherency protocol. Cache replacement employs least recently used (LRU) for instructions and least recently allocated (LRA) for , with prefetching enabled by default to improve hit rates during burst accesses. Unlike later variants, the standard K6-2 lacks on-die Level 2 (L2) cache and relies on external L2 implementation via the Super Socket 7 interface, supporting up to 2 MiB of synchronous burst static RAM (SRAM) for secondary caching. This external L2 operates at full core speed when synchronous or at bus speed when asynchronous, controlled by system logic through signals such as KEN# for cache snooping and CACHE# for external cache presence detection, enabling scalable memory bandwidth without integrated overhead. The bus interface adopts the Super Socket 7 standard, an evolution of , featuring a 64-bit data bus (D[63:0]) and 32-bit address bus (A[31:3]) with demultiplexed operation and support for 66 MHz or 100 MHz (FSB) speeds in synchronous or asynchronous configurations. This design delivers up to 800 MB/s peak bandwidth through pipelined non-atomic cycles and burst transfers signaled by BRDY#, while maintaining with legacy systems. The processor supports up to 4 GB of physical address space, but Super Socket 7 platforms are typically configured for 768 MB maximum using SDRAM, including PC66 (66 MHz) and PC100 (100 MHz) modules for matched bus timing. It supports pipelined burst reads for 32-byte line fills, write allocation on cache misses, and paging with 4 KiB or 4 MiB granules via TLBs, alongside Memory Type Range Registers (MTRRs) for defining cacheable, uncacheable, or write-combining regions starting at 128 KiB granularity. Voltage scaling in the interface ensures compatibility with AGP 2x graphics slots, facilitating accelerated by aligning bus voltages (e.g., 2.0–2.4 V core with 3.3 V I/O) without requiring additional level shifters.

Variants and Models

Standard K6-2 Models

The standard AMD K6-2 models were based on the 250 nm Chomper core, introduced in May 1998 with clock speeds ranging from 233 MHz to 366 MHz, primarily supporting a 66 MHz (FSB) and identified by 580. These processors featured an enhanced RISC86 with integrated MMX and 3DNow! support, targeting desktop systems compatible with motherboards. In November 1998, AMD released the Chomper Extended (CXT) core variant on the same , expanding speeds to 200–550 MHz and adding 100 MHz FSB support for Super Socket 7 platforms, with 58C and approximately 9.3 million transistors. The CXT core addressed limitations in bus compatibility while maintaining the core's nine-stage integer pipeline for improved multimedia performance. Representative models included the desktop-oriented K6-2-300, operating at 300 MHz with a 2.2 V core voltage and approximately 15 W power dissipation, and the higher-speed K6-2-500AFX at 500 MHz, restricted to Super 7 motherboards with 100 MHz FSB support. The processors underwent revisions under Model 8 stepping, with updates in CPUID stepping C (revision A) fixing errata related to I/O leakage current exceeding specifications (up to ±250 µA) and output signal delay timings (minimum 700 ps versus required 1.0–1.3 ns). While primarily desktop-focused, a of mobile K6-2-P models was available at lower speeds of – MHz, operating at reduced voltages of 1.9–2.2 V to enable power-efficient applications.
Core VariantClock Speeds (MHz)FSB Support (MHz)CPUIDTransistors (million)Key Models
Chomper233–366665809.3K6-2-300AFR
CXT200–55066/10058C9.3K6-2-500AFX

K6-2+ Variant

The K6-2+ was announced and launched on April 18, , and represents an enhanced, low-power evolution of the K6-2 processor family, produced on a 0.18 μm low-power manufacturing process. It integrates 21 million transistors, enabling improved efficiency compared to the original 0.25 μm K6-2 design. The variant adds an on-die L2 cache to address the external cache dependency of the standard K6-2, which typically relied on motherboard-provided L2 for performance. Key architectural features include a 64 KB L1 cache split evenly between 32 KB instruction and 32 KB caches (both 2-way set associative with 32-byte lines) and a 128 KB unified on-die L2 cache that operates at full core speed, configured as 4-way set associative with 512 sets. Each way consists of four 64-byte sectors, with each sector containing two 32-byte cache lines. This L2 configuration enhances hit rates and reduces latency in memory-intensive tasks, particularly beneficial for power-sensitive applications. The K6-2+ derives its core from the K6-III+ but limits the integrated L2 to 128 KB rather than the full 256 KB of the desktop-oriented K6-III+, prioritizing efficiency over maximum caching capacity. Available in clock speeds from 350 MHz to 550 MHz, the K6-2+ supports multiplier-based , with some units reaching 600 MHz on compatible motherboards. It operates at core voltages between 1.6 V and 1.9 V, delivering a (TDP) under 10 W in mobile configurations, such as the 400 MHz model at approximately 9.5 W. The processor supports a 100 MHz , enabling higher bandwidth than the 66 MHz standard of earlier K6-2 models. Targeted primarily at embedded and mobile markets, the K6-2+ and related K6-2GE models feature a of family 5, model 13 ( 5D), distinguishing them from the standard K6-2's model 8 or 9. These variants emphasize features like AMD PowerNow! for dynamic voltage and , making them suitable for battery-powered devices and industrial applications.

Performance and Legacy

Benchmark Results

In contemporary benchmarks, the AMD K6-2 demonstrated competitive integer performance relative to Intel's processors at equivalent clock speeds, though it lagged in floating-point workloads. For instance, the K6-2-300 achieved scores between those of the -233 and -266 in Ziff-Davis's Winstone 98 suite, which evaluated office productivity tasks like word processing and spreadsheets, benefiting from the K6-2's larger 64 KB L1 cache compared to the 's 32 KB. At higher speeds, such as the K6-2-350, it outperformed the -350 by approximately 10-15% in similar office-oriented tests under , closing the gap in application-level performance. In SPECint95 integer benchmarks, the -300 scored 11.6. SPECfp95 results showed greater disparity for the K6-2 relative to the , though higher-clocked K6-2 models improved floating-point performance. The K6-2's 3DNow! extensions provided notable uplifts in graphics-intensive benchmarks, particularly for games optimized for SIMD instructions. In using a Voodoo2 card and drivers supporting 3DNow!, the K6-2-300 delivered frame rates outperforming the Pentium II-300 by 20-30%. Without 3DNow!, the K6-2-300 managed 25.6 fps in , underscoring the technology's impact. This advantage stemmed from dual MMX units accelerating 3D transformations, yielding up to 66% gains in 3DWinbench 98 on NVIDIA RIVA 128 hardware under DirectX 6. Power efficiency was a strength of the K6-2 family, especially in mobile configurations. The K6-2-500 dissipated a typical 12.5 and maximum 20.8 , compared to the III-500's 28 TDP, enabling better battery life in tests where the K6-2 sustained at lower output. Overclocking further extended its viability; K6-2-300 chips commonly reached 450 MHz on stable motherboards, yielding 15-20% gains in benchmarks due to the 50% clock boost tempered by 100 MHz FSB limitations, without excessive voltage increases beyond 2.2 V.

Market Impact and Comparisons

The AMD K6-2 played a pivotal role in AMD's strategy to challenge 's dominance in the late 1990s PC market by offering a cost-effective alternative that extended the viability of the aging platform. Priced approximately 20-30% lower than comparable and processors—such as the K6-2 300 MHz at around $165 versus the 300 MHz at $237—it fueled the growth of budget-oriented PCs, making accessible to a broader consumer base. The adoption of Super further prolonged the life of existing motherboards against 's architecture, allowing users to upgrade without full system overhauls and thereby capturing market share in the value segment. Sales of the K6-2 surged in 1998, with AMD shipping over 8.5 million units in less than seven months from launch, which generated critical revenue amid the company's recovery from substantial losses in the mid-1990s. This financial influx was instrumental in funding the transition to the more advanced processor line launched later that year, helping AMD stabilize and position itself for future competitiveness. Despite its successes, the K6-2 had notable limitations, particularly in its (FPU), which performed 20-50% slower than Intel's equivalents in floating-point intensive applications due to architectural differences in execution latency. Additionally, while the processor introduced the 3DNow! SIMD extensions for enhanced multimedia processing, these were underadopted by developers, who increasingly favored Intel's SSE instructions for broader compatibility and ecosystem support, limiting the feature's long-term impact. In direct comparisons, the K6-2 matched or exceeded the 300A in -based tasks like office applications and general , thanks to superior execution and decode efficiency, but it gained an edge in multimedia workloads leveraging 3DNow!. Against the , however, the K6-2 lagged in overall performance, particularly in workloads benefiting from Intel's more advanced pipeline and cache design, which proved superior even in emerging multi-threaded scenarios as software began to exploit them. The K6-2's legacy extended beyond its desktop era, paving the way for the Athlon's market entry in 1999 by providing with the necessary financial and technological bridge. Variants like the K6-2E influenced embedded applications in industrial and consumer devices until around 2002, when production of the K6 family fully ceased to shift focus to newer architectures. Today, it retains interest among retro enthusiasts and collectors for its role in affordable PC history.

References

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