Hubbry Logo
Zen 3Zen 3Main
Open search
Zen 3
Community hub
Zen 3
logo
7 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
Contribute something
Zen 3
Zen 3
Zen 3
View on Wikipedia
from Wikipedia

AMD Zen 3
General information
LaunchedNovember 5, 2020; 5 years ago (November 5, 2020)
Designed byAMD
Common manufacturers
CPUID codeFamily 19h
Cache
L1 cache64 KB (per core):
  • 32 KB instructions
  • 32 KB data
L2 cache512 KB (per core)
L3 cache
  • 32 MB (per CCD)
  • 96 MB (per CCD with 3D V-Cache)
  • 16 MB (in APUs)
Architecture and classification
Technology node
MicroarchitectureZen
Instruction setAMD64 (x86-64)
Physical specifications
Transistors
  • 6.24 billion (1× CCD) or
    10.39 billion (2× CCD)
    (4.15 billion per 7 nm 8-core "CCD" & 2.09 billion for the 12 nm "I/O die")[1]
Cores
    • Desktop: 4 to 16
    • Workstation: 16 to 64
    • Server: 16 to 64
Package
  • Package FP6
Sockets
Products, models, variants
Product code names
  • Desktop
    • Vermeer (w/o iGPU)
    • Cézanne (APU)
    • Chagall

  • Thin & Light Mobile
    • Cézanne
    • Barcelo
    • Barcelo-R

  • High-End Mobile
    Cézanne
  • Server
    • Milan
    • Milan-X

History
PredecessorZen 2
Successors
Support status
Supported

Zen 3 is the name for a CPU microarchitecture by AMD, released on November 5, 2020.[2][3] It is the successor to Zen 2 and uses TSMC's 7 nm process for the chiplets and GlobalFoundries's 14 nm process for the I/O die on the server chips and 12 nm for desktop chips.[4] Zen 3 powers Ryzen 5000 mainstream desktop processors (codenamed "Vermeer") and Epyc server processors (codenamed "Milan").[5][6] Zen 3 is supported on motherboards with 500 series chipsets; 400 series boards also saw support on select B450 / X470 motherboards with certain BIOSes.[7] Zen 3 is the last microarchitecture before AMD switched to DDR5 memory and new sockets, which are AM5 for the desktop "Ryzen" chips alongside SP5 and SP6 for the EPYC server platform and sTRX8.[3] According to AMD, Zen 3 has a 19% higher instructions per cycle (IPC) on average than Zen 2.

On April 1, 2022, AMD released the new Ryzen 6000 series for laptops/mobile, using an improved Zen 3+ architecture featuring notable architectural improvements to power efficiency and power management.[8] And slightly later, on April 20, 2022, AMD would also release the Ryzen 7 5800X3D desktop processor, which increased gaming performance by around +15% on average by using for the very first time in a PC product, a 3D vertically stacked L3 cache. Specifically in the form of a 64MB L3 cache "3D V Cache" die made on the same TSMC N7 process as the 8-core Zen 3 CCD which it gets direct copper to copper hybrid bonded to.[9]

Features

[edit]

As the first largely "ground up redesign" of the Zen CPU core since the architecture family's original release in early 2017 with Zen 1/Ryzen 1000, Zen 3 was a significant architectural improvement over its predecessors; having a very significant IPC increase of +19% over the prior Zen 2 architecture in addition to being capable of reaching higher clock speeds.[10]

Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing the I/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8 CPU cores and 32 MB of shared L3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores paired with 16 MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through the Infinity Fabric.[10]

Zen 3 (along with AMD's RDNA2 GPUs) also implemented Resizable BAR, an optional feature introduced in PCIe 2.0, that was branded as Smart Access Memory (SAM). This technology allows CPU to directly access all of compatible video card's VRAM.[11] Intel and Nvidia have since implemented this feature as well.[12]

  • A de-lidded Ryzen 5 5600X. Only one 6-core CCD is present. The contacts for a second CCD are visible.
    A de-lidded Ryzen 5 5600X. Only one 6-core CCD is present. The contacts for a second CCD are visible.
  • Close-up of the CCD, taken under infrared lighting. This die was damaged by the de-lidding process.
    Close-up of the CCD, taken under infrared lighting. This die was damaged by the de-lidding process.
  • Close-up of the I/O die
    Close-up of the I/O die

In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs. Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.[13]

On April 20, 2022, AMD released the R7 5800X3D. It features, for the first time in a desktop PC product, 3D-stacked vertical L3 cache. Its extra 64MB comes via a TSMC N7 (7nm) "3D V Cache" die direct copper to copper hybrid bonded right on top of the 8-core Zen 3 CCD's usual 32MB, increasing the CPU's total L3 cache capacity to 96MB and bringing significant performance improvements for gaming in particular; now rivalling contemporary high-end consumer processors while being much more power efficient and running on older, cheaper motherboards using affordable DDR4 memory.[9] And despite now spanning multiple dies and being three times larger (96MB vs 32MB), the L3 cache's performance remains nearly identical; with X3D only adding around ≈+2ns via an additional three to four cycles of latency.[14] It would later be followed by the Ryzen 5 5600X3D and Ryzen 7 5700X3D for lower-end market segments, and succeeded by the Ryzen 7000X3D family of 3D V Cache equipped Zen 4 processors on the newer socket AM5 platform.

Improvements

[edit]
CCD layouts comparison for Zen 2 and Zen 3

Zen 3 has made the following improvements over Zen 2:[13][15]

  • An increase of 19% in instructions per clock
  • The base core chiplet has a single eight-core complex (versus two four-core complexes in Zen 2)
  • A unified 32MB L3 cache pool equally available to all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex.
    • On mobile: A unified 16MB L3
  • A unified 8-core CCX (from 2x 4-core CCX per CCD)
  • Increased branch prediction bandwidth. L1 branch target buffer size increased to 1024 entries (vs 512 in Zen 2)
  • New instructions
  • Improved integer units
    • 96 entry integer scheduler (up from 92)
    • 192 entry physical register file (up from 180)
    • 10 issue per cycle (up from 7)
    • 256 entry reorder-buffer (up from 224)
    • fewer cycles for DIV/IDIV ops (10...20 from 16...46)
  • Improved floating point units
    • 6 μOP dispatch width (up from 4)
    • FMA latency reduced by 1 cycle (down from 5 to 4)
  • Additional 64MB 3D vertically stacked dense library L3 cache (in -X3D models)

Feature tables

[edit]

CPUs

[edit]

APUs

[edit]

APU features table

Products

[edit]
AMD Ryzen 7 5800X

On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.[2]

Desktop CPUs

[edit]

The Ryzen 5000 series desktop CPUs are codenamed Vermeer. The models in the second table are based on Cezanne APUs with the integrated GPU disabled. Meanwhile the Ryzen Threadripper Pro 5000 series were codenamed Chagall.

Common features of Ryzen 5000 desktop CPUs:

  • Socket: AM4.
  • All the CPUs support DDR4-3200 in dual-channel mode.
  • All the CPUs support 24 PCIe 4.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • L1 cache: 64 KB per core (32 KB data + 32 KB instruction).
  • L2 cache: 512 KB per core.
  • Fabrication process: TSMC 7FF.
Branding and model Cores
(threads) 		Thermal
solution 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i] 		Release
date 		MSRP
Base Boost
Ryzen 9 5950X 16 (32) — 3.4 4.9 64 MB 105 W 2 × CCD
1 × I/OD 		2 × 8 Nov 5, 2020 US $799
5900XT 3.3 4.8 Jul 31, 2024 US $349
5900X 12 (24) 3.7 2 × 6 Nov 5, 2020 US $549
5900 3.0 4.7 65 W Jan 12, 2021 OEM
PRO 5945 Sep 2022[16]
Ryzen 7 5800X3D 8 (16) 3.4 4.5 96 MB 105 W 1 × CCD
1 × I/OD 		1 × 8 Apr 20, 2022 US $449
5800XT Wraith Prism
(only included before Aug 1, 2025)[17] 		3.8 4.8 32 MB Jul 31, 2024 US $249
5800X — 4.7 Nov 5, 2020 US $449
5800 3.4 4.6 65 W Jan 12, 2021 OEM
5700X3D 3.0 4.1 96 MB 105 W Jan 31, 2024[18] US $249
5700X 3.4 4.6 32 MB 65 W Apr 4, 2022 US $299
PRO 5845 Sep 2022 OEM
Ryzen 5 5600X3D 6 (12) 3.3 4.4 96 MB 105 W 1 × 6 Jul 7, 2023
US Only[19] 		US $229[20]
5600XT Wraith Stealth 3.7 4.7 32 MB 65 W Oct 31, 2024 US $194[21]
5600X 3.7 4.6 Nov 5, 2020 US $299
5600T 3.5 4.5 Oct 31, 2024 US $186[21]
5600 3.5 4.4 Apr 4, 2022 US $199
5600F [to be determined] 3.0 4.0 Sep 16, 2025 APJ Only[22]
PRO 5645 — 3.7 4.6 Sep 2022 OEM
5500X3D 3.0 4.0 96 MB 105 W Jun 5, 2025 LATAM Only[23]
  1. ^ Core Complexes (CCX) × cores per CCX

Common features of Ryzen 5000 (Cezanne) desktop CPUs:

  • Socket: AM4.
  • CPUs support DDR4-3200 in dual-channel mode.
  • L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • Fabrication process: TSMC 7FF.
Branding and model Cores
(threads) 		Thermal
solution 		Clock rate (GHz) L3 cache
(total) 		TDP Core
config[i] 		Release
date 		MSRP
(USD)
Base Boost
Ryzen 7 5700[24] 8 (16) Wraith Stealth 3.7 4.6 16 MB 65 W 1 × 8 Apr 4, 2022 (OEM),
Dec 21, 2023 (retail) 		$179
Ryzen 5 5500 6 (12) 3.6 4.2 1 × 6 Apr 4, 2022 $159
Ryzen 3 5100[25][26][27] 4 (8) – 3.8 8 MB 1 × 4 2023 OEM
  1. ^ Core Complexes (CCX) × cores per CCX

5100, 5500, and 5700 have no ECC support like non-Pro Ryzen 5000 Desktop APUs.

Common features of Ryzen 5000 workstation CPUs:

  • Socket: sWRX8.
  • All the CPUs support DDR4-3200 in octa-channel mode.
  • L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 128 PCIe 4.0 lanes. 8 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • Fabrication process: TSMC 7FF.
Branding and Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i] 		Release
date 		MSRP
Base Boost
Ryzen
Threadripper
PRO 		5995WX 64 (128) 2.7 4.5 256 MB 280 W 8 × CCD
1 × I/OD 		8 × 8 Mar 8, 2022
(OEM) /
?
(retail) 		OEM /
US $6500
5975WX 32 (64) 3.6 128 MB 4 × CCD
1 × I/OD 		4 × 8 Mar 8, 2022
(OEM) /
?
(retail) 		OEM /
US $3300
5965WX 24 (48) 3.8 4 × 6 Mar 8, 2022
(OEM) /
?
(retail) 		OEM /
US $2400
5955WX 16 (32) 4.0 64 MB 2 × CCD
1 × I/OD 		2 × 8 Mar 8, 2022 OEM
5945WX 12 (24) 4.1 2 × 6
  1. ^ Core Complexes (CCX) × cores per CCX

Desktop APUs

[edit]

Cezanne

[edit]

Common features of Ryzen 5000 desktop APUs:

  • Socket: AM4.
  • All the CPUs support DDR4-3200 in dual-channel mode.
  • L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • Includes integrated GCN 5th generation GPU.
  • Fabrication process: TSMC 7FF.
Branding and model CPU GPU[a] Thermal
solution 		TDP Release
date 		MSRP
Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		Core
config[i] 		Clock
(MHz) 		Config[ii] Processing
power[iii]
(GFLOPS)
Base Boost
Ryzen 7 5705G 8 (16) 3.8 4.6 16 MB 1 × 8 2000 512:32:8
8 CU 		2048 — 65 W
5700G[b] Wraith Stealth Apr 13, 2021 (OEM),
Aug 5, 2021 (retail) 		US $359
5705GE 3.2 — 35 W
5700GE[b] Wraith Stealth Apr 13, 2021 OEM
Ryzen 5 5600GT 6 (12) 3.6 1 × 6 1900 448:28:8
7 CU 		1702.4 65 W Jan 31, 2024[28] US $140
5605G 3.9 4.4 —
5600G[b] Wraith Stealth Apr 13, 2021 (OEM),
Aug 5, 2021 (retail) 		US $259
5605GE 3.4 — 35 W
5600GE[b] Wraith Stealth Apr 13, 2021 OEM
5500GT 3.6 65 W Jan 31, 2024[28] US $125
Ryzen 3 5305G 4 (8) 4.0 4.2 8 MB 1 × 4 1700 384:24:8
6 CU 		1305.6 —
5300G[b] OEM Apr 13, 2021 OEM
5305GE 3.6 — 35 W
5300GE[b] OEM Apr 13, 2021 OEM
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Unified shaders : texture mapping units : render output units and compute units (CU)
  3. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  1. ^ All of the iGPUs are branded as AMD Radeon Graphics.
  2. ^ a b c d e f Model also available as PRO version as 5350GE,[29] 5350G,[30] 5650GE,[31] 5650G,[32] 5750GE,[33] 5750G,[34] released June 1, 2021. Refresh models 5355GE, 5355G, 5655GE, 5655G, 5755GE, 5755G released September 5, 2024.[35]

Mobile APUs

[edit]

Cezanne

[edit]
Branding and Model CPU GPU TDP Release
date
Cores
(Threads) 		Clock rate (GHz) L3 cache
(total) 		Core
config[i] 		Model Clock
(GHz) 		Config[ii] Processing
power
(GFLOPS)[iii]
Base Boost
Ryzen 9 5980HX[36] 8 (16) 3.3 4.8 16 MB 1 × 8 Radeon
Graphics
[a] 		2.1 512:32:8
8 CUs 		2150.4 35–54 W Jan 12, 2021
5980HS[37] 3.0 35 W
5900HX[38] 3.3 4.6 35–54 W
5900HS[39] 3.0 35 W
Ryzen 7 5800H[40][41] 3.2 4.4 2.0 2048 35–54 W
5800HS[42] 2.8 35 W
5800U[note 1][43] 1.9 10–25 W
Ryzen 5 5600H[44][45] 6 (12) 3.3 4.2 1 × 6 1.8 448:28:8
7 CUs 		1612.8 35–54 W
5600HS[46] 3.0 35 W
5600U[note 1][47] 2.3 10–25 W
5560U[48] 4.0 8 MB 1.6 384:24:8
6 CUs 		1228.8
Ryzen 3 5400U[note 1][49][50] 4 (8) 2.7 4.1 1 × 4
  1. ^ All of the iGPUs are branded as AMD Radeon Graphics.
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Unified shaders : texture mapping units : render output units and compute units (CU)
  3. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  1. ^ a b c d Model also available as PRO version as 5450U,[51] 5650U,[52] 5850U,[53] released on March 16, 2021.

Barceló

[edit]
Branding and model CPU GPU TDP Release
date
Cores
(Threads) 		Clock rate (GHz) L3 cache
(total) 		Core
config[i] 		Model Clock
(GHz) 		Config[ii] Processing
power
(GFLOPS)[iii]
Base Boost
Ryzen 7 5825U[note 1][note 2][54] 8 (16) 2.0 4.5 16 MB 1 × 8 Radeon
Graphics[a] 		2.0 512:32:8
8 CUs 		2048 15 W Jan 4, 2022
Ryzen 5 5625U[note 1][note 2][55] 6 (12) 2.3 4.3 1 × 6 1.8 448:28:8
7 CUs 		1612.8
Ryzen 3 5425U[56] 4 (8) 2.7 4.1 8 MB 1 × 4 1.6 384:24:6
6 CUs 		? Jan 30, 2022
Ryzen 3 5125C[57] 2 (4) 3.0 — 1 × 2 ? 192:12:8
3 CU 		? May 5, 2022
  1. ^ All of the iGPUs are branded as AMD Radeon Graphics.
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Unified shaders : texture mapping units : render output units and compute units (CU)
  3. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  1. ^ a b c Model also available as Pro version as 5475U,[58] 5675U,[59] 5875U,[60] released on April 19, 2022.
  2. ^ a b c Model also available as Chromebook optimized version as 5425C,[61] 5625C,[62] 5825C,[63] released on May 5, 2022.

Barceló-R

[edit]

Common features of Ryzen 7030 notebook APUs:

  • Socket: FP6.
  • All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode.
  • L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 16 PCIe 3.0 lanes.
  • Native USB 4 (40Gbps) Ports: 0
  • Native USB 3.2 Gen 2 (10Gbps) Ports: 2
  • Includes integrated GCN 5th generation GPU.
  • Fabrication process: TSMC N7 FinFET.
Branding and Model CPU GPU TDP Release
date
Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		Core
config[a] 		Model Clock
(GHz) 		Processing
power[b]
(GFLOPS)
Base Boost
Ryzen 7 (PRO) 7730U 8 (16) 2.0 4.5 16 MB 1 × 8 Vega
8 CU 		2.0 2048 15 W January 4, 2023
[64]
Ryzen 5 (PRO) 7530U 6 (12) 1 × 6 Vega
7 CU 		1792
7430U 2.3 4.3 1.8 1612.8 Q4 2023
Ryzen 3 (PRO) 7330U 4 (8) 8 MB 1 × 4 Vega
6 CU 		1382.4 January 4, 2023
[65]
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Embedded CPUs

[edit]
Model Release
date 		Fab CPU Socket PCIe
support 		Memory
support 		TDP
Cores
(threads) 		Clock rate (GHz) Cache
Base Boost L1 L2 L3
V3C14[66][67] September 27, 2022[68] TSMC
7FF 		4 (8) 2.3 3.8 32 KB inst.
32 KB data
per core 		512 KB
per core 		8 MB FP7r2 20
(8+4+4+4)
PCIe 4.0 		DDR5-4800
dual-channel 		15 W
V3C44[66][67] 3.5 3.8 45 W
V3C16[66][67] 6 (12) 2.0 3.8 16 MB 15 W
V3C18I[66][67] 8 (16) 1.9 3.8 15 W
V3C48[66][67] 3.3 3.8 45 W

Server CPUs

[edit]

The Epyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using the SP3 socket.[6] Epyc Milan was released on March 15, 2021.[69]

Common features:

  • SP3 socket
  • Zen 3 microarchitecture
  • TSMC 7 nm process for the compute and cache dies, GloFo 14 nm process for the I/O die
  • MCM with one I/O Die (IOD) and multiple Core Complex Dies (CCD) for compute, one core complex (CCX) per CCD chiplet
  • Eight-channel DDR4-3200
  • 128 PCIe 4.0 lanes per socket, 64 of which are used for Infinity Fabric inter-processor links in 2P platforms
  • 7003X series models include 64 MiB L3 cache dies stacked on top of the compute dies (3D V-Cache)
  • 7003P series models are limited to uniprocessor operation (1P, single-socket)
Model Cores
(threads) 		Chiplets Core
config
[i] 		Clock rate Cache size Socket Scaling TDP
default (range) 		Release
price
Base
(GHz) 		Boost
(GHz) 		L2
per core 		L3
per CCX 		Total
7203(P)   8 (16) 2 + IOD  2 × 4  2.8  3.4  512 KB 32 MB 68 MB   SP3 2P (1P) 120 W (120-150)   $348 ($338)
72F3 8 + IOD  8 × 1  3.7  4.1 260 MB 2P 180 W (165-200) $2468
7303(P) 16 (32) 2 + IOD  2 × 8  2.4  3.4 32 MB 72 MB 2P (1P) 130 W (120-150)   $604 ($594)
7313(P) 4 + IOD  4 × 4  3.0  3.7 136 MB 2P (1P) 155 W (155-180) $1083 ($913)
7343  3.2  3.9 2P 190 W (165-200) $1565
73F3 8 + IOD  8 × 2  3.5  4.0 264 MB 240 W (225-240) $3521
7373X 8* + IOD  3.05  3.8 96 MB 776 MB 240 W (225-280) $4185
7413 24 (48) 4 + IOD  4 × 6  2.65  3.6 32 MB 140 MB 2P 180 W (165-200) $1825
7443(P)  2.85  4.0 2P (1P) 200 W (165-200) $2010 ($1337)
74F3 8 + IOD  8 × 3  3.2  4.0 268 MB 2P 240 W (225-240) $2900
7473X 8* + IOD  2.8  3.7 96 MB 780 MB 240 W (225-280) $3900
7453 28 (56) 4 + IOD  4 × 7  2.75  3.45 16 MB 78 MB 2P 225 W (225-240) $1570
7513 32 (64) 4 + IOD  4 × 8  2.6  3.65 32 MB 144 MB 2P 200 W (165-200) $2840
7543(P) 8 + IOD  8 × 4  2.8  3.7 272 MB 2P (1P) 225 W (225-240) $3761 ($2730)
75F3  2.95  4.0 2P 280 W (225-280) $4860
7573X 8* + IOD  2.8  3.6 96 MB 784 MB $5590
7R13[70] 48 (96) 6 + IOD  6 × 8  2.65  3.7 32 MB 216 MB TBD TBD OEM/AWS
7643(P) 8 + IOD  8 × 6  2.3  3.6 280 MB 2P (1P) 225 W (225-240) $4995 ($2722)
7663 56 (112) 8 + IOD  8 × 7  2.0  3.5 32 MB 284 MB 2P 240 W (225-240) $6366
7663P 1P 240 W (225-280) $3139
7713(P) 64 (128) 8 + IOD  8 × 8  2.0  3.675 32 MB 288 MB 2P (1P) 225 W (225-240) $7060 ($5010)
7763  2.45  3.4 2P 280 W (225-280) $7890
7773X 8* + IOD  2.2  3.5 96 MB 800 MB $8800
  1. ^ Core Complexes (CCX) × cores per CCX

Zen 3+

[edit]
AMD Zen 3+
General information
LaunchedApril 1, 2022; 3 years ago (April 1, 2022)
Designed byAMD
Common manufacturer
CPUID codeFamily 19h
Cache
L1 cache64 KB (per core)
L2 cache512 KB (per core)
L3 cacheUp to 16 MB
Architecture and classification
Technology nodeTSMC N6
Instruction setAMD64 (x86-64)
Physical specifications
Cores
  • 4 to 8
Package
    • Package FP7
    • Package FP7r2
Products, models, variants
Product code names
  • Thin & Light Mobile
    • Rembrandt
    • Rembrandt-R

  • High-End Mobile
    • Rembrandt
    • Rembrandt-R

History
PredecessorZen 3
SuccessorZen 4
Support status
Supported

Zen 3+ is the codename for a refresh of the Zen 3 microarchitecture, which focuses on power efficiency improvements. It was released in April 2022 with the Ryzen 6000 series of mobile processors.

Features and improvements

[edit]

Zen 3+ has 50 new or enhanced power management features over Zen 3, and also provides an adaptive power management framework, as well as new deep sleep states. Altogether, this brings improvements to efficiency both during idle, and when under load, with up to 30% performance-per-watt increase over Zen 3, as well as longer battery life.[71][72]

IPC is identical to that of Zen 3; the performance improvements of Ryzen 6000 over Ryzen 5000 mobile processors stem from it having a higher efficiency (hence more performance in power-constrained form factors like laptops), as well as the increased clock speeds from being built on the smaller TSMC N6 node.[73]

The Rembrandt implementation of Zen 3+ also has support for DDR5 and LPDDR5 memory.

Products

[edit]

Rembrandt

[edit]

On April 1, 2022, AMD released the Ryzen 6000 series of mobile APUs, codenamed Rembrandt. It introduces PCIe 4.0 and DDR5/LPDDR5 for the first time in an APU for the laptop and also introduced RDNA2 integrated graphics to the PC. It is built on TSMC's 6 nm node.[8]

Common features of Ryzen 6000 notebook APUs:

  • Socket: FP7, FP7r2.
  • All the CPUs support DDR5-4800 or LPDDR5-6400 in dual-channel mode.
  • L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 16 PCIe 4.0 lanes.
  • Native USB 4 (40Gbps) Ports: 2
  • Native USB 3.2 Gen 2 (10Gbps) Ports: 2
  • Includes integrated RDNA 2 GPU.
  • Fabrication process: TSMC N6 FinFET.
Branding and model CPU GPU TDP Release
date
Cores
(threads) 		Clock (GHz) L3 cache
(total) 		Core
config[i] 		Model Clock
(GHz) 		Config[ii] Processing
power
(GFLOPS)[iii]
Base Boost
Ryzen 9 6980HX 8 (16) 3.3 5.0 16 MB 1 × 8 680M 2.4 768:48:8
12 CUs 		3686.4 45 W Jan 4, 2022
[74]
6980HS 35 W
6900HX[a] 4.9 45 W
6900HS[a] 35 W
Ryzen 7 6800H[a] 3.2 4.7 2.2 3379.2 45 W
6800HS[a] 35 W
6800U[a] 2.7 15–28 W
Ryzen 5 6600H[a] 6 (12) 3.3 4.5 1 × 6 660M 1.9 384:24:8
6 CUs 		1459.2 45 W
6600HS[a] 35 W
6600U[a] 2.9 15–28 W
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Unified shaders : texture mapping units : render output units and compute units (CU)
  3. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  1. ^ a b c d e f g h Model also available as PRO version (6650U[75], 6650H[76], 6650HS[77], 6850U[78], 6850H[79], 6850HS[80], 6950H[81], 6950HS[82]), released on April 19, 2022.

Rembrandt-R

[edit]

Rembrandt-R is the codename for a refresh of Rembrandt codenamed processors, released as the Ryzen 7035 series of mobile APUs in January 2023.

Common features of Ryzen 7035 notebook APUs:

  • Socket: FP7, FP7r2.
  • All the CPUs support DDR5-4800 or LPDDR5-6400 in dual-channel mode.
  • L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 16 PCIe 4.0 lanes.
  • Native USB 4 (40Gbps) Ports: 0
  • Native USB 3.2 Gen 2 (10Gbps) Ports: 2
  • Includes integrated RDNA 2 GPU.
  • Fabrication process: TSMC N6 FinFET.
Branding and model CPU GPU TDP Release
date[83]
Cores
(threads) 		Clock (GHz) L3 cache
(total) 		Core
config[a] 		Model Clock
(GHz) 		Processing
power[b]
(GFLOPS)
Base Boost
Ryzen 7 7735HS 8 (16) 3.2 4.75 16 MB 1 × 8 680M
12 CU 		2.2 3379.2 35–54 W April 30, 2023
7735H
7736U 2.7 4.7 15–28 W January 4, 2023
7735U 4.75 15–30 W
7435HS 3.1 4.5 — 35–54 W 2024[84]
7435H
Ryzen 5 7535HS 6 (12) 3.3 4.55 1 × 6 660M
6 CU 		1.9 1459.2 April 30, 2023
7535H
7535U 2.9 15–30 W January 4, 2023
7235HS 4 (8) 3.2 4.2 8 MB 1 × 4 — 35–53 W 2024[85]
7235H
Ryzen 3 7335U 3.0 4.3 660M
4 CU 		1.8 921.6 15–30 W January 4, 2023
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Zen 3

View on Grokipedia
from Grokipedia
Zen 3 is a (CPU) developed by Advanced Micro Devices (AMD) as the successor to , introduced with the 5000 series desktop processors on November 5, 2020. Fabricated on TSMC's node, it emphasizes performance efficiency through a chiplet-based design that integrates multiple core complex dies (CCDs) via Infinity Fabric. The architecture delivers an average 19% uplift in instructions per clock (IPC) over , driven by enhancements in branch prediction, a wider execution engine, and optimized pipeline throughput. A defining feature of Zen 3 is its redesigned eight-core CCD, which unifies 32 MB of L3 cache accessible to all cores within the , doubling the directly available L3 cache per core compared to and significantly reducing inter-core communication latency for latency-sensitive workloads like gaming. This configuration enables up to 16 cores and 32 threads in high-end desktop models such as the 9 5950X, with boost clocks reaching 4.9 GHz and support for PCIe 4.0 and DDR4-3200 memory. In server applications, Zen 3 powers the 7003 "" series, scaling to 64 cores per socket with up to 256 MB of L3 cache, PCIe 4.0 lanes, and improved energy efficiency for tasks. Mobile variants, including the 5000 "Cezanne" APUs, integrate Zen 3 cores with graphics for laptops, offering up to eight cores and enhanced integrated performance. Zen 3 marked a pivotal advancement for , establishing leadership in gaming performance upon launch while maintaining competitive productivity and multi-threaded capabilities against contemporaries like Intel's 10th and 11th-generation Core processors. Its innovations, including (SMT) and advanced prefetching, contributed to broad adoption across consumer, professional, and enterprise segments, with the architecture remaining relevant through refreshes like Zen 3+ in mobile products until the transition to Zen 4.

Development

Announcement and design goals

AMD first provided high-level details on Zen 3 during its "" processor launch event on August 7, 2019, confirming the would utilize TSMC's enhanced node (7 nm+) and continue the -based for scalability in high-core-count configurations. This revelation positioned Zen 3 as the successor to , with early roadmap updates emphasizing its role in extending 's competitive edge in both desktop and server markets through modular integration, allowing for efficient scaling beyond 16 cores without the manufacturing challenges of monolithic dies. The phase for Zen 3 was completed by mid-2019, with occurring later that year, targeting production readiness in 2020 while maintaining compatibility with existing AM4 sockets for desktop variants. The development of Zen 3 was motivated by the need to address intensifying competition, particularly as faced repeated delays in transitioning to its , which hampered its ability to deliver competitive core counts and performance density. aimed to solidify its market leadership by focusing on single-threaded performance improvements critical for gaming and workloads, leveraging the chiplet's flexibility to support up to 64 cores in server applications like the upcoming "" without compromising efficiency. On October 8, 2020, formally unveiled at a dedicated event, detailing key design goals including a 19% increase in instructions per clock (IPC) over , achieved primarily through a unified core complex redesign that consolidated the L3 cache into a single 32 MB domain per eight-core chiplet, reducing latency and enhancing branch prediction for better single-threaded uplift. This architecture targeted Zen 2-level clock speeds of up to 4.9 GHz while improving power efficiency, enabling higher sustained performance in latency-sensitive tasks without increasing significantly.

Manufacturing and release

The compute chiplets of Zen 3 processors were fabricated on TSMC's node, enabling high transistor density with each featuring 4.15 billion transistors across an area of approximately 80.7 mm². The I/O die, handling interconnects and peripheral interfaces, was produced using ' 12 nm process for desktop and mobile variants, or 14 nm for server implementations. This combination optimized performance in core logic while maintaining cost-effective I/O fabrication on a more established node. Engineering samples reached OEM partners in Q2 2020, allowing early validation and . The official launch followed on November 5, 2020, introducing the 5000 series desktop lineup, headlined by the 16-core 9 5950X at a launch MSRP of $799. Zen 3's modular architecture facilitated yield improvements through smaller, specialized dies that reduced defect rates during manufacturing. Cost efficiencies arose from reusing compatible compute chiplets and I/O dies across desktop, mobile, and server segments, streamlining production and minimizing variant-specific redesigns. Launch availability faced challenges from COVID-19-induced supply chain constraints, resulting in widespread shortages and elevated resale prices for 5000 processors in late 2020.

Architecture

Core microarchitecture

The Zen 3 core implements a 4-wide superscalar, , building on the foundational design of prior Zen generations while introducing targeted refinements for improved throughput and efficiency. The consists of 19 stages, enabling deep speculation and high-frequency operation, while the floating-point is shortened to 4 stages to minimize latency in vector workloads. This configuration supports simultaneous multi-threading (SMT) with two threads per core, allowing the core to dispatch up to 6 micro-operations (μops) per cycle—typically 4 to the domain and 2 to the floating-point domain—facilitating balanced execution across diverse workloads. https://www.agner.org/optimize/microarchitecture.pdf https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 Central to the execution are dual schedulers, each capable of handling up to 44 entries, that enable 4-wide dispatch to four arithmetic logic units (ALUs) and three address generation units (AGUs). This setup allows for robust handling of operations, with branch execution supported by two dedicated units to maintain pipeline flow. The core is identified via function 0000_0001h, returning family 19h (model 01h or higher for Zen 3 variants), which distinguishes it from prior (17h) implementations. In desktop configurations, Zen 3 supports up to 8 cores per core complex (CCX), unifying access to shared resources within the complex for streamlined single-threaded performance. https://smartos.org/man/3cpc/amd_f19h_zen3_events https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 https://wccftech.com/amd-zen-3-ryzen-4000-vermeer-cpus-detailed-up-to-16-cores-32-threads/ The represents a key enhancement, featuring three 256-bit fused multiply-add (FMA) units alongside two dedicated add pipes, delivering up to 24 floating-point operations per cycle for AVX2 instructions. This triple-FMA configuration reduces FMA latency to 4 cycles from 5 in , enabling higher throughput for vectorized compute tasks without AVX-512 support, which was introduced in subsequent architectures. Store-to-load forwarding latency is optimized at 5 cycles, supporting efficient data dependencies in numerical applications. https://www.realworldtech.com/forum/?threadid=195965&curpostid=195985 https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 https://www.agner.org/optimize/microarchitecture.pdf Enhancements in the load/store unit boost memory operation throughput to 3 loads or 2 stores per cycle (up to 256 bits each), a step up from Zen 2's 2 loads and 1 store. Three AGUs facilitate parallel address calculations, with architectural shifts—such as relocating floating-point stores and FP-to-integer conversions to the load/store domain—reducing overall latency by 1-2 cycles for dependent operations. This design minimizes stalls in bandwidth-sensitive scenarios, contributing to the core's overall 19% instructions-per-clock (IPC) uplift over Zen 2. https://www.nextplatform.com/2021/03/26/deep-dive-into-amds-milan-epyc-7003-architecture/ https://forums.anandtech.com/threads/design-changes-in-zen-3-cpu-core-chiplet-only.2585982/

Chiplet design and interconnect

The Zen 3 utilizes a (MCM) design consisting of one or more compute s, known as core complex dies (CCDs), connected to a central (I/O) die through AMD's Fabric interconnect. Each CCD, fabricated on TSMC's node, integrates a single 8-core core complex (CCX) with 32 MB of unified L3 cache shared among all eight cores, departing from Zen 2's configuration of two 4-core CCXs per CCD with separate 16 MB L3 slices. This shift eliminates the need for inter-CCX communication via Fabric for local cache accesses, thereby reducing average inter-core L3 latency within the CCD compared to Zen 2's dual-CCX setup. The Infinity Fabric links between each CCD and the I/O die employ an on-package (IFOP) interface with 16 bidirectional lanes, operating at speeds up to the Infinity Fabric clock (FCLK) of 1.8 GT/s in typical configurations, delivering up to 32 bytes read and 16 bytes write per cycle at 1.8 GHz FCLK, for approximately 57.6 GB/s read and 28.8 GB/s write bandwidth (aggregate ~86.4 GB/s) per link. The I/O die, built on a 12 nm process for client processors and 14 nm for server variants, manages essential system interfaces including the integrated supporting DDR4-3200 and up to 24 lanes of PCIe 4.0 for desktop applications, while server implementations expand to 128 PCIe 4.0 lanes. This design integrates the I/O die with a mesh topology of Infinity Fabric routers to efficiently route traffic among multiple CCDs and external peripherals, enhancing overall system coherence and scalability. In server configurations, such as the "" processors on the SP3 socket, the architecture supports up to eight CCDs per package, enabling a maximum of 64 cores while maintaining low-latency access to shared resources via the central I/O die and Infinity Fabric mesh. Each Zen 3 CCD contains approximately 4.15 billion transistors, contributing to the dense integration of eight high-performance cores and their associated within a compact 83 mm² die area. This approach allows to scale core counts flexibly while optimizing manufacturing yields by isolating compute logic on advanced nodes separate from the I/O functions on more mature processes. The memory subsystem integrates a dual-channel DDR4 controller on the I/O die, supporting up to DDR4-3200 with a theoretical peak bandwidth of 51.2 GB/s, which enhances overall system throughput for memory-intensive workloads. This configuration leverages the Infinity Fabric interconnect for efficient data movement between the I/O die and compute chiplets, prioritizing bandwidth improvements over latency in multi-core scenarios. Zen 3 introduces optional 3D V-Cache in select variants, stacking an additional 64 MB of L3 cache vertically on the core complex die using through-silicon vias (TSVs) for a total of 96 MB per eight-core CCX, targeted at gaming applications to further reduce cache miss rates and latency through increased capacity and direct access paths. While low-latency RAM can improve performance in standard Zen 3 models, it does not fully compensate for the absence of 3D V-Cache, as the stacked cache provides a much larger reduction in effective memory latency and significantly higher FPS in CPU-bound gaming scenarios like 1080p/1440p simulation games or esports, often exceeding the benefits from RAM optimizations.

Key features and improvements

Performance enhancements

Zen 3 achieves an average 19% increase in instructions per clock (IPC) over , with gains reaching up to 25% in certain integer-heavy workloads such as decompression and tasks. This uplift stems primarily from enhancements in the core's engine, including a larger reorder buffer expanded to 256 entries from 224 in , which allows for greater speculation depth and reduced stalls during instruction retirement. Additionally, improved branch misprediction recovery and speculation mechanisms contribute to higher throughput in pipelines, enabling more efficient handling of complex paths. A key contributor to the IPC gains is the overhauled branch prediction unit, featuring a doubled L1 branch target buffer (BTB) size of 1024 entries compared to 512 in , alongside an enlarged L2 BTB with 6656 entries. Zen 3 retains the perceptron-based predictor introduced in earlier generations but benefits from higher prediction bandwidth and "zero-bubble" prediction for direct branches, resulting in improved accuracy over in branch-intensive benchmarks. These changes minimize bubbles from mispredictions, particularly in workloads with frequent conditional branches, boosting overall execution efficiency. Execution enhancements further amplify performance, with dispatch and issue widths increased to 6-wide from 4-wide in , allowing up to 10 integer operations per cycle via additional ports. Floating-point handling is improved through dedicated ports for FP stores and conversions, alongside a reduced FMA latency of 4 cycles (down from 5), supporting up to 6 FP μOPs dispatched per cycle. SMT handling is optimized for dual threads per core, with better resource allocation reducing contention in mixed workloads. These tweaks, combined with the unified cache design, enable 15-20% better , facilitating sustained higher boost clocks up to 4.9 GHz on single cores.

Cache and memory subsystem

The in Zen 3 processors follows a three-level design per core, with private L1 and L2 caches and a shared L3 cache at the core complex level. Each core features a 32 KiB instruction cache (L1I) that is 8-way set associative and a 32 KiB data cache (L1D) that is also 8-way set associative, both supporting 64-byte cache lines for efficient instruction fetch and data access. These L1 caches employ a write-back policy and provide low-latency access critical for , with typical hit latencies around 4 cycles for both instruction and data accesses. The private L2 cache per core is 512 KiB and 8-way set associative, also with 64-byte lines, serving as a unified victim cache for L1 evictions and extending the effective capacity for frequently accessed . L2 hit latency is approximately 12 cycles, balancing size and speed to support the core's execution while minimizing pressure on higher levels. At the core complex (CCX) level, Zen 3 unifies the L3 cache into a single 32 MB shared structure for all eight cores in the complex, a key change from Zen 2's split design that reduces inter-core latency by providing uniform access. This L3 cache is 16-way set associative with 64-byte lines and operates as a victim cache, capturing evicted from L2 to maintain data locality; access latency within the CCX is around 34-40 cycles, enabling faster shared retrieval compared to prior generations. The memory subsystem integrates a dual-channel DDR4 controller on the I/O die, supporting up to DDR4-3200 with a theoretical peak bandwidth of 51.2 GB/s, which enhances overall system throughput for memory-intensive workloads. This configuration leverages the Infinity Fabric interconnect for efficient data movement between the I/O die and compute chiplets, prioritizing bandwidth improvements over latency in multi-core scenarios. Zen 3 introduces optional 3D V-Cache in select variants, stacking an additional 64 MB of L3 cache vertically on the core complex die using through-silicon vias (TSVs) for a total of 96 MB per eight-core CCX, targeted at gaming applications. This technology improves gaming performance by reducing latency and boosting frame rates by 20-35% in CPU-bound games, while also improving 1% low FPS for smoother gameplay and frame rate stability in cache-sensitive tasks like game engine simulations and rendering, providing an edge in steady execution of complex scenes in titles such as simulators, MMOs, and AAA games through further reduced cache miss rates, increased capacity, and direct access paths.

Specifications

Processor tables

The Zen 3 processors encompass a range of desktop and server models without integrated graphics, emphasizing high-performance computing across segments. Desktop variants utilize the AM4 socket and deliver 24 total PCIe 4.0 lanes, of which 20 are usable for devices like GPUs and NVMe storage, while supporting unlocked multipliers for overclocking on applicable models. Server configurations employ the SP3 socket and provide up to 128 PCIe 4.0 lanes per processor for expansive I/O scalability. The following table summarizes key specifications for representative desktop processors based on the Zen 3 :
ModelCores/ThreadsBase Clock (GHz)Boost Clock (GHz)L3 Cache (MB)TDP (W)Socket
9 5950X16/323.44.964105AM4
9 5900X12/243.74.864105AM4
7 5800X8/163.84.732105AM4
5 5600X6/123.74.63265AM4
Server processors in the 7003 series scale to higher core counts for applications, as shown in the representative models below:
ModelCores/ThreadsBase Clock (GHz)Boost Clock (GHz)L3 Cache (MB)TDP (W)Socket
776364/1282.453.5256280SP3
754332/642.803.70256225SP3
744324/482.854.00128200SP3
730316/322.403.4064130SP3
A notable variant is the 7 5800X3D, which incorporates 3D V-Cache technology to expand the L3 cache for enhanced gaming performance; it features 8 cores/16 threads, a 3.4 GHz base clock, up to 4.5 GHz boost, 96 MB L3 cache, 105 W TDP, and AM4 socket, launching on April 20, 2022.

APU tables

Zen 3-based APUs, codenamed Cezanne and its refresh Barcelo, combine up to eight Zen 3 CPU cores with integrated Radeon Vega graphics targeted at mobile client devices such as laptops and thin clients. These APUs utilize a monolithic die design fabricated on TSMC's 7 nm process, supporting DDR4-3200 or LPDDR4x-4266 memory and featuring soldered BGA packaging for compact, power-efficient form factors. The integrated graphics employ the Vega (GCN 5th generation) architecture with configurations ranging from 6 to 8 compute units (CUs), delivering up to 512 stream processors clocked as high as 2.1 GHz in higher-power variants. These iGPUs include multimedia engines with VCN 3.0 support for hardware-accelerated AV1 video decode, enabling efficient playback of modern video formats without discrete GPUs. Power scaling across these accommodates diverse laptop designs, with configurable (TDP) from 10 W in ultra-low-power U-series models for thin-and-light devices to 54 W in H-series and configurable HX variants for performance-oriented systems. All models feature unlocked multipliers for in supported platforms, though actual power limits are OEM-configurable via cTDP.
ModelCores/ThreadsBase Clock (GHz)Boost Clock (GHz)iGPU (CUs @ Peak GHz)TDP (W)Form Factor
7 5800U (Cezanne)8/161.94.4 8 (8 @ 2.0)15BGA, soldered
5 5600U (Cezanne)6/122.34.2 7 (7 @ 1.8)15BGA, soldered
3 5400U (Cezanne)4/82.64.0 6 (6 @ 1.6)15BGA, soldered
7 5825U (Barcelo)8/162.04.5 8 (8 @ 2.0)15BGA, soldered
ModelCores/ThreadsBase Clock (GHz)Boost Clock (GHz)iGPU (CUs @ Peak GHz)TDP (W, configurable)Form Factor
9 5980HS (Cezanne)8/163.04.8 8 (8 @ 2.1)35BGA, soldered
7 5800H (Cezanne)8/163.24.4 8 (8 @ 2.0)45BGA, soldered
9 5980HX (Cezanne)8/163.34.8 8 (8 @ 2.1)45 (up to 54)BGA, soldered
7 5825HS (Barcelo)8/163.04.5 8 (8 @ 2.0)35-54BGA, soldered

Products

Desktop processors

The Zen 3-based desktop processors, codenamed Vermeer for non-integrated graphics models, were released under the 5000 series branding starting in November 2020, targeting high-performance consumer PCs with unlocked multipliers for in the 5000X variants. These processors utilize the AM4 socket and require updates on compatible motherboards to enable full support. Integrated graphics variants, such as the Ryzen 5 5600G from the related Cezanne lineup, provide entry-level GPU capabilities for budget builds without discrete cards. Configurations in the Ryzen 5000 desktop lineup scale up to 16 cores and 32 threads in the flagship Ryzen 9 5950X, emphasizing multi-threaded workloads like content creation while maintaining strong single-threaded performance for everyday tasks. Backward compatibility extends to 300- and 400-series motherboards, including X370 and B450 chipsets, following manufacturer-provided BIOS firmware updates that add official Zen 3 support. Post-launch, the Ryzen 5000 series quickly dominated the desktop gaming market, capturing significant share from competitors through superior IPC gains and overall performance leadership in benchmarks. The Ryzen 7 5800X3D variant, introduced in April 2022, further amplified this by stacking additional 3D V-Cache to reach 96 MB of L3 cache, delivering frame rate improvements of 20-35% in CPU-bound games, with enhancements to 1% low FPS for smoother gameplay in cache-sensitive titles like simulators, MMOs, and AAA games—due to reduced latency in data access. This 3D V-Cache provides a much greater performance uplift in gaming compared to using low-latency RAM on non-X3D models, specifically addressing game-data latency for superior FPS gains in latency-sensitive workloads. In early 2025, extended the platform's lifecycle by announcing six new 5000G SKUs targeted at budget-oriented OEM systems, including the Ryzen 7 5705G (8 cores, up to 4.6 GHz boost) and lower-tier options like the Ryzen 3 5305G, all leveraging Zen 3 cores with integrated graphics for cost-effective AM4 upgrades. These additions sustain the series' relevance for entry-level desktops amid ongoing AM4 ecosystem support.

Mobile processors

The Zen 3-based mobile processors primarily utilize the Cezanne architecture, integrated into the 5000 series for laptops, targeting ultrabooks and high-performance portable devices. The U-series variants, such as the Ryzen 7 5800U with 8 cores and 16 threads at a 15 W TDP, emphasize low-power operation for thin-and-light ultrabooks, delivering up to 4.4 GHz boost clocks and 16 MB of L3 cache for efficient multitasking. In contrast, the H-series, exemplified by the Ryzen 9 5900HX with similar core counts but a configurable 45 W+ TDP, caters to creators and gamers in thicker chassis, supporting boost clocks up to 4.6 GHz for demanding workloads like and . These adaptations incorporate advanced thermal management, including dynamic voltage scaling and fine-grained , to balance performance within mobile form factors' constrained cooling envelopes. For embedded mobile applications, such as thin clients and compact systems, employs the Barcelo-R architecture, a Zen 3 variant optimized for reliability in low-power environments. These processors feature higher base clocks—up to 2.7 GHz in models like the 3 5425C—and support configurable TDPs as low as 10 W, enabling deployment in fanless designs with sustained performance for office productivity and light . Integrated Radeon Vega graphics provide basic visual acceleration, suitable for embedded displays without discrete GPUs. Zen 3 mobile implementations achieve up to 20% better power efficiency compared to Zen 2 equivalents at equivalent performance levels, primarily through a 19% increase in instructions per clock (IPC) and unified 16 MB L3 cache per core complex, reducing latency and power draw during idle and light loads. This translates to notable battery life extensions, with the Ryzen 7 5800U offering up to 17.5 hours of general usage and 21 hours of video playback on a standard laptop battery. These gains also enable support for Windows 11 features like DirectStorage, leveraging the architecture's PCIe 3.0 lanes for faster asset loading in compatible games and applications. Adoption of Zen 3 mobile processors peaked in premium laptops from major OEMs like , HP, and between 2021 and 2023, powering devices such as the ASUS ZenBook and series for professional and creative workflows. By 2025, these chips persist in budget-oriented models, including entry-level handhelds and refurbished systems, benefiting from ongoing updates and compatibility with modern OSes.

Server processors

The AMD EPYC 7003 series processors, codenamed and based on the , represent the primary server implementation for enterprise and data center environments, scaling up to 64 cores and 128 threads per socket with support for 8-channel DDR4 at speeds up to 3200 MT/s and 128 PCIe 4.0 lanes. These processors utilize a chiplet-based design with multiple compute dies connected via Infinity Fabric, enabling high core density while maintaining efficient inter-die communication for demanding server workloads. EPYC 7003 supports dual-socket configurations on the SP3 socket, interconnected through up to four xGMI links, which facilitates scalable systems for large-scale computing. NUMA optimizations, configurable via settings to support 1 to 8 nodes per socket, enhance access locality and I/O affinity, making it particularly suitable for cloud and virtualized environments where workload distribution across sockets is critical. Reliability features in the 7003 include enhanced RAS capabilities, such as advanced in the 8 Universal Memory Controllers operating in 6-way interleave mode, alongside secure memory encryption via Secure Nested Paging and Keys for user-level isolation. These processors also provide approximately 10% better compared to the prior EPYC 7002 generation in benchmarks like High-Performance Linpack on high-end models, contributing to lower in power-constrained data centers. Launched in 2021, the 7003 series saw rapid adoption by hyperscalers including cloud providers for general-purpose server deployments due to its performance leadership and scalability. As of 2025, these processors remain in use for cost-effective AI applications, supported by ongoing optimizations in containerized and environments that leverage their efficiency for edge and enterprise AI tasks.

Embedded processors

The AMD Ryzen Embedded V3000 series processors, built on the microarchitecture, are designed for rugged, long-lifecycle embedded systems, with configurations such as the Ryzen Embedded V3C48 providing 8 cores and 16 threads at a 45 W TDP within the broader series' 10-54 W power envelope. Unlike previous V-series processors, the V3000 series does not include integrated , targeting applications where discrete GPUs or no graphics are used. These processors emphasize reliability for 24/7 operations, offering up to 10 years of planned availability to support extended deployment cycles in industrial environments. Key features include an extended range of -40°C to 85°C on select SKUs like the V3C18I, enabling deployment in harsh conditions such as outdoor or factory settings. Additionally, the series provides up to 20 lanes of PCIe 4.0 connectivity, allowing integration of high-speed add-in cards for storage, networking, or expansion in compact systems, including discrete for display needs. These processors find applications in industrial PCs for and control, as well as systems requiring robust I/O capabilities. In 2025, production of the V3000 series continues to sustain legacy deployments, with ongoing security updates ensuring compatibility, while serving as a transitional option ahead of Zen 4-based embedded solutions like the Ryzen Embedded 7000 series.

Zen 3+

Architectural changes

Zen 3+ represents a process-optimized refresh of the , primarily targeted at mobile applications to enhance power efficiency without altering core instructions per clock (IPC) performance. The maintains the same as Zen 3 but leverages advancements in to reduce power consumption, making it suitable for battery-constrained devices. A key change is the shift to TSMC's 6 nm (N6) process node from the previous 7 nm (N7), enabling up to a 30% reduction in power usage for tasks like video conferencing while delivering comparable or better performance. This shrink improves overall energy efficiency per watt, with the design retaining compatibility with existing 7 nm ecosystem elements such as socket interfaces for mobile platforms. The monolithic die implementation in Zen 3+ further optimizes power delivery and thermal management compared to chiplet-based desktop variants. Memory support sees upgrades to DDR5-4800 and LPDDR5-6400, providing up to 102 GB/s of dual-channel bandwidth—approximately 1.5 times higher than prior generations' DDR4/LPDDR4X configurations. This enhancement boosts data throughput for integrated graphics and multitasking without requiring changes to the core from Zen 3. Additional refinements include an improved I/O subsystem with optional support for faster connectivity (up to 40 Gbps) and enhanced clocking for the integrated graphics, reaching up to 2.2 GHz to leverage the denser process node. These tweaks focus on peripheral efficiency and display output without impacting CPU core metrics. Zen 3+ was announced on January 4, 2022, with products available starting February 2022, serving as an interim solution to bridge to the more comprehensive architecture, with a strong emphasis on mobile power optimization.

Product implementations

The Zen 3+ architecture found its primary implementation in AMD's Ryzen 6000 series mobile processors, codenamed Rembrandt, which were released in early 2022 and targeted premium laptops with enhanced power efficiency and integrated graphics. These APUs utilize a TSMC 6nm process node for improved performance-per-watt, supporting up to eight Zen 3+ cores and 16 threads, along with DDR5/LPDDR5 memory and PCIe 4.0 connectivity. The integrated Radeon graphics, based on the RDNA 2 architecture, deliver up to 2.1 times the graphics performance of the prior generation, enabling better handling of creative workloads and light gaming without discrete GPUs. A flagship example is the 9 6980HX, featuring eight cores and 16 threads with a base clock of 3.3 GHz and boost up to 5.0 GHz, paired with a 680M iGPU comprising 12 compute units, all within a configurable 45W TDP . This configuration supports adaptive , including states that help save power during idle periods compared to Zen 3, making it suitable for thin-and-light premium ultrabooks. The series also introduced hardware-accelerated video decoding in the iGPU, improving efficiency for high-resolution streaming and video playback. Low-power variants, often referred to as Rembrandt-R configurations, extended Zen 3+ to ultrathin laptops and handheld devices through the U-series, such as the 7 6800U with eight cores and 16 threads clocked from 2.7 GHz base to 4.7 GHz boost, integrated 680M graphics, and a 15-28W TDP range. These models prioritize battery life, offering up to 29 hours of video playback while maintaining decode support for modern . Their compact design and efficiency enhancements made them ideal for portable form factors like convertible handhelds and entry-level creator devices. While Zen 3+ was predominantly a mobile-focused evolution, extended the broader Zen 3 on the desktop through a limited refresh of the 5000 series as the 5000XT lineup in mid-2024, featuring higher boost clocks on the existing 7nm Zen 3 cores—such as the Ryzen 7 5800XT at up to 4.8 GHz—without architectural changes to Zen 3+. These rebadged models supported the AM4 platform's DDR4 memory exclusively, with no native DDR5 integration, aiming to prolong affordability for legacy users. By 2025, Zen 3+ implementations like the 6000 series continued to appear in OEM laptops, particularly in budget and mid-range segments, where manufacturers rebranded or refreshed older stock to meet demand for cost-effective, efficient . In October 2025, rebranded select Zen 3+ processors as the 100 series for ongoing use in entry-level devices. This legacy support extended the ecosystem's relevance in entry-level ultrabooks and commercial devices, leveraging the architecture's mature power efficiency for extended battery life in everyday tasks. In January 2026, AMD's Ryzen executive teased the potential revival of Zen 3-based desktop CPUs in response to global DDR5 RAM shortages impacting adoption of the AM5 platform. The executive indicated that reintroducing these older chips is "something we're actively working on right now" to address soaring RAM prices. This announcement reflects broader industry responses to memory supply constraints, including rumors of Nvidia planning to reintroduce the GeForce RTX 3060 graphics card in the first quarter of 2026.

References

  1. https://www.tomshardware.com/news/amd-zen-3-ryzen-5000-announcement-19-percent-ipc-1080p-gaming-lead
  2. https://www.amd.com/en/technologies/zen-core.html
  3. https://www.amd.com/en/products/processors/server/epyc/7003-series.html
  4. https://hothardware.com/news/amd-roadmaps-zen-3-status-zen-4-rdna2-on-track
  5. https://www.kitguru.net/components/cpu/james-dawson/amd-announce-future-specifications-and-roadmap-for-epyc-processors/
  6. https://www.tomshardware.com/reviews/amd-ryzen-9-5950x-5900x-zen-3-review/2
  7. https://www.amd.com/content/dam/amd/en/documents/solutions/technologies/chiplet-architecture-white-paper.pdf
  8. https://www.tomshardware.com/news/scalping-pricing-trends-suggest-ryzen-5000-supply-improving
  9. https://chipsandcheese.com/p/pushing-amds-infinity-fabric-to-its
  10. https://www.techpowerup.com/298338/amd-zen-4-dies-transistor-counts-cache-sizes-and-latencies-detailed
  11. https://www.tomshardware.com/features/ryzen-5000-ram-guide
  12. https://www.amd.com/en/products/processors/technologies/3d-v-cache.html
  13. https://www.techpowerup.com/285307/amd-zen-3-3d-vertical-cache-detailed-some-more
  14. https://www.techspot.com/review/2635-ryzen-7950x3d-memory-scaling/
  15. https://forums.anandtech.com/threads/raptor-lake-official-thread.2599551/post-40863000
  16. https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5600x-tested
  17. https://en.wikichip.org/wiki/amd/microarchitectures/zen_3
  18. https://chipsandcheese.com/p/measuring-zen-3s-bottlenecks
  19. https://www.tomshardware.com/news/amd-zen-3-ryzen-5000-release-date-specifications-pricing-benchmarks-all-we-know
  20. https://chipsandcheese.com/p/deep-diving-zen-3-v-cache
  21. https://www.techspot.com/review/2248-amd-ryzen-7-5800x3d/
  22. https://www.tomshardware.com/reviews/amd-ryzen-7-5800x3d-cpu-review
  23. https://www.amd.com/en/blogs/2024/amd-epyc-cpus-deliver-breakthrough-performance-wi.html
  24. https://www.amd.com/en/products/specifications/processors.html
  25. https://www.amd.com/content/dam/amd/en/documents/products/processors/ryzen/5000/amd-ryzen-5000-datasheet.pdf
  26. https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/datasheets/amd-epyc-7003-series-product-datasheet.pdf
  27. https://www.amd.com/en/products/processors/server/epyc/7003-series/amd-epyc-7303.html
  28. https://www.amd.com/en/products/processors/desktops/ryzen/5000-series/amd-ryzen-7-5800x3d.html
  29. https://ir.amd.com/news-events/press-releases/detail/1053/amd-launches-the-ultimate-gaming-processor-brings-enthusiast-performance-to-an-expanded-lineup-of-ryzen-desktop-processors
  30. https://en.wikichip.org/wiki/amd/cores/cezanne
  31. https://www.notebookcheck.net/AMD-Radeon-RX-Vega-8-Ryzen-4000-5000-GPU-Benchmarks-and-Specs.453150.0.html
  32. https://www.techpowerup.com/275702/amd-ryzen-5000-mobile-series-specifications-leaked
  33. https://www.tomshardware.com/news/amds-ryzen-5000-barcelo-apus-surface-in-hps-new-laptops
  34. https://www.tomshardware.com/news/amd-exploring-ryzen-5000-support-on-300-series
  35. https://hothardware.com/news/amd-300-series-motherboards-with-ryzen-5000-cpu
  36. https://www.tomshardware.com/pc-components/cpus/ryzen-to-the-top-how-amd-innovated-in-the-gaming-cpu-market
  37. https://www.tomshardware.com/pc-components/cpus/gigabyte-x3d-turbo-mode-promises-up-to-35-percent-higher-gaming-performance
  38. https://www.techpowerup.com/333136/amd-lists-six-new-ryzen-5000g-skus-zen-3s-lifespan-extended-again
  39. https://www.tomshardware.com/pc-components/cpus/amd-breathes-life-into-ryzen-5000g-family-with-six-new-chips-cezanne-with-up-to-eight-zen-3-cores-and-4-6-ghz-boost-clocks
  40. https://www.amd.com/en/newsroom/press-releases/2021-1-12-amd-announces-world-s-best-mobile-processors-in-c.html
  41. https://www.tomshardware.com/news/amd-ryzen-5000-mobile-cezanne-soc-architecture-deep-dive-zen-3-powers-into-notebooks
  42. https://www.amazon.com/MALLRACE-Graphics-Notebook-Computer-Keyboard/dp/B0FQSQ186F
  43. https://docs.amd.com/v/u/en-US/overview-amd-epyc7003-series-processors-microarchitecture
  44. https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/tuning-guides/data-plane-development-kit-tuning-guide-amd-epyc7003-series-processors.pdf
  45. https://infohub.delltechnologies.com/p/amd-milan-bios-characterization-for-hpc/
  46. https://www.amd.com/en/newsroom/press-releases/2021-3-15-amd-epyc-7003-series-cpus-set-new-standard-as-hig.html
  47. https://datacentremagazine.com/technology-and-ai/amd-unveils-new-line-epyc-processors-hpc
  48. https://www.amd.com/en/blogs/2025/amd--mwc-2025-advancing-ai-from-the-enterprise-.html
  49. https://neuralservers.com/collections/ai-inference
  50. https://www.amd.com/en/products/embedded/ryzen/ryzen-v3000-series.html
  51. https://www.amd.com/en/newsroom/press-releases/2022-9-27-amd-launches-ryzen-embedded-v3000-series-processor.html
  52. https://www.adlinktech.com/en/amd-based-solutions
  53. https://www.amd.com/en/products/embedded/ryzen.html
  54. https://www.amd.com/en/resources/product-security/bulletin/amd-sb-5004.html
  55. https://www.amd.com/en/newsroom/press-releases/2022-1-4-amd-unveils-new-ryzen-mobile-processors-uniting-z.html
  56. https://www.tomshardware.com/news/amds-6nm-ryzen-6000-rembrandt-chips-have-zen-3-rdna2-and-ddr5
  57. https://www.tomshardware.com/news/amd-usb4-chipset-driver-update-for-ryzen-6000
  58. https://www.techpowerup.com/cpu-specs/ryzen-5-pro-6650h.c2769
  59. https://ir.amd.com/news-events/press-releases/detail/1039/amdunveils-new-ryzen-mobile-processors-uniting-zen-3-core-with-amd-rdna-2-graphics-in-powerhousedesign
  60. https://www.techpowerup.com/292118/amd-zen3-architecture-and-ryzen-6000-rembrandt-mobile-processors-detailed
  61. https://www.amd.com/en/partner/articles/ryzen-6000-series-mobile-processors.html
  62. https://www.notebookcheck.net/AMD-Ryzen-9-6980HX-Processor-Benchmarks-and-Specs.589850.0.html
  63. https://www.tomshardware.com/news/amd-6nm-ryzen-6000-rembrandt-soc-deep-dive-gunning-for-alder-lake
  64. https://www.notebookcheck.net/AMD-Ryzen-7-6800U-Processor-Benchmarks-and-Specs.589897.0.html
  65. https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-6000-series/amd-ryzen-7-6800u.html
  66. https://www.kitguru.net/lifestyle/mobile/laptops/luke-hill/amd-ryzen-7-6800u-review-with-asus-zenbook-s-13-oled/all/1/
  67. https://www.amd.com/en/products/processors/desktops/ryzen/5000-series/amd-ryzen-7-5800xt.html
  68. https://arstechnica.com/gadgets/2025/10/amd-shores-up-its-budget-laptop-cpus-by-renaming-more-years-old-silicon/
  69. https://www.amazon.com/ryzen-6000-laptop/s?k=ryzen%2B6000%2Blaptop
  70. https://www.tomshardware.com/pc-components/cpus/amd-ryzen-chief-teases-return-of-older-zen-3-chips-to-fight-soaring-ram-prices-thats-something-were-actively-working-on-right-now
  71. https://wccftech.com/nvidia-to-bring-back-geforce-rtx-3060-q1-2026-tackle-memory-shortages/
Add your contribution
Related Hubs
Contribute something
User Avatar
No comments yet.