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Phase detector
View on Wikipedia | This article includes a list of general references, but it lacks sufficient corresponding inline citations. (June 2018) |
A phase detector or phase comparator is a frequency mixer, analog multiplier or logic circuit that generates a signal which represents the difference in phase between two signal inputs.
The phase detector is an essential element of the phase-locked loop (PLL). Detecting phase difference is important in other applications, such as motor control, radar and telecommunication systems, servo mechanisms, and demodulators.
Types
[edit]Phase detectors for phase-locked loop circuits may be classified in two types.[1] A Type I detector is designed to be driven by analog signals or square-wave digital signals and produces an output pulse at the difference frequency. The Type I detector always produces an output waveform, which must be filtered to control the phase-locked loop voltage-controlled oscillator (VCO). A type II detector is sensitive only to the relative timing of the edges of the input and reference pulses and produces a constant output proportional to phase difference when both signals are at the same frequency. This output will tend not to produce ripple in the control voltage of the VCO.
Analog phase detector
[edit]The phase detector needs to compute the phase difference of its two input signals. Let α be the phase of the first input and β be the phase of the second. The actual input signals to the phase detector, however, are not α and β, but rather sinusoids such as sin(α) and cos(β). In general, computing the phase difference would involve computing the arcsine and arccosine of each normalized input (to get an ever-increasing phase) and doing a subtraction. Such an analog calculation is difficult. Fortunately, the calculation can be simplified by using some approximations.
Assume that the phase differences will be small (much less than 1 radian, for example). The small-angle approximation for the sine function and the sine angle addition formula yield:
The expression suggests a quadrature phase detector can be made by summing the outputs of two multipliers. The quadrature signals may be formed with phase shift networks. Two common implementations for multipliers are the double balanced diode mixer, diode ring and the four-quadrant multiplier, Gilbert cell.
Instead of using two multipliers, a more common phase detector uses a single multiplier and a different trigonometric identity:
The first term provides the desired phase difference. The second term is a sinusoid at twice the reference frequency, so it can be filtered out. In the case of general waveforms the phase detector output is described with the phase detector characteristic.
A mixer-based detector (e.g., a Schottky diode-based double-balanced mixer) provides "the ultimate in phase noise floor performance" and "in system sensitivity." since it does not create finite pulse widths at the phase detector output.[2] Another advantage of a mixer-based PD is its relative simplicity.[2] Both the quadrature and simple multiplier phase detectors have an output that depends on the input amplitudes as well as the phase difference. In practice, the input amplitudes of input signals are normalized prior to input into the detector to remove the amplitude dependency.
Digital phase detector
[edit]
A phase detector suitable for square wave signals can be made from an exclusive-OR (XOR) logic gate. When the two signals being compared are completely in-phase, the XOR gate's output will have a constant level of zero. When the two signals differ in phase by 1°, the XOR gate's output will be high for 1/180th of each cycle — the fraction of a cycle during which the two signals differ in value. When the signals differ by 180° — that is, one signal is high when the other is low, and vice versa — the XOR gate's output remains high throughout each cycle. This phase detector requires inputs that are symmetrical square waves, or nearly so.
The XOR detector compares well to the analog mixer in that it locks near a 90° phase difference and has a pulse wave output at twice the reference frequency. The output changes duty cycle in proportion to the phase difference. Applying the XOR gate's output to a low-pass filter results in an analog voltage that is proportional to the phase difference between the two signals. The remainder of its characteristics are very similar to the analog mixer for capture range, lock time, reference spurious and low-pass filter requirements.
Digital phase detectors can also be based on a sample and hold circuit, a charge pump, or a logic circuit consisting of flip-flops. When a phase detector based on logic gates is used in a PLL, it can quickly force the VCO to synchronize with an input signal, even when the frequency of the input signal differs substantially from the initial frequency of the VCO. Such phase detectors also have other desirable properties, such as better accuracy when there are only small phase differences between the two signals being compared and superior pull-in range.
Phase frequency detector
[edit]A phase frequency detector (PFD) is an asynchronous circuit originally made of four flip-flops (i.e., the phase-frequency detectors found in both the RCA CD4046 and the motorola MC4344 ICs introduced in the 1970s). The logic determines which of the two signals has a zero-crossing earlier or more often. When used in a PLL application, lock can be achieved even when it is off frequency.
The PFD improves the pull-in range and lock time over simpler phase detector designs such as multipliers or XOR gates. Those designs work well when the two input phases are already near lock or in lock, but perform poorly when the phase difference is too large. When the phase difference is too large (which will happen when the instantaneous frequency difference is large), then the sign of the loop gain can reverse and start driving the VCO away from lock. The PFD has the advantage of producing an output even when the two signals being compared differ not only in phase but in frequency. A phase frequency detector prevents a false lock condition in PLL applications, in which the PLL synchronizes with the wrong phase of the input signal or with the wrong frequency (e.g., a harmonic of the input signal).[3]
A bang-bang charge pump phase frequency detector supplies current pulses with fixed total charge, either positive or negative, to the capacitor acting as an integrator. A phase detector for a bang-bang charge pump must always have a dead band where the phases of inputs are close enough that the detector fires either both or neither of the charge pumps, for no total effect. Bang-bang phase detectors are simple but are associated with significant minimum peak-to-peak jitter, because of drift within the dead band.
In 1976 it was shown that by using a three-state phase frequency detector configuration (using only two flip-flops) instead of the original RCA/Motorola four flip-flops configurations, this problem could be elegantly overcome.[citation needed] For other types of phase-frequency detectors other, though possibly less-elegant, solutions exist to the dead zone phenomenon.[3] Other solutions are necessary since the three-state phase-frequency detector does not work for certain applications involving randomized signal degradation, which can be found on the inputs to some signal regeneration systems (e.g., clock recovery designs).[4]
A proportional phase detector employs a charge pump that supplies charge amounts in proportion to the phase error detected. Some have dead bands and some do not. Specifically, some designs produce both up and down control pulses even when the phase difference is zero. These pulses are small, nominally the same duration, and cause the charge pump to produce equal-charge positive and negative current pulses when the phase is perfectly matched. Phase detectors with this kind of control system don't exhibit a dead band and typically have lower minimum peak-to-peak jitter when used in PLLs.
In PLL applications it is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out-of-lock condition.
Electronic phase detector
[edit]Some signal processing techniques such as those used in radar may require both the amplitude and the phase of a signal, to recover all the information encoded in that signal. One technique is to feed an amplitude-limited signal into one port of a product detector and a reference signal into the other port; the output of the detector will represent the phase difference between the signals.
Optical phase detectors
[edit]In optics phase detectors are also known as interferometers. For pulsed (amplitude modulated) light, it is said to measure the phase between the carriers. It is also possible to measure the delay between the envelopes of two short optical pulses by means of cross correlation in a nonlinear crystal. And it is possible to measure the phase between the envelope and the carrier of an optical pulse, by sending a pulse into a nonlinear crystal. There the spectrum gets wider and at the edges the shape depends significantly on the phase.
See also
[edit]References
[edit]- ^ Paul Horowitz and Winfield Hill, The Art of Electronics 2nd Ed. Cambridge University Press, Cambridge, 1989 ISBN 0-521-37095-7 pg. 644
- ^ a b Crawford 1994, pp. 9, 19
- ^ a b Crawford 1994, pp. 17–23, 153, and several other pages
- ^ Wolaver 1991, p. 211
- Crawford, James A. (1994), Frequency Synthesizer Design Handbook, Artech House, ISBN 0-89006-440-7
- Wolaver, Dan H. (1991), Phase-Locked Loop Circuit Design, Prentice Hall, ISBN 0-13-662743-9
- Devon Fernandez and Sanjeev Manandhar (8 December 2003). "Digital Phase Locked Loop" (PDF). Retrieved 2006-04-25.
- Zilic, Zeljko (2001-08-17). "Phase- and Delay-Locked Loop Clock Control in Digital Systems". TechOnLine. Archived from the original on 2006-05-15. Retrieved 2006-04-25.
- Mike Curtin and Paul O'Brien (July–August 1999). "Phase Locked Loops for High-Frequency Receivers and Transmitters-3". Analog Dialogue. Analog Devices. Retrieved 2006-04-25.
Further reading
[edit]- Egan, William F. (2000), Frequency Synthesis by Phase-lock (2nd ed.), John Wiley & Sons, ISBN 0-471-32104-4
External links
[edit]Phase detector
View on GrokipediaFundamentals
Definition and purpose
A phase detector (PD), also known as a phase comparator, is a circuit or device that compares the phases of two input signals of the same frequency and produces an output signal proportional to their phase difference.[1] This output typically manifests as a voltage level or pulse width that directly corresponds to the extent and direction of the phase offset between the signals.[4] The primary purpose of a phase detector is to quantify phase error in feedback systems, enabling synchronization of oscillators or signals to a reference.[2] It serves as a core component in phase-locked loops (PLLs), where it drives corrective adjustments to align the phase of a voltage-controlled oscillator with an input reference, thus achieving stable frequency and phase locking.[5] When integrated with additional elements like charge pumps, phase detectors can also facilitate frequency detection by responding to both phase and frequency discrepancies.[2] Phase detectors were first conceptualized in the 1930s for radio receivers, marking an early milestone in phase comparison techniques.[6] A key advancement occurred in the 1950s and 1960s through integration into PLLs, exemplified by Donald Richman's 1954 development of acquisition time equations for first-order PLLs applied to color television synchronization.[7] Notably, phase detector outputs vary by type, producing a DC voltage in analog implementations or pulse trains in digital ones, which in turn shapes the design of subsequent loop filters in feedback control systems.[4] Analog and digital variants differ primarily in their signal processing approaches but share the fundamental goal of phase error measurement.[1]Basic operating principles
A phase detector compares a reference signal (REF) with a variable signal (VAR), both typically sinusoidal at the same nominal frequency, to produce an output voltage that represents their phase difference θ = φ_VAR - φ_REF, where φ denotes the phase of each signal.[8] The output is ideally a DC level after low-pass filtering, enabling feedback systems to align the phases.[5] The fundamental operation relies on nonlinear mixing of the inputs, often via multiplication, yielding a transfer characteristic V_out = K_d \sin(\theta), where K_d is the phase detector gain in volts per radian, determined by the input amplitudes and circuit parameters.[8] To derive this, consider REF = A \cos(\omega t) and VAR = A \cos(\omega t + \theta). Their product is \frac{A^2}{2} [\cos(2\omega t + \theta) + \cos(\theta)]. A low-pass filter removes the high-frequency term at 2\omega, leaving V_out = \frac{A^2}{2} \cos(\theta). If the reference uses a quadrature sinusoid, such as A \sin(\omega t), the low-pass output becomes \frac{A^2}{2} \sin(\theta), with K_d = \frac{A^2}{2}.[9] This sinusoidal response arises from the trigonometric identity for the product of sinusoids, ensuring the output encodes the instantaneous phase error.[8] For small phase differences, where |\theta| \ll \pi/2, the sine function linearizes as \sin(\theta) \approx \theta, yielding the approximation V_out \approx K_d \theta.[9] This linear region is crucial for stable operation in feedback loops, as it provides a proportional error signal. Conceptually, the inputs are two waveforms offset by θ; the detector mixes them to generate sum and difference frequencies, but at matched frequencies (\omega_REF = \omega_VAR = \omega), the difference term collapses to DC, modulated by the phase offset—visualize aligned peaks for θ=0 (maximum positive output), shifting to antiphase at θ=π (zero or minimum), with the filtered envelope tracing the sine curve.[5] The transfer function is generally periodic with period 2π due to phase wrapping, resulting in a sinusoidal or triangular shape depending on the mixing mechanism, which repeats every full cycle of phase difference.[8] Phase detectors perform optimally when the input frequencies match nominally; mismatches introduce beat frequencies in the output, manifesting as spurious tones (spurs) or preventing stable DC locking, as the phase error evolves continuously rather than statically.[10]Classification
Analog phase detectors
Analog phase detectors are electronic circuits that employ continuous-time analog components, such as multipliers or mixers, to generate an output voltage proportional to the phase difference between two input signals of identical frequency, making them particularly suitable for radio frequency (RF) applications in phase-locked loops (PLLs).[11] These devices produce a smooth, analog output without discrete steps, enabling precise phase measurement in systems requiring high resolution, such as frequency modulation (FM) demodulators.[12] A primary type is the multiplier phase detector, which utilizes a double-balanced mixer to compute the product of the input signals after low-pass filtering to extract the DC component representing the phase difference. In this configuration, the two inputs—typically sine waves with amplitudes and and phase difference —yield an output voltage of For signals with peak voltages and , the full transfer function simplifies to , where the detector gain .[1] This cosine response provides a linear region around , ideal for locking in analog PLLs, though the output exhibits nulls at odd multiples of .[11] Double-balanced mixers, often implemented with a diode ring or transistor-based structures, suppress unwanted carrier feedthrough and offer high port isolation, enhancing performance in RF environments.[13] Another key type is the switching phase detector, which operates by using diodes or transistors to sample one input signal using pulses derived from the other, effectively multiplying the signals in a switching manner to produce a phase-proportional output. This approach, common in high-frequency analog systems, relies on the switching elements to commutate the signal, filtering the result to obtain a DC voltage indicative of .[11] For instance, Schottky diodes or bipolar transistors can form the switching network, providing fast response times suitable for RF sampling without requiring complex multiplication.[13] Analog phase detectors exhibit high dynamic range, often exceeding 60 dB, allowing operation across wide input power levels, but they are sensitive to amplitude variations in the inputs, which can distort the phase measurement if not amplitude-limited prior to detection.[14] Their smooth output avoids quantization noise inherent in digital alternatives, making them preferable for applications demanding low-noise, continuous phase tracking. A representative implementation is the Gilbert cell multiplier, a four-quadrant analog multiplier circuit using cross-coupled transistor pairs to achieve precise multiplication with subnanosecond response, widely adopted in integrated RF PLLs since the late 1960s. These detectors have been integral to analog PLLs for FM demodulation since the 1950s, enabling robust signal recovery in early communication systems.[12]Digital phase detectors
Digital phase detectors utilize digital logic components, such as gates and counters, to compare the phases of two input signals and generate binary or pulse-based outputs that represent the phase difference.[15] These devices are particularly suited for integrated circuits due to their simplicity and compatibility with binary signal processing.[1] The most common type is the XOR-gate phase detector, which employs an exclusive-OR logic gate to produce an output pulse whose duty cycle is proportional to the phase difference between the two inputs, assuming square-wave signals of the same frequency.[16] The XOR output is high whenever the inputs differ, resulting in pulses that occur during the phase offset period; this output is typically low-pass filtered to yield an average DC voltage representing the phase error.[1] For inputs with 50% duty cycles, the average output voltage is given by where is the supply voltage and is the phase difference in radians, with an effective linear range of 0 to .[16] Waveform analysis shows that at , the output is constantly low (zero average), increasing linearly to a maximum pulse width at , where the signals are fully inverted relative to each other.[15] Other variants include AND-gate and NAND-gate phase detectors, which provide outputs based on the overlap of the input signals but are limited to smaller phase ranges, typically 0 to , due to their dependence on simultaneous high states at both inputs.[15] These gates produce shorter pulses for phase alignment and are less commonly used than XOR types because of their narrower detection window and sensitivity to signal timing.[1] Digital phase detectors like the XOR type were introduced in the 1970s alongside the rise of CMOS integrated circuits, enabling compact implementations in early digital phase-locked loops (PLLs).[15] They are insensitive to input amplitude variations as long as logic thresholds are met, but require inputs with precisely 50% duty cycles to maintain linearity; deviations can distort the phase measurement.[16] A practical example is the use of the 74HC86 quad XOR gate IC, which provides a low-cost, off-the-shelf solution for building phase detectors in discrete or hybrid circuits.[16] A key drawback is the false zero-crossing at multiples of , where the output average returns to zero despite a full phase shift, potentially causing the detector to lock onto harmonics of the input signal rather than the fundamental frequency.[16] This harmonic locking issue limits their reliability in applications requiring unambiguous phase detection over wide ranges.[15] In PLLs, digital phase detectors such as these contribute to loop stability by providing pulse outputs that drive voltage-controlled oscillators.[1]Phase-frequency detectors
A phase-frequency detector (PFD) is a digital variant of a phase detector designed to detect both phase and frequency differences between a reference signal and a feedback signal, producing separate up and down output pulses proportional to these errors; it is typically implemented using edge-triggered D flip-flops configured as an up-down counter.[10] This architecture enables wide capture and lock ranges in phase-locked loops (PLLs), addressing limitations of phase-only detectors by ensuring the loop can acquire signals even when frequencies differ significantly.[2] In operation, the PFD compares the rising edges of the reference (REF) and variable (VAR) inputs. If the REF edge precedes the VAR edge, an UP pulse is asserted with a duration corresponding to the time difference until the VAR edge arrives; conversely, if the VAR edge precedes the REF edge, a DOWN pulse is generated until the REF edge occurs. When the signals are phase- and frequency-locked, both outputs remain inactive (logic low or high-impedance, depending on implementation), producing no net error signal.[17] The pulse widths are directly related to the phase error θ by the equation τ = |θ| / (2π f_ref), where f_ref is the reference frequency and τ is the pulse duration; the phase detector gain is K_d = V_dd / (2 π ) for full-scale output from 0 to supply voltage V_dd.[10] PFDs were developed in the 1980s specifically for charge-pump PLLs, where they eliminate false locking problems inherent in simpler digital phase detectors like XOR gates, which can synchronize to harmonics rather than the fundamental frequency.[18] A representative example is the phase comparator PC2 in the 74HC4046 integrated circuit, which integrates a PFD alongside other detector types for versatile PLL applications up to several MHz.[19] These detectors exhibit linear response over the full 2π radian phase range, providing a constant gain slope that supports stable locking without ambiguity, but they can suffer from a dead zone—a region of insensitivity to small phase errors—if the internal reset delay between flip-flops is insufficient to generate minimum pulse widths, leading to missed edge detections near lock.[10] Proper design of the reset mechanism, often incorporating a short delay, mitigates this issue while preserving frequency discrimination.Implementations
Electronic phase detectors
Electronic phase detectors are hardware components realized through silicon integrated circuits or discrete electronic elements, enabling phase comparison in both radio frequency (RF) and baseband signal processing domains.[20] These implementations leverage semiconductor technologies to produce an output voltage or current proportional to the phase difference between input signals, facilitating synchronization in phase-locked loops (PLLs) and related systems. Analog electronic phase detectors often employ diode-based mixer circuits, where Schottky diodes serve as key elements for RF applications in the 1-10 GHz range. In such configurations, the diodes act as nonlinear elements to generate sum and difference frequencies from the input signals, with low-pass filtering extracting the phase-difference component; this approach provides broadband operation but requires careful balancing to suppress carrier feedthrough.[21][14] For lower-frequency baseband use, op-amp-based squaring circuits multiply the input signals after conversion to square waves, yielding a DC output proportional to the cosine of the phase difference; these utilize high-speed op-amps like the EL5100 for switching and amplification, achieving detection up to several MHz with minimal distortion. Digital electronic phase detectors typically rely on logic gates or flip-flops for discrete-time phase comparison, suitable for clock recovery and frequency synthesis. A common phase-frequency detector (PFD) implementation uses two D flip-flops, such as those in the 74LS74 dual D flip-flop IC with added reset logic via NAND gates, to generate up/down pulses indicating phase lead or lag; this configuration operates up to 25 MHz and eliminates dead zones through edge-triggered detection.[22] For low-power applications, CMOS XOR gates provide a simple binary phase detector, producing a pulse-width-modulated output averaged to yield the phase error; implementations in 45 nm CMOS achieve operation beyond 1 GHz with reduced transistor count for portable devices.[16] The development of electronic phase detectors traces back to vacuum tube circuits in the 1940s, where triode-based mixers enabled early radar and communication PLLs, evolving to gallium arsenide (GaAs) Schottky devices today for high-speed millimeter-wave applications in 5G networks operating above 20 GHz.[23][24] Typical power consumption for these detectors ranges from 1-10 mW in CMOS or GaAs ICs, balancing performance with efficiency in battery-constrained systems. Integration of phase detectors into monolithic PLL ICs, such as the CD4046, combines the detector with a voltage-controlled oscillator and filter on a single CMOS chip, supporting frequencies up to 1.3 MHz for cost-effective synchronization in digital circuits.[25] In printed circuit board (PCB) layouts, minimizing phase noise involves solid ground planes, decoupling capacitors near power pins, and short, symmetric traces to reduce parasitic inductance and coupling between reference and feedback paths.[26]Optical phase detectors
Optical phase detectors are specialized devices designed to measure phase differences between two optical waves, primarily by exploiting interference patterns generated upon their recombination. These detectors are essential in optical systems where phase information carries critical data, such as in fiber-optic communications and sensing applications. Unlike electronic counterparts, optical phase detectors operate directly on light signals, leveraging photonic structures to achieve high-speed and low-loss phase comparison.[27] A key principle underlying many optical phase detectors is interferometry, exemplified by the Mach-Zehnder interferometer (MZI). In an MZI configuration, an input optical beam is divided into two paths by a beam splitter; one path may introduce a phase shift due to environmental factors or deliberate modulation, and the beams are then recombined at a second beam splitter. The resulting interference produces output intensities that depend on the phase difference between the paths, described by the equation for one output port:where is the input intensity. The complementary output follows , allowing differential measurement to enhance sensitivity. This setup converts phase variations into detectable intensity changes, with the phase difference related to path length variation by , where is the optical wavelength and is the path difference.[27][28] Homodyne detection represents another core principle, particularly for precise phase extraction in coherent optical systems. Here, the signal beam is interfered with a phase-locked local oscillator (LO) beam using a 50:50 beam splitter, and the outputs are directed to a pair of balanced photodiodes. The photodiodes generate currents and , and their difference yields a signal proportional to the phase quadrature of the input field, effectively demodulating the phase information while suppressing common-mode noise from the LO. This balanced configuration achieves high common-mode rejection ratios exceeding 50 dB, making it ideal for weak signal detection. Additionally, fringe visibility , which quantifies interference contrast, is given by
serving as a metric for system coherence and alignment quality.[29][30][31] Optical phase detectors first emerged prominently in the 1980s alongside advancements in fiber-optic technology, driven by the need for coherent detection in high-capacity transmission systems. Early developments focused on integrating interferometric techniques with single-mode fibers to enable phase-sensitive amplification and demodulation, marking a shift from intensity-based to phase-based optical signaling.[32] In applications like coherent LIDAR, optical phase detectors facilitate precise ranging and velocity measurements by analyzing beat frequencies from frequency-modulated continuous-wave signals. Integrated photonic implementations on silicon-on-insulator (SOI) platforms have advanced significantly in the 2020s, enabling compact, CMOS-compatible chips with cascaded phase shifters for beam steering and on-chip detection, achieving resolutions suitable for automotive and remote sensing.[33][34] For unambiguous phase detection across full ranges, quadrature optical phase detectors employ two orthogonal interferometers or phase-shifted outputs (e.g., at 0° and 90°) to resolve the sign and magnitude of , avoiding the 2π ambiguity inherent in single-output systems. However, these detectors face challenges such as polarization sensitivity, where misalignment in beam polarizations can degrade fringe visibility and introduce errors, necessitating polarization diversity schemes or controllers to maintain performance.[35][36]