Hubbry Logo
Reversible computingReversible computingMain
Open search
Reversible computing
Community hub
Reversible computing
logo
7 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
Contribute something
Reversible computing
Reversible computing
Reversible computing
View on Wikipedia
from Wikipedia

Reversible computing is any model of computation where every step of the process is time-reversible. This means that, given the output of a computation, it is possible to perfectly reconstruct the input. In systems that progress deterministically from one state to another, a key requirement for reversibility is a one-to-one correspondence between each state and its successor. Reversible computing is considered an unconventional approach to computation and is closely linked to quantum computing, where the principles of quantum mechanics inherently ensure reversibility (as long as quantum states are not measured or "collapsed").[1]

Reversibility

[edit]

There are two major, closely related types of reversibility that are of particular interest for this purpose: physical reversibility and logical reversibility.[2]

A process is said to be physically reversible if it results in no increase in physical entropy; it is isentropic. There is a style of circuit design ideally exhibiting this property that is referred to as charge recovery logic, adiabatic circuits, or adiabatic computing (see Adiabatic process). Although in practice no nonstationary physical process can be exactly physically reversible or isentropic, there is no known limit to the closeness with which we can approach perfect reversibility, in systems that are sufficiently well isolated from interactions with unknown external environments, when the laws of physics describing the system's evolution are precisely known.

A motivation for the study of technologies aimed at implementing reversible computing is that they offer what is predicted to be the only potential way to improve the computational energy efficiency (i.e. useful operations performed per unit energy dissipated) of computers beyond the fundamental von Neumann–Landauer limit[3][4] of kT ln(2) energy dissipated per irreversible bit operation.

The Landauer limit was millions of times below the energy consumption of computers in the 2000s and thousands of times less in the 2010s.[5] Reversible computing proponents argue that a significant portion of this energy consumption is due to architectural overheads. These overheads are the energy costs associated with non-computational parts of the system, such as wires, transistors, and memory, that are required to make a computer work. They believe that makes it difficult for current technology to achieve much greater energy efficiency without adopting reversible computing principles. [6]

Relation to thermodynamics

[edit]

As was first argued by Rolf Landauer while working at IBM,[7] in order for a computational process to be physically reversible, it must also be logically reversible. Landauer's principle is the observation that the oblivious erasure of n bits of known information must always incur a cost of nkT ln(2) in thermodynamic entropy. A discrete, deterministic computational process is said to be logically reversible if the transition function that maps old computational states to new ones is a one-to-one function; i.e. the output logical states uniquely determine the input logical states of the computational operation.

For computational processes that are nondeterministic (in the sense of being probabilistic or random), the relation between old and new states is not a single-valued function, and the requirement needed to obtain physical reversibility becomes a slightly weaker condition, namely that the size of a given ensemble of possible initial computational states does not decrease, on average, as the computation proceeds forwards.

Physical reversibility

[edit]

Landauer's principle (and indeed, the second law of thermodynamics) can also be understood to be a direct logical consequence of the underlying reversibility of physics, as is reflected in the general Hamiltonian formulation of mechanics, and in the unitary time-evolution operator of quantum mechanics more specifically.[8]

The implementation of reversible computing thus amounts to learning how to characterize and control the physical dynamics of mechanisms to carry out desired computational operations so precisely that the experiment accumulates a negligible total amount of uncertainty regarding the complete physical state of the mechanism, per each logic operation that is performed. In other words, precisely track the state of the active energy that is involved in carrying out computational operations within the machine, and design the machine so that the majority of this energy is recovered in an organized form that can be reused for subsequent operations, rather than being permitted to dissipate into the form of heat.

Although achieving this goal presents a significant challenge for the design, manufacturing, and characterization of ultra-precise new physical mechanisms for computing, there is at present no fundamental reason to think that this goal cannot eventually be accomplished, allowing someday to build computers that generate much less than 1 bit's worth of physical entropy (and dissipate much less than kT ln 2 energy to heat) for each useful logical operation that they carry out internally.

Today, the field has a substantial body of academic literature. A wide variety of reversible device concepts, logic gates, electronic circuits, processor architectures, programming languages, and application algorithms have been designed and analyzed by physicists, electrical engineers, and computer scientists.

This field of research awaits the detailed development of a high-quality, cost-effective, nearly reversible logic device technology, one that includes highly energy-efficient clocking and synchronization mechanisms, or avoids the need for these through asynchronous design. This sort of solid engineering progress will be needed before the large body of theoretical research on reversible computing can find practical application in enabling real computer technology to circumvent the various near-term barriers to its energy efficiency, including the von Neumann–Landauer bound. This may only be circumvented by the use of logically reversible computing, due to the second law of thermodynamics.[9]

Logical reversibility

[edit]

For a computational operation to be logically reversible means that the output (or final state) of the operation can be computed from the input (or initial state), and vice versa. Reversible functions must be injective. This means that reversible gates (and circuits, i.e. compositions of multiple gates) generally have the same number of input bits as output bits (assuming that all input bits are consumed by the operation).

An inverter (NOT) gate is logically reversible because it can be undone. The NOT gate may however not be physically reversible, depending on its implementation.

The exclusive or (XOR) gate is irreversible because its two inputs cannot be unambiguously reconstructed from its single output, or alternatively, because information erasure is not reversible. However, a reversible version of the XOR gate—the controlled NOT gate (CNOT)—can be defined by preserving one of the inputs as a 2nd output. The three-input variant of the CNOT gate is called the Toffoli gate. It preserves two of its inputs a,b and replaces the third c by . With , this gives the AND function, and with this gives the NOT function. Because AND and NOT together is a functionally complete set, the Toffoli gate is universal and can implement any Boolean function (if given enough initialized ancilla bits).

Surveys of reversible circuits, their construction and optimization, as well as recent research challenges, are available.[10][11][12][13][14]

Reversible Turing machines (RTMs)

[edit]

The reversible Turing machine (RTM) is a foundational model in reversible computing. An RTM is defined as a Turing machine whose transition function is invertible, ensuring that each machine configuration (state and tape content) has at most one predecessor configuration. This guarantees backward determinism, allowing the computation history to be traced uniquely.[15]

Formal definitions of RTMs have evolved over the last decades. While early definitions focused on invertible transition functions, more general formulations allow for bounded head movement and cell modification per step. This generalization ensures that the set of RTMs is closed under composition (executing RTM followed by executing RTM results in a new RTM) and inversion (the inverse of an RTM is also an RTM), forming a group structure for reversible computations. This contrasts with some classical TM definitions where composition might not yield a machine of the same class.[16] The dynamics of an RTM can be described by a global transition function that maps configurations based on a local rule.[17]

Yves Lecerf proposed a reversible Turing machine in a 1963 paper,[18] but apparently unaware of Landauer's principle, did not pursue the subject further, devoting most of the rest of his career to ethnolinguistics.

A landmark result by Charles H. Bennett in 1973 demonstrated that any standard Turing machine can be simulated by a reversible one.[19] Bennett's construction involves augmenting the TM with an auxiliary "history tape". The simulation proceeds in three stages:[20]

  1. Compute: The original TM's computation is simulated, and a record of every transition rule applied is written onto the history tape.
  2. Copy output: The final result on the work tape is copied to a separate, initially blank output tape. This copy operation itself must be done reversibly (e.g., using CNOT gates).
  3. Uncompute: The simulation runs in reverse, using the history tape to undo each step of the forward computation. This process erases the work tape and the history tape, returning them to their initial blank state, leaving only the original input (preserved on its tape) and the final output on the output tape.

This construction proves that RTMs are computationally equivalent to standard TMs in terms of the functions they can compute, establishing that reversibility does not limit computational power in this regard.[20] However, this standard simulation technique comes at a cost. The history tape can grow linearly with the computation time, leading to a potentially large space overhead, often expressed as where and are the space and time of the original computation.[19] Furthermore, history-based approaches face challenges with local compositionality; combining two independently reversibilized computations using this method is not straightforward. This indicates that while theoretically powerful, Bennett's original construction is not necessarily the most practical or efficient way to achieve reversible computation, motivating the search for methods that avoid accumulating large amounts of "garbage" history.[20]

RTMs compute precisely the set of injective (one-to-one) computable functions. They are not strictly universal in the classical sense because they cannot directly compute non-injective functions (which inherently lose information). However, they possess a form of universality termed "RTM-universality" and are capable of self-interpretation.[15]

Commercialization

[edit]

London-based Vaire Computing is prototyping a chip in 2025, for release in 2027.[21]

See also

[edit]

References

[edit]

Further reading

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Reversible computing

View on Grokipedia
from Grokipedia
Reversible computing is a of in which every logical operation is reversible, meaning that the transition function mapping states is bijective, allowing the entire process to be undone step-by-step without loss of or increase in . This approach ensures that no data is erased or merged during processing, contrasting with conventional irreversible computing where operations like logical AND or OR discard . In 1973, Charles H. Bennett demonstrated that any general-purpose , including those performed by irreversible , can be embedded into an equivalent reversible using techniques such as recording intermediate results on auxiliary storage and retracing steps backward to recover the initial state. The foundational principle underlying reversible computing is , which states that erasing one bit of information in a computational system inevitably dissipates at least kTln⁡2kT \ln 2 energy as heat, where kk is and TT is the temperature, setting a thermodynamic limit on energy efficiency in irreversible systems. By avoiding such erasures, reversible computing circumvents this limit, enabling operations that, in principle, require arbitrarily small energy per step as technology advances, potentially approaching zero dissipation through adiabatic processes where energy is recycled rather than lost. Key concepts include logical reversibility (bijective state transitions) and physical reversibility (thermodynamically efficient implementations, often using adiabatic circuits that slowly charge and discharge capacitors to minimize resistive losses). Bennett's 1988 historical notes further trace these ideas to early thermodynamic considerations by figures like Szilard and Landauer, emphasizing how reversibility aligns computation with the time-reversible laws of physics. Reversible computing offers significant benefits for energy efficiency, particularly in power-constrained environments, by enabling devices to perform more operations per joule—potentially orders of magnitude beyond current technology—thus extending battery life in portable electronics and reducing cooling needs in data centers. In supercomputing, it supports higher performance densities without thermal bottlenecks, while in embedded systems, it allows compact designs with sustained operation. Notable applications include adiabatic logic circuits for low-power VLSI, reversible extensions, and emerging hardware prototypes aimed at AI workloads, where reversible algorithms could slash use by running computations backward to reuse intermediate results. Recent advancements, as of 2025, highlight its potential to address AI's , with companies like Vaire Computing developing prototypes that demonstrate partial and research indicating possible up to 4,000-fold energy efficiency gains compared to conventional chips. Despite challenges in scaling hardware and adapting software paradigms, ongoing research at institutions like underscores reversible computing's scalability across future technologies, including cryogenic and superconducting systems.

Fundamentals

Overview and Definition

Reversible computing is a of in which every step is designed to be logically reversible, meaning the transition function of the is bijective—permuting the state space such that each output state uniquely determines a single input state, enabling the process to be executed either forward or backward without loss of . This bijectivity ensures that the entire computation can be undone by inverting the steps, preserving the mapping between initial and final configurations. At its core, reversible computing adheres to the principle of information preservation, avoiding operations that destroy data, such as the erasure of bits, which contrasts sharply with conventional computing models like the standard that rely on many-to-one transitions and thereby incur logical irreversibility. In irreversible systems, such destructive steps lead to an increase in thermodynamic as information is lost, but reversible approaches maintain full of states to sidestep this . A primary benefit of this is the potential for near-zero energy dissipation per computational operation under ideal conditions, as it circumvents the thermodynamic penalties associated with loss in traditional digital systems. The originated in the context of Landauer's 1961 exploration of the links between logical irreversibility and heat generation in processes, with Charles Bennett formalizing reversible methods in 1973 to enable efficient, low-dissipation . Its scope extends beyond classical implementations to include inherently reversible , where unitary operations ensure bijectivity, and adiabatic variants that emphasize gradual state changes for physical reversibility.

Historical Background

The concept of reversible computing emerged from foundational work in the physics of information processing during the mid-20th century. In 1961, at articulated the principle that the erasure of one bit of information in a computational process incurs a minimum thermodynamic cost of kBTln⁡2k_B T \ln 2 energy dissipation, where kBk_B is Boltzmann's constant and TT is the , linking logical irreversibility to physical . This insight highlighted the inefficiencies inherent in conventional irreversible models and laid the groundwork for exploring reversible alternatives to minimize dissipation. Building on , Charles Bennett extended the theoretical framework in 1973 by demonstrating that any , including operations, could be performed reversibly with only a constant-factor overhead in time and space, thereby avoiding erasure altogether. Bennett's proof showed that logical reversibility is compatible with universal , suggesting pathways for thermodynamically efficient machines. The 1980s saw significant advancements in models bridging logical and physical reversibility. In 1982, and Tommaso Toffoli introduced conservative logic, a framework for computation that preserves the number of 1s (or "tokens") across inputs and outputs, ensuring reversibility while reflecting physical conservation laws like and . Complementing this, and Toffoli proposed the billiard ball model in 1982, a mechanical system where computation arises from elastic collisions of identical spheres, demonstrating how reversible physical processes could implement universal logic gates without energy loss. During the 1990s and 2000s, reversible computing intersected with , amplifying its scope. David Deutsch's 1985 formulation of the provided a reversible inherently compatible with , where unitary operations ensure time-reversibility and opened avenues for quantum extensions of classical reversible paradigms. This period marked growing recognition of reversibility's role in quantum algorithms, though classical reversible models continued to evolve independently. The witnessed a resurgence of interest in reversible computing driven by escalating demands in data centers and mobile devices, prompting research into low-power architectures. Adiabatic circuit prototypes, which slowly charge and discharge capacitors to recycle and approach theoretical reversibility limits, emerged as practical implementations, with early demonstrations achieving up to 100-fold reductions compared to conventional designs in controlled settings. This revival was supported by the inauguration of the Reversible Computation (RC) conference series in 2009, which fostered a dedicated forum for advancements in theory, hardware, and applications.

Theoretical Foundations

Logical Reversibility

Logical reversibility in refers to the property of computational operations where the transition function mapping input states to output states is bijective, ensuring that every output corresponds uniquely to an input and allowing the computation to be inverted without loss of . This concept was formalized by Charles Bennett, who defined logical irreversibility in standard computing models like the as arising from transition functions that are not one-to-one, leading to the convergence of multiple states into a single output state. In contrast, reversible operations treat the state space as a where each logical step induces a , preserving the full of possible configurations and enabling deterministic recovery of prior states from subsequent ones. A key property of logically reversible computations is the strict one-to-one correspondence between inputs and outputs, which prevents information erasure at the logical level and maintains injectivity across the entire state space. This implies that the number of possible input states equals the number of possible output states, avoiding any compression or loss that would render inversion ambiguous. However, preserving reversibility imposes constraints on common circuit elements: , which duplicates a signal to multiple destinations, and , which merges signals from multiple sources, cannot be implemented directly without ancillary storage or reversible equivalents, as they would otherwise violate the bijective mapping by introducing non-injective behavior. Instead, such operations must employ techniques like temporary registers to track and restore states, ensuring the overall function remains a . Bennett's seminal theorem establishes the universality of reversible computing by proving that any irreversible computation can be simulated reversibly through a "history mechanism" that retains intermediate states throughout the process. Specifically, for any standard one-tape Turing machine, there exists an equivalent three-tape reversible Turing machine that computes the same function while keeping a complete record of prior configurations, allowing the entire computation to be undone by reversing the steps in order. This approach, known as Bennett's history method, demonstrates that reversibility does not limit expressiveness but merely requires additional space to store transient information, which can be uncomputed at the end to recover the original resources. Illustrative examples of logically reversible operations include the classical NOT gate, which inverts a single bit (0 to 1, 1 to 0) and is self-inverse, directly mapping its as a permutation of the two-state space. Another example is the controlled-NOT (CNOT) gate, operating on two bits where the target bit is flipped only if the control bit is 1, producing outputs (00→00, 01→01, 10→11, 11→10) that form a bijective mapping without information loss. These gates highlight how basic reversible primitives can compose to form more complex functions while adhering to the permutation requirement. In terms of , reversible circuits generally require more gates and ancillary bits than irreversible ones to embed non-bijective functions within a bijective framework, often incurring a linear overhead in size. Nevertheless, they retain the same asymptotic expressive power as classical irreversible circuits, as any deterministic can be embedded reversibly with resource increase, preserving . This equivalence underscores that logical reversibility expands the toolkit for without sacrificing universality.

Physical Reversibility

Physical reversibility in requires that the underlying physical dynamics of the be time-symmetric, meaning that the equations governing the of the system's state are invariant under time , allowing the to proceed forward or backward without loss of . This principle aligns with the fundamental laws of classical and , where microscopic processes are reversible in the absence of dissipation. To achieve this in practice, computational operations must employ adiabatic processes, which involve slow, gradual changes in control parameters to prevent abrupt state transitions that could introduce irreversibility through energy dissipation. In ideal reversible processes, entropy remains constant, making them isentropic, as no heat is generated or absorbed in a way that increases the disorder of the system. However, real physical systems deviate from this ideal due to dissipative mechanisms such as friction in mechanical components or decoherence in quantum-like setups, which lead to entropy production and information loss over time. These challenges necessitate careful engineering to minimize such effects, ensuring that the physical evolution mirrors the logical bijectivity required for computation. A seminal model illustrating physical reversibility is computer proposed by and Tommaso Toffoli in , which uses elastic collisions of perfectly rigid spheres in a frictionless environment to propagate signals and perform logic operations without dissipation or erasure. In this idealized setup, balls representing bits collide at right angles within a grid of deflectors, conserving both and , thereby demonstrating how conservative physical interactions can implement universal reversible . Despite these theoretical models, practical implementations face significant error sources, including thermal noise that randomizes particle or signal states and imprecise timing in control signals that disrupts collision accuracy or adiabatic switching. To mitigate these, robust error-correcting codes must be integrated into the physical architecture, allowing detection and reversal of deviations while preserving overall reversibility. Scaling reversible computing to nanoscale dimensions exacerbates these issues, as become dominant relative to signal energies, often requiring operation at cryogenic temperatures to suppress or in high-vacuum conditions to eliminate dissipative interactions like air resistance. These environmental controls are essential for maintaining the precision needed for reversible dynamics at small scales, though they pose additional hurdles for practical deployment.

Thermodynamic Implications

Reversible computing has profound thermodynamic implications, primarily through its ability to minimize energy dissipation in information processing, which is fundamentally limited by the second law of thermodynamics. Central to this is , which establishes that the erasure of one bit of information in an irreversible computation requires a minimum energy dissipation of kTln⁡2kT \ln 2, where kk is Boltzmann's constant and TT is the absolute temperature. This dissipation arises because irreversible operations increase the of the environment by an amount corresponding to the lost information, converting useful energy into heat. In contrast, reversible computing avoids this limit by preserving all throughout the , ensuring that every logical step is bijective and thus logically reversible. By not erasing bits, reversible operations can, in principle, approach zero thermodynamic dissipation in the limit of infinitely slow execution, as no net increase occurs in the system or its environment. This insight builds on the connection between and , exemplified by the Szilard , where measuring the position of a gas in a extracts work equivalent to kTln⁡2kT \ln 2 by reducing through acquired ; reversible similarly treat as negative , allowing energy to be recycled without loss. Despite these theoretical advantages, practical reversible systems face overheads from clocking signals, input/output interfaces, and finite-speed operations, which introduce some dissipation even without erasure. At (T≈300T \approx 300 K), the Landauer limit equates to approximately 3 zeptojoules (zJ) per bit, underscoring the minuscule yet fundamental scale of these costs. These bounds imply that reversible computing could push the ultimate limits of computational density and speed by enabling denser integration of logic elements without prohibitive generation, potentially sustaining exascale or beyond performance in thermodynamically constrained environments.

Computational Models

Reversible Turing Machines

A reversible is a variant of the standard model where the transition function is bijective, meaning it is both deterministic in the forward direction and invertible in the backward direction, ensuring that every configuration has a unique predecessor and successor. This logical reversibility prevents loss at each computational step, allowing the entire history to be reconstructed from any intermediate state. Charles Bennett introduced a seminal construction in 1973 for embedding an arbitrary irreversible Turing machine within a reversible one using a three-tape setup: a working tape for computation, a history tape to record the states and symbols discarded during forward steps, and an output tape to preserve the final result. The process unfolds in three phases—forward computation while logging history, copying the output to the third tape, and backward retracing using the history tape to restore the initial configuration without erasure—ensuring the overall mapping from input to output is reversible. This design maintains the simplicity of the Turing model while achieving injectivity through non-overlapping quadruples that specify tape operations without ambiguity. Reversibility introduces potential nondeterminism in step interpretation, as a given configuration might correspond to forward progress, backward reversal, or a stationary (halting) action, leading to up to three possible historical paths; however, unique decoding via the encoded history tape resolves this by specifying the exact prior state. The transition rules, defined as quadruples of the form AT1…Tn→A′T1′…Tn′A T_1 \dots T_n \rightarrow A' T_1' \dots T_n', ensure one-to-one mappings by partitioning the state space into disjoint domains and ranges. Reversible s are computationally universal, capable of simulating any standard while preserving reversibility, though with overhead: the three-tape version incurs linear time (approximately 4n4n steps for an nn-step computation) but quadratic space if compacted to a single tape due to head movements between work and history regions. Bennett proved that for any irreversible SS input II to output PP, the reversible RR transforms (I:\blank:\blank)(I : \blank : \blank) to (\blank:\blank:P)(\blank : \blank : P), demonstrating equivalence in expressive power. Variants include one-tape reversible Turing machines, which simulate the three-tape model but require O(n2)O(n^2) time due to tape shifting, and time-bounded reversible Turing machines that use extended seven-stage protocols for problems where the output uniquely determines the input, enabling efficient simulations with bounded runtime overhead.

Alternative Models

Alternative models of reversible computing extend beyond tape-based architectures to encompass physically inspired and spatially distributed paradigms that maintain logical reversibility through bijective mappings or conservative transformations. These models emphasize parallelism, locality, and physical realizability, often drawing from natural processes to demonstrate computation without information loss. While equivalent in expressive power to reversible Turing machines, they offer unique insights into scalable, energy-efficient systems. The model, proposed by Fredkin and Toffoli, exemplifies collision-based computing where bits are represented by the presence or absence of perfectly elastic spheres moving on a two-dimensional plane. Signals propagate through elastic collisions at predefined angles, ensuring that trajectories remain deterministic and reversible, as each collision conserves and position without . This model constructs universal gates, such as AND and OR, using switch-like structures that redirect balls without altering their count, thereby preserving the total state. It illustrates how macroscopic physical laws can underpin reversible logic, with computations unfolding ballistically over time. Building on similar principles, conservative logic networks, also from Fredkin and Toffoli, formalize as permutations of state vectors in a manner that avoids destructive interference. Operations are designed to map inputs bijectively to outputs, using gates like the , which swaps two bits conditionally based on a control bit without erasing information. This paradigm ensures that every computational step is invertible, with network depth and fan-out limited only by physical constraints, enabling the synthesis of arbitrary reversible functions through composition of primitives. Such networks underpin implementations and highlight the universality of conservative transformations in logic design. Reversible cellular automata (RCA) provide a spatial framework for reversible , where local update rules evolve a grid of cells bijectively across discrete time steps, allowing unique reconstruction of prior states from any configuration. These rules must be surjective and injective over the state space, often achieved through linear operations modulo 2 or block permutations. A canonical example is , an elementary one-dimensional automaton where each cell's next state is the exclusive-or of its two neighbors, generating the Sierpinski triangle pattern while remaining globally reversible under null boundary conditions with an even number of cells due to its additive structure over finite fields. RCAs support universal when combined with appropriate wiring, as shown in partitioned architectures that simulate Fredkin . In biochemical realms, DNA strand displacement enables reversible molecular through toehold-mediated hybridization and branch migration, where single-stranded DNA inputs trigger the release of outputs from double-stranded complexes. This is inherently reversible, as displaced strands can rebind under equilibrium conditions, allowing error correction and iterative operations without net destruction. Qian and Winfree demonstrated scalable logic circuits, including a half adder, using this mechanism, where gates like AND are cascaded via fuel strands to propagate signals reversibly at . Such models leverage DNA's parallelism for massive concurrency, with reaction rates tunable for computational fidelity. The Margolus neighborhood refines two-dimensional RCAs by partitioning the lattice into 2x2 blocks that update alternately in a checkerboard pattern, ensuring reversibility through local permutations within each block. Developed by Margolus, this approach simulates conservative physics-like dynamics, such as elastic collisions or , by rotating or reflecting block states bijectively. For instance, a simple rule might swap diagonally opposed cells if they differ, preserving particle counts and enabling the emulation of models on a discrete grid. This neighborhood facilitates efficient hardware mapping and has been used to model reversible simulations of gases and waves, underscoring RCA's role in physically motivated .

Implementations

Reversible Logic Gates and Circuits

Reversible logic gates are the fundamental building blocks of reversible digital circuits, designed to perform computations that are bijective, mapping each input uniquely to an output while preserving the number of inputs and outputs. Unlike traditional irreversible gates such as OR, which discard and thus violate reversibility, these gates ensure that the entire input state can be recovered from the output. The design of such gates draws from early theoretical work establishing that reversibility is possible at the logical level without loss of computational power. Universal reversible gates enable the construction of any reversible circuit, analogous to how NAND or NOR gates suffice for classical irreversible logic. The , also known as the controlled-controlled-NOT (CCNOT), is a three-bit gate that flips the target bit both control bits are 1, effectively implementing a reversible AND operation when an initialized to 0 is used as the target. Its is as follows:
Input (A, B, C)Output (A, B, C)
000000
001001
010010
011011
100100
101101
110111
111110
This gate, introduced in foundational work on reversible computing, is universal when combined with the NOT gate, allowing simulation of any classical reversible function. Similarly, the Fredkin gate, or controlled-SWAP, exchanges two target bits if the control bit is 1, preserving the number of 1s in the output and thus supporting conservative logic where information is neither created nor destroyed. Its operation can be described as outputting the control bit unchanged and swapping the other two inputs conditionally, making it universal for reversible circuits that maintain bit parity. Common gate libraries for reversible circuits include the controlled-NOT (CNOT) gate, which flips the target bit if the control is 1, serving as a two-bit reversible XOR that entangles qubits in quantum contexts while remaining fully reversible classically. The SWAP gate interchanges two bits without conditions, essential for rearranging data in reversible architectures and constructible from three CNOT gates. In quantum extensions, the Hadamard gate creates superpositions from basis states on a single , preserving reversibility as its own inverse and enabling hybrid classical-quantum reversible designs. These gates collectively form universal sets, such as {NOT, CNOT, Toffoli}, for synthesizing arbitrary reversible functions. Circuit synthesis in reversible computing involves embedding irreversible functions into reversible frameworks, often using methods like Bennett's bracketing technique, which structures computations by forward evaluation followed by backward uncomputation to restore ancillas and ensure bijectivity. This approach, originally formulated for Turing machines, minimizes space overhead by checkpointing intermediate states and reversing subcomputations, allowing irreversible algorithms to be simulated reversibly with quadratic time but linear space in the worst case. Optimization focuses on reducing gate count, circuit depth, and quantum cost, with heuristics exploring permutations of inputs and outputs to find minimal embeddings. Ancilla management is crucial for maintaining reversibility, as embedding non-bijective functions requires auxiliary bits (ancillas) initialized to known values, typically 0, to store temporary results without loss. These produce "garbage" outputs that must be cleaned by reversing the —reapplying gates in reverse order—to reset ancillas for reuse, a known as uncomputation that avoids permanent garbage accumulation. Effective balances ancilla count with circuit efficiency, as excessive ancillas increase hardware demands while poor cleaning leads to non-reversible artifacts. Electronic design automation (EDA) tools support reversible by automating synthesis, optimization, and verification. REVKIT, an open-source toolkit, provides algorithms for Toffoli-based synthesis, truth table embedding, and gate library optimization, enabling researchers to generate and benchmark circuits with minimal ancillas and low depth. It integrates methods for both classical reversible and construction, facilitating exploration of trade-offs in gate count and latency.

Hardware Technologies

Adiabatic logic represents a key hardware approach for implementing reversible computing by minimizing energy dissipation through charge recovery mechanisms. These circuits operate by slowly ramping up and down the voltage applied to logic gates, allowing the charge on capacitive nodes to be recycled rather than dissipated as heat during switching. This technique, rooted in the principles of thermodynamic reversibility, can theoretically reduce power consumption to arbitrarily low levels as switching speeds decrease. A prominent example is Efficient Charge Recovery Logic (ECRL), which uses dual-rail signaling to ensure reversible operation and high energy recovery through resonant clocking setups. Resonant adiabatic circuits, such as those employing LC resonators for energy oscillation, further enhance efficiency by providing flat-topped waveforms that maintain logic states without static power loss. Josephson junction technology enables low-dissipation reversible computing through superconducting circuits that operate at cryogenic temperatures, typically below 4 K. These junctions, formed by thin insulating barriers between superconductors, allow coherent tunneling of Cooper pairs with minimal energy loss, supporting ballistic signal propagation ideal for reversible gates. Adiabatic Quantum Flux Parametron (AQFP) logic, for instance, uses AC-biased Josephson junctions to achieve physically reversible operations, with energy dissipation approaching the Landauer's limit only during unavoidable error corrections. Experimental demonstrations have shown AQFP circuits performing reversible logic with power dissipation as low as ~7 pW per junction at clock frequencies up to 5 GHz, highlighting their potential for ultra-low-power applications. Capacitive shunting in these junctions further stabilizes dynamics, enabling near-ideal reversibility in asynchronous ballistic shift registers. Nanoscale approaches leverage quantum dots for reversible state transitions by confining electrons in nanostructures, enabling logic operations with minimal overhead. (QCA) architectures implement reversible gates through electrostatic interactions between dot cells, where electron positions encode binary states that can be propagated without voltage-based switching. This paradigm supports full reversibility since cell configurations are bijective, allowing backward to recover inputs. Recent designs have demonstrated QCA-based reversible arithmetic logic units (ALUs) with cell counts reduced by 16.37% and latency decreased by 41.17% compared to prior layouts, achieving efficiencies suitable for beyond-CMOS scaling. complements these efforts by exploring magnetic tunnel junctions for spin-based reversible switches, though practical implementations remain in early research stages focused on low-power rather than full logic reversibility. Field-programmable gate arrays (FPGAs) facilitate prototyping of reversible hardware by mapping reversible logic onto reconfigurable lookup tables and interconnects. This allows rapid iteration of reversible circuits without custom fabrication, using standard processes to emulate adiabatic or conservative logic behaviors. Implementations often employ Toffoli and Fredkin synthesized into FPGA fabric, with optimizations reducing gate count by 25-30% for complex functions like ALUs. For example, a 4-bit reversible ALU has been implemented on FPGAs, demonstrating feasibility with optimizations to reduce gate count and power. These modules serve as bridges to custom silicon, validating designs before scaling. In the 2020s, early prototypes have advanced toward pre-commercial reversible hardware, exemplified by Vaire Computing's designs featuring pipelined reversible pipelines with integrated . Their River test chip, fabricated in 22nm , demonstrates adiabatic resonators that recycle over 50% of switching energy via controlled charge , operating at multi-GHz speeds. These pipelines process in reversible stages, enabling forward and backward to minimize dissipation, with simulations projecting 10x energy efficiency gains for AI workloads. As of 2025, such prototypes remain experimental, focusing on validation of core mechanisms before full . As of November 2025, further prototypes in superconducting technologies continue to demonstrate scalability, with research focusing on integration for AI applications.

Software Approaches

Software approaches to reversible computing emphasize algorithmic techniques and programming paradigms that ensure computations can be undone without loss of , primarily through bijective mappings and avoidance of irreversible operations like destructive overwrites. These methods enable forward and backward execution on conventional hardware, facilitating applications such as and while minimizing auxiliary space usage. Key developments include specialized languages and tools that enforce reversibility at the software level, drawing from theoretical models like reversible Turing machines for implementation. Reversible programming languages provide structured ways to write code that inherently supports bidirectional execution. , a seminal imperative language, achieves reversibility by pairing forward and backward statements, such as monitoring persistent variables to track changes reversibly without garbage production. Similarly, RFun is a functional language where functions are defined inversely, allowing automatic generation of reversible programs through calls, as introduced by Yokoyama et al. in their foundational work on reversible functional paradigms. These languages restrict operations to injective functions, ensuring that every forward step has a unique inverse, which is verified through type systems or static analysis to prevent non-bijective constructs. Algorithm design in reversible software focuses on in-place reversibility to conserve and enable exact reversal. For sorting, reversible variants of algorithms like maintain auxiliary information, such as pivot selections or histories, to allow undoing partitions without extra storage proportional to input size; this approach achieves constant-factor overhead compared to irreversible counterparts. Avoiding destructive updates is central, with techniques like copying values before modification and pairing them with restoration steps, ensuring that data flows bijectively through the computation. Such designs reference reversible models briefly, simulating their tape operations in software to validate reversibility. Simulation tools emulate reversible computational models on standard machines, aiding and . Software emulators for reversible Turing machines (RTMs) implement the three-tape —input, computation, and output—using reversible transitions to mimic Bennett's universal RTM construction, often in compact codebases for tasks like incrementation or . Reversible debuggers extend this by enabling backward execution of programs, particularly in concurrent settings; for instance, tools for Erlang programs record causal dependencies to replay and reverse executions, isolating errors by stepping backward from failures while preserving . Optimization techniques in reversible software address space-time trade-offs through checkpointing and uncomputing. Checkpointing periodically saves computation states to allow and reversal, offering a practical alternative to full-history recording with tunable overhead based on frequency. Uncomputing reverses intermediate s to erase temporary , minimizing ancillary ; this is applied in reversible , such as algorithms that compute coefficients forward and uncompute residuals backward to recover inputs exactly, enabling iterative without accumulation of garbage. Verification ensures software reversibility by checking bijectivity, where functions map inputs uniquely to outputs and vice versa. Tools perform static on reversible languages like to detect non-injective operations, using flow-sensitive type checking to confirm that all updates preserve invertibility across program paths. These verifiers, often integrated into compilers, generate proofs of reversibility, supporting optimization passes that eliminate redundant checkpoints while maintaining bijectivity guarantees.

Applications and Impacts

Energy Efficiency and Sustainability

Reversible computing offers significant theoretical energy savings by circumventing the Landauer limit, which dictates a minimum energy dissipation of kTln⁡2kT \ln 2 (approximately 0.017 eV at ) per irreversible bit erasure. In reversible paradigms, computations preserve through bijective state transformations, avoiding such erasures and enabling reuse across operations without fundamental thermodynamic bounds. This approach theoretically allows for unbounded efficiency improvements as technology advances, with demonstrations in nanomechanical rod logic achieving energy per cycle around 4×10−264 \times 10^{-26} J at 100 MHz—74,000 times below the Landauer limit. In contexts, these principles suggest potential reductions in by orders of magnitude; for instance, reversible designs could yield up to 1,000-fold improvements over conventional irreversible systems, addressing projections of data centers exceeding 1 GW power draw by 2030. Such savings stem from minimizing dissipative losses, allowing sustained scaling without the exponential energy costs of traditional scaling. Practical implementations, particularly adiabatic reversible circuits, demonstrate measurable efficiency gains through energy recovery mechanisms. In adiabatic charging, signal energy is slowly ramped and recycled via resonant power clocks, dissipating only resistive losses rather than full capacitive energy. Simulations of Bennett-clocked ALUs show up to two orders of magnitude (100x) energy reduction at low frequencies (<3 MHz) compared to static baselines, dropping to one order (10x) at 50 MHz, with even greater relative savings at 20 nm nodes due to reduced leakage. These circuits approach near-complete recovery of switched energy when ramp times exceed RC time constants, outperforming irreversible by avoiding the full 12CVDD2\frac{1}{2} C V_{DD}^2 dissipation per switch. The sustainability impacts of extend to reduced thermal waste and operational demands in large-scale systems. By minimizing heat generation—approaching zero per operation as efficiency improves—reversible hardware lowers cooling requirements, which currently consume up to 40% of . This enables greener with vastly improved power-performance ratios, potentially orders of magnitude beyond non-reversible technologies, fostering environmentally viable scaling for . Case studies in illustrate these benefits in specialized applications. A reconfigurable reversible gate architecture for symmetric , implemented on Artix-7 FPGAs using Toffoli and Fredkin gates, achieves lower power draw than conventional designs: for 4-bit blocks, it consumes 81 mW versus 83 mW (a 2.4% reduction), scaling to 160 mW versus 175 mW for 16-bit blocks, while also reducing delay by 21%. This demonstrates reversible computing's ability to maintain functions with diminished overhead, preserving without erasure-induced losses. Broader ecological advantages include mitigating electronic waste from power-intensive hardware. Reversible computing's capacity for indefinite efficiency gains delays the need for frequent chip replacements driven by thermal and energetic bottlenecks, promoting longer device lifespans and reduced material throughput in computing infrastructure. By sustaining performance without escalating power demands, it supports principles in electronics, curbing the environmental footprint of obsolete high-power systems.

Role in Quantum and Adiabatic Computing

Reversible computing plays a foundational role in paradigms, as quantum operations are inherently reversible. All quantum gates correspond to unitary matrices, which are linear operators that preserve the norm of quantum states and are invertible, ensuring that quantum evolutions can be undone without loss of information. This unitarity implies that quantum computation avoids the information erasure inherent in irreversible classical operations, aligning directly with the principles of reversible computing where every computational step is bijective. Consequently, classical reversible models serve as a of quantum models, providing a bridge for simulating quantum behaviors using deterministic, invertible logic. A seminal contribution linking these paradigms is David Deutsch's 1985 model of the universal quantum computer, which extends Charles Bennett's 1973 framework of reversible s to the quantum domain. Deutsch demonstrated that a , operating via unitary transformations on quantum states, can simulate any reversible classical computation while enabling superpositions and interference for enhanced efficiency. Bennett's reversible construction, which embeds irreversible steps within reversible ones using temporary storage and uncomputation, directly informs this quantum extension by ensuring logical reversibility without thermodynamic dissipation. This model underscores how reversible computing underpins quantum universality, allowing quantum devices to perform arbitrary computations reversibly. In adiabatic quantum computing, reversibility is preserved through the slow, continuous evolution of the system's Hamiltonian, maintaining the within the subspace. This ensures that if the evolution is sufficiently gradual, the system avoids excitations and remains reversible, akin to unitary dynamics in gate-based models. The approach ties closely to , where reversible adiabatic processes solve optimization problems by gradually transitioning from an initial Hamiltonian to a problem-specific one, minimizing energy barriers without abrupt state changes. Hybrid approaches leverage reversible classical computing for preprocessing in , enhancing overall system reliability. By employing reversible operations to and decode quantum states, classical preprocessing can simulate fault-tolerant codes that ancillary qubits without introducing additional errors, as reversibility allows uncomputing garbage outputs. This integration reduces the complexity of quantum circuits by offloading invertible logical steps to classical hardware. Reversible designs offer key advantages in noisy intermediate-scale quantum (NISQ) devices by facilitating fault-tolerance through approximate reversible circuits that mitigate noise without excessive overhead. In NISQ environments, where error rates are high, these designs enable lower error accumulation compared to exact irreversible implementations, as demonstrated in simulations where approximate reversible gates outperform standard ones under decoherence. Such strategies ease the path to scalable by embedding reversibility to support error suppression in resource-constrained settings.

Emerging Uses in AI and Beyond

Reversible computing offers a promising solution to the escalating energy demands of , particularly in addressing the inefficiencies of during training. Traditional involves irreversible operations that erase intermediate , leading to significant as . By contrast, reversible models run computations backward—known as decomputation—to recover and this , potentially reducing by up to 4,000 times compared to conventional approaches. This dramatic efficiency gain stems from avoiding the thermodynamic costs of information erasure, as outlined in , and has been projected for AI workloads by researchers at . Reversible neural networks further exemplify these benefits, enabling efficient and through invertible architectures that preserve all computational states. Invertible transformers, for instance, allow exact reversal of forward passes without extra , making them suitable for resource-constrained AI deployments. Similarly, reversible recurrent neural networks (RNNs), including bidirectional variants, process sequential data in both directions while minimizing storage needs, as demonstrated in designs like the fully reversible bidirectional feature pyramid network. These structures draw from normalizing flows and residual couplings, ensuring bijective mappings that support both generative modeling and precise inversion. In 2025, advancements in reversible AI programs gained prominence, with discussions emphasizing their role in curbing computational waste to foster sustainable large language models. A Quanta Magazine feature detailed how backward-running algorithms, building on decades of theoretical work, could enable AI systems to operate with orders-of-magnitude lower energy use by uncomputing intermediate results. This approach aligns with broader efforts to scale AI without exacerbating global energy constraints, potentially integrating reversible logic into hardware for training massive models. Beyond AI, reversible computing enhances simulations in climate modeling by supporting invertible generative frameworks that efficiently handle probabilistic environmental dynamics. Reversible deep generative models, leveraging normalizing flows, allow for accurate forward simulations and backward inference of climate states, reducing the computational overhead of iterative predictions. In secure encryption, reversible logic gates enable low-power cryptographic circuits that maintain during reversible operations, as seen in designs for efficient in quantum-resistant schemes. The 17th International Conference on Reversible Computation (RC 2025), held in , , highlighted ongoing research into these applications, fostering discussions on integrating reversible paradigms with emerging computational fields like AI.

Challenges and Prospects

Technical Challenges

One major technical challenge in reversible computing is the significant overhead associated with implementing reversible circuits, particularly in terms of increased gate count and latency. To preserve reversibility, non-reversible functions must be embedded into larger reversible structures, often requiring additional ancilla bits to maintain bijectivity, which can expand the circuit size by factors of 2 to 4 compared to their irreversible counterparts. This ancilla management introduces extra latency, as computations must include forward passes followed by uncomputation steps to clear temporary states and avoid garbage accumulation, thereby slowing overall performance. Error propagation poses another critical obstacle, where even minor irreversibilities or in reversible operations can amplify dramatically over long computations. In strictly reversible systems, errors introduced at any propagate deterministically both forward and backward, potentially corrupting entire outputs unless robust correction mechanisms are employed, such as redundant encoding or fault-tolerant designs. This sensitivity necessitates advanced correction codes tailored for reversibility, which further increase computational overhead and complexity, as standard irreversible error-handling techniques are incompatible. Scalability remains hindered by the accumulation of garbage outputs in large-scale reversible circuits. As circuit depth grows, the need to track and uncompute garbage—unwanted side-effect bits generated during —leads to exponential increases in resource requirements, making it difficult to synthesize efficient circuits for complex functions beyond a few dozen bits. Optimization techniques, such as hierarchical synthesis or ancilla minimization, have been proposed to mitigate this, but they often trade off against gate count or depth, limiting practical for real-world applications. Testing and reversible systems are complicated by the bidirectional nature of execution, which allows backward but introduces unique verification challenges. Traditional forward-only testing methods fail to capture reversible-specific faults, such as those arising from improper uncomputation or state inconsistencies during , requiring specialized tools that simulate both directions and handle concurrent reversible threads. This bidirectional , while powerful for isolating errors, demands substantial computational resources and novel approaches to ensure circuit integrity. In the 2020s, integrating reversible components with existing irreversible infrastructure presents ongoing hurdles, as hybrid systems must manage interfaces that inevitably introduce dissipative losses without compromising overall reversibility. Current architectures, built on irreversible paradigms, resist seamless incorporation of reversible modules due to mismatched signaling and power delivery requirements, necessitating custom interconnects and protocol translations that add latency and cost. Efforts to address this include modular designs with reversible cores embedded in irreversible wrappers, but physical at these boundaries remains a persistent issue, amplifying small errors across the hybrid boundary.

Commercialization and Future Directions

Vaire Computing emerged as a leading player in the commercialization of reversible computing, unveiling its Ice River test chip prototype in 2025, which demonstrated energy recovery through an on-chip adiabatic resonator design. This prototype achieved an average of 50% energy recycling in its resonator component, marking a significant step toward practical implementation by minimizing heat dissipation in computations. The company, founded in the UK, focuses on silicon-based reversible chips tailored for AI workloads, with plans to release a specialized processor for AI inference by 2027. Theoretical projections suggest these chips could achieve up to 4,000 times the energy efficiency of conventional processors, addressing the escalating power demands of data centers. A IEEE Spectrum article highlighted how reversible logic is transitioning from academic labs to industry, driven by advancements in (EDA) tools specifically for reversible circuits. Vaire Computing is developing these tools alongside novel reversible architectures, enabling scalable synthesis and integration with existing processes. This shift is supported by key researchers like Michael Frank, who joined Vaire from in 2024 to accelerate hardware prototyping. Other contributors include teams at the and Zettaflops, focusing on adiabatic computing elements that recover energy during logic operations. Investments in reversible computing startups have targeted energy-efficient solutions for data centers, with Vaire securing $4.5 million in seed funding in 2024 to prototype near-zero energy chips. These funds support fabrication and testing aimed at reducing AI and costs in hyperscale environments. While specific partnerships remain nascent, industry analyses indicate growing interest from firms seeking sustainable alternatives to traditional GPUs, potentially leading to collaborations for custom AI accelerators. Industry roadmaps project reversible computing's integration into high-performance systems by 2030, with goals including exascale supercomputers that leverage for sustained operations without excessive cooling. Vaire's timeline envisions widespread adoption in edge AI devices, where low-power reversible processors could enable efficient on-device , reducing latency and battery drain in IoT applications. Long-term visions from emphasize reversible architectures as essential for scaling beyond current thermodynamic limits, potentially enabling modular upgrades in supercomputing clusters. The Reversible Computation (RC) conference series has evolved since its inception around 2009 as an annual forum, fostering collaboration among computer scientists, physicists, and engineers on practical implementations. The 2025 edition, held in , , emphasized hardware prototypes and software tools, building on prior events to address commercialization barriers. Regarding standards, IEEE initiatives like Rebooting Computing are exploring extensions to EDA frameworks for reversible hardware, with potential for formal standards to emerge as prototypes mature, ensuring interoperability in semiconductor design flows.

References

  1. https://mathweb.ucsd.edu/~sbuss/CourseWeb/Math268_2013W/Bennett_Reversibiity.pdf
  2. https://users.cs.duke.edu/~reif/courses/complectures/AltModelsComp/Bennett/LandauerPrinciple.pdf
  3. https://www.cise.ufl.edu/research/revcomp/overview.html
  4. https://www3.nd.edu/~lent/pdf/nd/FCN_ReversibleAndAdiabaticHanninenLentSniderBlair2014.pdf
  5. https://worrydream.com/refs/Bennett_1988_-_Notes_on_the_history_of_reversible_computation.pdf
  6. http://insti.physics.sunysb.edu/yitp/conf/simons-qcomputation/talks/frank.pdf
  7. https://spectrum.ieee.org/reversible-computing
  8. https://www.sandia.gov/app/uploads/sites/210/2022/06/UMass-talk-v6SAND.pdf
  9. https://worrydream.com/refs/Landauer_1961_-_Irreversibility_and_Heat_Generation_in_the_Computing_Process.pdf
  10. https://arxiv.org/pdf/1306.3760
  11. https://pubs.aip.org/aip/aed/article/1/3/030902/3364907/Industry-perspective-Limits-of-energy-efficiency
  12. https://www.nature.com/articles/s42254-021-00400-8
  13. https://link.springer.com/article/10.1007/BF01857727
  14. https://www.daviddeutsch.org.uk/wp-content/deutsch85.pdf
  15. https://www.sandia.gov/app/uploads/sites/210/2022/06/FrankConte-HotCarbon22-v4SAND.pdf
  16. https://reversible-computation.github.io/previous/
  17. https://cqi.inf.usi.ch/qic/80_Toffoli.pdf
  18. http://www.mathstat.dal.ca/~selinger/qpl2006/PDFS/05-Green-Altenkirch.pdf
  19. https://www.cs.princeton.edu/courses/archive/fall06/cos576/papers/bennett03.pdf
  20. https://web1.eng.famu.fsu.edu/~mpf/Frank-99-PhD.pdf
  21. https://www.sandia.gov/app/uploads/sites/210/2022/06/ECI22-talk-v7.pdf
  22. https://strangepaths.com/wp-content/uploads/2007/11/conservativelogic.pdf
  23. https://web1.eng.famu.fsu.edu/~mpf/p385-frank.pdf
  24. https://fab.cba.mit.edu/classes/863.18/notes/computation/Szilard-1929.pdf
  25. https://www.cs.princeton.edu/courses/archive/fall04/cos576/papers/bennett73.html
  26. https://publications.csail.mit.edu/lcs/pubs/pdf/MIT-LCS-TM-197.pdf
  27. https://dl.acm.org/doi/abs/10.1007/978-3-642-03745-0_29
  28. https://inmabb.criba.edu.ar/revuma/pdf/v56n1/v56n1a06.pdf
  29. https://users.cs.duke.edu/~reif/courses/complectures/AltModelsComp/Margolus/MargolusPhysicsLikeComp.pdf
  30. https://www.science.org/doi/10.1126/science.1200520
  31. https://web.eecs.umich.edu/~imarkov/pubs/misc/iwls02-revsyn.pdf
  32. https://web.eecs.umich.edu/~imarkov/pubs/jour/tcad03-iwls.pdf
  33. https://www.informatik.uni-bremen.de/revkit/10_rc_revkit.pdf
  34. https://www.osti.gov/servlets/purl/1459779
  35. https://www.nature.com/articles/srep06354
  36. https://pmc.ncbi.nlm.nih.gov/articles/PMC5428326/
  37. https://link.aps.org/doi/10.1103/PhysRevApplied.19.054034
  38. https://www.nature.com/articles/s41534-024-00849-2
  39. https://www.mdpi.com/2079-9292/11/23/4038
  40. https://www.researchgate.net/publication/395701514_Design_of_an_efficient_nanoscale_reversible_arithmetic_and_logic_unit_using_quantum_dots_for_energy-efficient_digital_signal_processing_devices
  41. https://www.ijert.org/research/fpga-implementation-alu-based-on-reversible-logic-IJERTV3IS10818.pdf
  42. https://ieeexplore.ieee.org/document/8389908
  43. https://www.eetimes.com/vaire-demos-energy-recovery-with-reversible-computing-test-chip/
  44. https://physicsworld.com/a/reversible-computing-could-help-solve-ais-looming-energy-crisis/
  45. https://dl.acm.org/doi/10.1145/1366230.1366239
  46. https://dl.acm.org/doi/10.1145/1244381.1244404
  47. https://link.springer.com/chapter/10.1007/978-3-642-29517-1_2
  48. https://cra.org/ccc/wp-content/uploads/sites/2/2020/11/Jayson-Lynch_ReversibleAlgorithmsTalk.pdf
  49. https://nextjournal.com/giggle/rtm50
  50. https://ieeexplore.ieee.org/document/9717362
  51. https://arxiv.org/pdf/2003.04617
  52. https://arxiv.org/pdf/2110.14717
  53. https://www.sandia.gov/app/uploads/sites/210/2022/06/ICRC18-talk-v3.pdf
  54. https://arxiv.org/pdf/1803.02789
  55. https://www.sandia.gov/app/uploads/sites/210/2022/06/CRNCH21-talk-1v0.pdf
  56. https://ijsred.com/volume8/issue5/IJSRED-V8I5P243.pdf
  57. https://royalsocietypublishing.org/doi/10.1098/rspa.1985.0070
  58. https://royalsocietypublishing.org/doi/10.1098/rspa.1996.0039
  59. https://link.springer.com/article/10.1023/A:1007720606911
  60. https://arxiv.org/abs/2302.01066
  61. https://www.sandia.gov/app/uploads/sites/210/2023/11/Comet23-slides_SAND.pdf
  62. https://arxiv.org/abs/2407.09093
  63. https://proceedings.mlsys.org/paper_files/paper/2023/file/c4f3fb058f957d5f753f9f9f0f08d991-Paper-mlsys2023.pdf
  64. https://proceedings.mlr.press/v97/behrmann19a/behrmann19a.pdf
  65. https://www.quantamagazine.org/how-can-ai-researchers-save-energy-by-going-backward-20250530/
  66. https://www.cs.cmu.edu/~epxing/Class/10708-19/assets/project/final-reports/project7.pdf
  67. https://www.researchgate.net/publication/390236352_Reversible_Logic-Based_Cryptography_Design_for_Secure_and_Efficient_Data_Processing
  68. https://reversible-computation-2025.github.io/
  69. https://arxiv.org/pdf/1605.05989
  70. https://www.sciencedirect.com/science/article/pii/S2590005622000285
  71. https://www.osti.gov/servlets/purl/1811970
  72. https://irp.fas.org/agency/dod/jason/reversible.pdf
  73. https://msoeken.github.io/papers/2016_dac_2.pdf
  74. https://link.springer.com/chapter/10.1007/978-3-030-47361-7_5
  75. https://msoeken.github.io/papers/2013_ismvl_2.pdf
  76. https://vaire.co/
  77. https://techcrunch.com/2024/07/01/vaire-computing-raises-4-5m-for-reversible-computing-moonshot-which-could-drastically-reduce-energy-needs/
  78. https://www.datacenterdynamics.com/en/analysis/vaire-computing-reversible-computing-semiconductor-chip/
  79. https://www.sandia.gov/app/uploads/sites/210/2022/06/Frank-SC21-panel-v4.pdf
Add your contribution
Related Hubs
Contribute something
User Avatar
No comments yet.