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Flat memory model
Flat memory model
Flat memory model
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Flat memory model or linear memory model refers to a memory addressing paradigm in which "memory appears to the program as a single contiguous address space."[1] The CPU can directly (and linearly) address all of the available memory locations without having to resort to any sort of bank switching, memory segmentation or paging schemes.

Memory management and address translation can still be implemented on top of a flat memory model in order to facilitate the operating system's functionality, resource protection, multitasking or to increase the memory capacity beyond the limits imposed by the processor's physical address space, but the key feature of a flat memory model is that the entire memory space is linear, sequential and contiguous.

In a simple controller, or in a single tasking embedded application, where memory management is not needed nor desirable, the flat memory model is the most appropriate, because it provides the simplest interface from the programmer's point of view, with direct access to all memory locations and minimum design complexity.

In a general purpose computer system, which requires multitasking, resource allocation, and protection, the flat memory system must be augmented by some memory management scheme, which is typically implemented through a combination of dedicated hardware (inside or outside the CPU) and software built into the operating system. The flat memory model (at the physical addressing level) still provides the greatest flexibility for implementing this type of memory management.

Memory models

[edit]
Further information: Memory address § Memory models

Most modern memory models fall into one of three categories:

Flat unpaged memory model

[edit]
  • Simple interface for programmers, clean design
  • Greatest flexibility due to uniform access speed (segmented memory page switches usually incur varied latency due to longer accesses of other pages, either due to extra CPU logic in changing page, or hardware requirements)
  • Minimum hardware and CPU real estate for simple controller applications[clarification needed]
  • Maximum execution speed, as there is no need to access auxiliary data structures such as a segment or page table in RAM
  • Not suitable for general computing or multitasking operating systems

Paged memory model

[edit]
Main article: Memory paging
  • Suitable for multitasking, general operating system design, resource protection and allocation
  • Suitable for virtual memory implementation
  • More CPU real estate, somewhat lower speed
  • More complex to program
  • Rigid page boundaries, not always the most memory efficient
  • This memory model is required when using Physical Address Extension (PAE) in Pentium Pro and later x86 CPUs to support 36-bit physical addresses to address more than 4GB of physical memory.

x86 segmented memory model

[edit]
Main articles: Memory segmentation and x86 memory models
  • Similar to paged memory, but paging is achieved by the implicit addition of two relatively shifted registers: segment:offset
  • Variable page boundaries, more efficient and flexible than the paged memory model
  • Quite complex and awkward from a programmer's point of view
  • More difficult for compilers
  • Pages can overlap / poor resource protection and isolation
  • Many to one address translation correspondence: Many segment:offset combinations resolve to the same physical address
  • Greater chance of programming errors
  • Implemented in the original Intel 8086, 8088, 80186, 80286, and supported by 80386 and all subsequent x86 machines through to present day Pentium and Core 2 processors. This memory model has remained ever since in the x86 machines, which now provide multi-mode operation and rarely operate in the compatible segmented mode.[clarification needed] See x86 memory segmentation for details.
  • saves RAM by moving the segment address, this allows short jumps that require fewer bytes.

Within the x86 architectures, when operating in the real mode (or emulation), physical address is computed as:[2]

Address = 16 × segment + offset

(I.e., the 16-bit segment register is shifted left by 4 bits and added to a 16-bit offset, resulting in a 20-bit address.)

See also

[edit]

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Flat memory model

View on Grokipedia
from Grokipedia
The flat memory model, also known as the linear memory model, is a memory addressing paradigm in where the program's available is presented to it as a single, contiguous, and uniformly addressable space, without divisions into separate segments or regions. In this model, addresses are generated directly as offsets within the entire space, typically byte-addressable and ranging from 0 to a maximum limit, such as 4 gigabytes (2^32 bytes) in 32-bit systems or up to 2^64 bytes in 64-bit extensions. This abstraction hides underlying hardware complexities like paging or caching from the programmer, allowing straightforward linear access to data and code. In the context of the x86 architecture, particularly the family introduced by in 1985, the flat memory model is implemented in by configuring segment descriptors in the (GDT) or Local Descriptor Table (LDT) with a base address of 0 and a limit covering the full linear , effectively making segmentation invisible to applications. A minimal setup requires at least one descriptor and one descriptor, both mapped to the entire 4 GB space, with segment registers (CS, DS, ES, SS) typically set to selectors referencing these descriptors. When combined with paging—enabled via the PG bit in the CR0 control register—this forms a protected flat model, where linear addresses are translated to physical addresses through page tables, providing isolation and protection against invalid accesses via exceptions. In e (64-bit) mode, segmentation is largely disabled for most registers (with bases fixed at 0), extending the flat model to a 64-bit linear while retaining support for FS and GS segments if needed. This model contrasts with segmented memory approaches, such as the real-address mode in early x86 systems, where memory is divided into variable-length segments addressed via base-offset pairs, limiting the addressable space to 1 MB and complicating programming. Adopted widely in modern operating systems like Windows (via Win32's 32-bit flat mode) and real-time environments like (using a flat 32-bit space with paging disabled), the flat model enhances efficiency by enabling direct 32-bit or 64-bit address manipulation in registers like EAX or RAX, reducing overhead in tasks such as stack operations, string processing, and access. Its design supports key features like canonical addressing in 64-bit mode to prevent exploits and integration with mechanisms such as Memory Type Range Registers (MTRRs) for cache control, making it foundational for and secure multitasking.

Definition and Basics

Core Concept

The flat memory model, also known as the linear memory model, is a memory addressing paradigm in which the program's available is presented as a single, contiguous linear address space of bytes, accessible through direct addresses that begin at zero. This approach presents to programs as an unbroken, sequential space, eliminating the need for division into separate regions or additional mapping mechanisms at the addressing level. In the flat memory model, programs reference memory locations using absolute addresses within the linear space, bypassing segmentation descriptors or registers that would otherwise translate or offset the , though virtual-to-physical via paging may still apply. This direct mapping simplifies address calculations, as the provided by the program corresponds straightforwardly to its position in the linear . For instance, the byte at N is located precisely at linear position N, without any base adjustments or bounds checking beyond the total addressable space. To illustrate address calculation in a flat memory model, consider the following pseudocode example for accessing a memory location:

function access_memory(logical_address, value): linear_address = logical_address // Direct mapping: no segmentation indirection if 0 ≤ linear_address < total_addressable_space: memory[linear_address] = value // May involve paging to physical else: raise out_of_bounds_error

function access_memory(logical_address, value): linear_address = logical_address // Direct mapping: no segmentation indirection if 0 ≤ linear_address < total_addressable_space: memory[linear_address] = value // May involve paging to physical else: raise out_of_bounds_error

This pseudocode demonstrates the simplicity of the model, where the linear address is identical to the logical one, assuming no segmentation. In contrast to segmented models, the flat approach avoids dividing memory into variable-sized segments, treating the entire space uniformly. This model is native to many RISC architectures, such as MIPS and ARM, where addressing is inherently linear without segmentation.

Key Characteristics

The flat memory model provides an uninterrupted linear address space extending from address 0 to the maximum limit supported by the processor architecture, typically up to 4 GB in 32-bit modes or vastly larger in 64-bit modes. This contiguous structure enables straightforward pointer arithmetic, where memory locations can be accessed and manipulated using simple offset calculations without segment base adjustments or boundary checks. A defining trait is the absence of hardware-enforced boundaries or relocation features inherent to segmented schemes, meaning code, data, and stack regions share the same without isolated segments. As a result, multitasking and rely on software-managed techniques, such as operating system-level paging, to prevent unauthorized access or overlaps. This model minimizes hardware overhead by avoiding segmentation mechanisms, such as segment registers, allowing direct linear addressing without base adjustments or descriptor fetches—and eliminating the need for page tables in non-paged configurations. Address translation thus requires fewer CPU cycles, as logical addresses map directly to linear addresses without multi-level indirection from segmentation. The flat memory model accommodates fixed-size addressing based on the architecture's bit width, including 16-bit variants for limited spaces, 32-bit for standard linear ranges up to 4 GB, and 64-bit for expansive virtual addressing.

Historical Development

Early Implementations

The flat memory model emerged in the mid-1970s with the advent of 8-bit microprocessors, which provided direct access to a contiguous 64 KB address space without segmentation or complex translation mechanisms. The , introduced in April 1974, exemplified this approach through its 16-bit address bus (A15-A0), enabling straightforward addressing of up to 65,536 bytes of for both program and in a unified space. This design simplified programming for resource-constrained systems, as developers could treat the entire addressable as a single linear array, supporting a mix of RAM and ROM without hardware-level partitioning. Building on the 8080's architecture, the , released in July 1976, maintained compatibility while enhancing the flat model with improved instruction sets and register capabilities, still within the same 64 KB flat address space defined by its 16-bit address bus. These processors powered early personal computers and embedded controllers, where the flat model's simplicity facilitated rapid development and low-cost hardware integration, such as in control systems for peripherals and basic computing tasks. In single-tasking environments, the flat memory model was particularly effective, as seen in the microcomputer introduced in 1975, which utilized the to directly map up to 64 KB of memory without operating system-mediated addressing. Similarly, the operating system, developed by starting in 1974 for the 8080, operated within this flat 64 KB space, allocating memory directly for transient program areas and system routines in a single-user, single-tasking setup that required no abstraction. This direct mapping allowed efficient execution of user programs loaded from disk, with the OS handling only basic file I/O and console operations atop the processor's native addressing. To overcome the 64 KB hardware limit in these 8-bit systems, simple bank-switching schemes were employed, where external hardware logic—often triggered via I/O ports or dedicated control lines—swapped portions of larger physical memory into the processor's flat address window. For instance, in Z80-based setups, bank selection could map additional 16 KB or 32 KB blocks into the upper address range, enabling effective expansion to 128 KB or more while preserving the illusion of a contiguous flat space for software. These techniques, common in embedded controllers and early PCs exceeding basic RAM needs, relied on minimal circuitry like latches and decoders to toggle banks dynamically during program execution. This foundational flat model in 8-bit systems paved the way for its adaptation in subsequent architectures, though with increasing complexity to handle larger address spaces.

Evolution in Processor Architectures

Following the flat model in 8-bit designs, 's x86 evolution began with the 8086 in 1978, which introduced 16-bit processing but employed segmented addressing in , providing access to up to 1 MB of through a 20-bit space formed by combining a 16-bit segment selector shifted left by 4 bits with a 16-bit offset. This scheme allowed flat-like access within segments by using consistent segment values, enabling linear addressing for small programs without full segmentation overhead, though the architecture remained inherently segmented. A significant advancement occurred with the Intel 80386 in 1985, transitioning to 32-bit architectures in , where the flat model was enabled by configuring segment descriptors in the (GDT) to span the entire 4 GB linear —using a base address of 0 and a limit of 4 GB. This setup eliminated the need for segment-relative addressing in application code, presenting memory as a single contiguous array accessible via 32-bit pointers ranging from 0 to 2^32 - 1; paging could be enabled separately via the PG bit in the CR0 register for translation if desired. The model persisted and expanded in 64-bit architectures, such as introduced in 2003, where enforces a flat memory model by largely ignoring legacy segmentation, supporting a theoretically up to 16 exabytes (2^64 bytes) while typically implementing 48-bit addressing for practical limits around 256 terabytes. In this setup, effective addresses serve as linear addresses without segment base additions, relying on paging for and protection. Parallel to x86 evolution, the flat model influenced RISC designs, notably the architecture developed from the mid-1980s by , which natively employs a single flat without segmentation, initially 32-bit covering 4 GB and later extended to 64-bit for larger scales, with an optional (MMU) for virtual addressing and virtualization support. This inherent flatness facilitated efficient embedded and mobile applications, contrasting segmented approaches while allowing MMU-based extensions for protected environments.

Comparison with Other Memory Models

Versus Segmented Memory

The segmented memory model divides the into discrete, variable-sized blocks known as segments, each accessed via a segment selector and an offset to form a . In the x86 architecture's , for instance, the effective address is calculated as the segment value multiplied by 16 plus the offset, enabling segments up to 64 KB in size but allowing overlaps and non-contiguous allocation that complicate . This approach, while providing flexibility for modular code organization, introduces significant complexity through the need for segment registers and potential relocation challenges when loading modules, as segments must be adjusted to avoid conflicts. In contrast, the flat memory model treats the entire space as a single, contiguous linear region, eliminating the use of segment registers for addressing by setting all segment bases to zero. This simplifies access to a direct linear equivalent to the offset alone, bypassing the multiplication and addition steps of segmented addressing. By avoiding descriptor lookups required in protected-mode segmentation—where the segment selector indexes into a descriptor table to retrieve the base before adding the offset—the flat model reduces overhead and prevents issues like segment overlaps that demand careful relocation during program loading. For example, in a segmented system under x86 , accessing data at segment 0x1000 and offset 0x2000 yields an effective of 0x1000×16+0x2000=0x1020000x1000 \times 16 + 0x2000 = 0x102000, involving hardware computation and potential overlap checks; in the flat model, the same access at offset 0x102000 uses direct addition within the linear space, streamlining computation without segment involvement. This elimination of segmentation hardware in flat models, such as in x86-64 , further avoids the burdens of managing variable-sized blocks and their associated descriptors.

Versus Paged Memory

The paged memory model divides the virtual address space into fixed-size units known as pages, typically 4 KB in size, which are mapped to physical memory frames using page tables that translate virtual (linear) addresses to physical addresses. This structure facilitates key operating system functions, including demand paging for loading pages only when needed, swapping inactive pages to disk to manage physical memory constraints, and per-page access controls that enforce protection mechanisms such as read/write permissions and user/supervisor isolation. In contrast, the flat memory model provides a single contiguous linear without segmentation, where logical addresses map directly to linear addresses. When paging is disabled, linear addresses map one-to-one with physical addresses, bypassing lookups and translation hardware for direct access. However, paging is fully compatible with and often combined with the flat model—enabled via the PG bit in the —to form a protected flat model, where linear addresses are translated to physical addresses via , providing , isolation, and . In IA-32e (64-bit) mode, paging is mandatory, extending the flat model to support a large with hardware-enforced page-level protections. A primary distinction in non-paged configurations lies in memory protection and isolation: paging provides built-in hardware support for fine-grained protection at the page level, preventing unauthorized access between processes and enabling efficient multitasking through isolated virtual address spaces. Without paging enabled, the flat model offers direct access to physical memory without inherent virtual isolation boundaries, simplifying addressing but requiring alternative mechanisms (e.g., software checks) for safeguards—though this is uncommon in modern systems, which enable paging for robustness. This setup means memory operations in a non-paged flat model occur in a single contiguous space, potentially exposing risks like buffer overflows without page-level barriers, but the combination with paging mitigates these via translation and protection flags. In terms of multitasking trade-offs, paging supports non-contiguous allocation by allowing pages to be scattered across physical while appearing contiguous to processes, enabling efficient sharing of pages between tasks and to handle memory pressure. The flat model without paging demands contiguous physical allocation for code, data, and stacks, which can lead to external fragmentation challenges in multi-process environments where large blocks become unavailable despite sufficient total free . Modern systems routinely combine the flat model with paging to leverage the simplicity of linear addressing alongside the robustness of management.

Implementation Details

In x86 Architecture

Introduced with the Intel 80386 processor, the protected mode flat configuration expands addressing to 32 bits while effectively disabling segmentation to achieve linear access across the full 4 GB (2^32 bytes) space. This is realized by configuring segment descriptors in the (GDT) with a base address of 0 and a limit of 0xFFFFFFFF (interpreted as 4 GB when the granularity bit G=1 enables 4 KB units), alongside access rights such as 0x92 for writable data segments or 0x9A for executable code segments. Paging is disabled by clearing the PG bit in CR0, mapping linear addresses directly to physical addresses without translation overhead, which simplifies the model to a single contiguous space. To switch to this flat model, software loads the GDT with identity-mapped entries (base=0, limit=0xFFFFF with flags 0xCF for granularity and appropriate access bytes), executes LGDT to load the GDT register, performs a far jump to reload the CS selector (e.g., 0x08 for code), and updates the remaining segment registers (DS, ES, FS, GS, SS) to the data selector (e.g., 0x10). In modern processors operating in (IA-32e mode), the flat addressing model is the default, building on with segmentation further minimized—segment bases for CS, DS, SS, ES, FS, and GS are ignored or set to zero, treating the as fully linear. Virtual addresses are 48 bits wide, sign-extended to 64 bits in , where bits 63:48 must replicate bit 47 (all 0s for positive or all 1s for negative addresses in the upper half); non-canonical forms raise a general-protection exception (#GP). This configuration uses four-level paging (PML4, PDPT, PD, PT) for translation to physical addresses up to 52 bits, but with segmentation disabled, effective addresses map directly, providing a seamless 256 TB (2^48 bytes) centered around zero. The following assembly code example illustrates a basic GDT setup and transition to protected mode flat model on an 80386+ processor (assuming real mode initially):

; GDT structure (24 bytes total) gdt_start: ; Null descriptor dd 0x0 dd 0x0 ; Code segment: base=0, limit=0xFFFFF, 32-bit, executable, ring 0 dw 0xFFFF ; Limit (bits 0-15) dw 0x0 ; Base (bits 0-15) db 0x0 ; Base (bits 16-23) db 10011010b ; Access byte: present, ring 0, code, executable, readable db 11001111b ; Flags: 32-bit, 4KB granularity; Limit (bits 16-19) db 0x0 ; Base (bits 24-31) ; Data segment: base=0, limit=0xFFFFF, 32-bit, writable, ring 0 dw 0xFFFF ; Limit (bits 0-15) dw 0x0 ; Base (bits 0-15) db 0x0 ; Base (bits 16-23) db 10010010b ; Access byte: present, ring 0, data, writable db 11001111b ; Flags: 32-bit, 4KB granularity; Limit (bits 16-19) db 0x0 ; Base (bits 24-31) gdt_end: ; GDT descriptor (6 bytes) gdt_descriptor: dw gdt_end - gdt_start - 1 ; GDT size dd gdt_start ; GDT address ; Switch to protected mode lgdt [gdt_descriptor] ; Load GDT mov eax, cr0 or eax, 1 ; Set PE bit mov cr0, eax jmp 0x08:protected_mode ; Far jump to code segment protected_mode: mov ax, 0x10 ; Data segment selector mov ds, ax mov es, ax mov fs, ax mov gs, ax mov ss, ax

; GDT structure (24 bytes total) gdt_start: ; Null descriptor dd 0x0 dd 0x0 ; Code segment: base=0, limit=0xFFFFF, 32-bit, executable, ring 0 dw 0xFFFF ; Limit (bits 0-15) dw 0x0 ; Base (bits 0-15) db 0x0 ; Base (bits 16-23) db 10011010b ; Access byte: present, ring 0, code, executable, readable db 11001111b ; Flags: 32-bit, 4KB granularity; Limit (bits 16-19) db 0x0 ; Base (bits 24-31) ; Data segment: base=0, limit=0xFFFFF, 32-bit, writable, ring 0 dw 0xFFFF ; Limit (bits 0-15) dw 0x0 ; Base (bits 0-15) db 0x0 ; Base (bits 16-23) db 10010010b ; Access byte: present, ring 0, data, writable db 11001111b ; Flags: 32-bit, 4KB granularity; Limit (bits 16-19) db 0x0 ; Base (bits 24-31) gdt_end: ; GDT descriptor (6 bytes) gdt_descriptor: dw gdt_end - gdt_start - 1 ; GDT size dd gdt_start ; GDT address ; Switch to protected mode lgdt [gdt_descriptor] ; Load GDT mov eax, cr0 or eax, 1 ; Set PE bit mov cr0, eax jmp 0x08:protected_mode ; Far jump to code segment protected_mode: mov ax, 0x10 ; Data segment selector mov ds, ax mov es, ax mov fs, ax mov gs, ax mov ss, ax

This setup creates identity-mapped segments covering the full 4 GB space, enabling flat linear addressing post-transition.

In Other Architectures

The ARM architecture natively employs a flat memory model, utilizing linear addressing within a single contiguous . In 32-bit ARM implementations, such as ARMv7-A, the instruction set addresses a flat space of 2^32 bytes, treated as unsigned byte addresses from 0 to 2^32 - 1, which can also be viewed as 2^30 32-bit words or 2^31 16-bit halfwords. For 64-bit in ARMv8, this extends to a 64-bit linear , supporting up to 2^64 bytes while maintaining the flat structure for . The (MMU) enables optional virtual-to-physical address translation and paging for protected environments, but in bare-metal configurations, the MMU can be disabled to provide direct access to a flat space, restricting applications to specified regions as needed. RISC-V architectures implement a flat virtual addressing scheme, where the appears as a single linear region to software. In supervisor mode, direct is achieved by setting the Supervisor Address Translation and Protection (SATP) register's MODE field to 0, which disables translation and enables bare mode for flat physical addressing without paging overhead. This configuration is common in embedded and real-time applications, allowing straightforward memory access across the full 32-bit or 64-bit depending on the variant, such as RV32 or RV64. In embedded systems based on MIPS and PowerPC processors, the flat memory model facilitates efficient operation without the complexity of segmentation or virtualization. MIPS architectures, including MIPS32 and MIPS64, support a flat 32-bit or 64-bit address space ranging from 0x00000000 to 0xFFFFFFFF (or larger for 64-bit), enabling byte-addressable access in a contiguous layout suitable for resource-constrained environments. Similarly, PowerPC cores utilize a flat model with paging disabled, providing a uniform view of memory from 0 to the processor's address limit, which simplifies porting and execution in systems lacking full MMU support. This model is particularly advantageous for real-time operating systems like FreeRTOS, which run on these architectures in bare-metal or minimal configurations, avoiding MMU-related overhead to ensure deterministic timing and low-latency task switching in embedded applications such as industrial controls and automotive systems. In the 2020s, flat memory models have gained prominence in IoT devices for enabling low-power, with minimal abstraction layers. The , powered by dual Xtensa LX6 32-bit RISC cores, exemplifies this trend by providing a flat, linear 32-bit for efficient code and data handling, integrated with low-power features like the Ultra-Low-Power (ULP) for without waking the main cores. This approach reduces in battery-operated IoT nodes, supporting direct flash and PSRAM access while maintaining compatibility with real-time kernels like for tasks such as wireless communication and edge processing.

Advantages and Limitations

Benefits

The flat memory model offers high performance by eliminating address translation latency, as physical addresses are used directly without the overhead of segmentation or paging mechanisms. In configurations without a (MMU), memory accesses occur with zero translation delay, making it particularly suitable for real-time and embedded applications where predictable timing is critical. This direct addressing avoids TLB misses and page faults that could introduce nondeterministic delays in paged systems, enabling faster context switches and more efficient execution in time-sensitive environments. Programming with the flat memory model is simplified through direct pointer usage, where addresses are linear and contiguous without requiring segment offsets or base calculations. Developers can manipulate pointers as simple offsets into a unified , reducing the complexity of low-level code and minimizing opportunities for bugs related to segment boundaries or far pointers. This approach aligns well with modern compilers optimized for 32-bit or 64-bit architectures, promoting portability across flat-model systems and easing the transition from 16-bit segmented environments. The model exhibits low resource usage due to its minimal descriptor requirements; for instance, in non-paged implementations, the absence of page tables avoids the memory overhead associated with maintaining structures, which can consume a noticeable portion of RAM in resource-constrained small systems. Segmentation descriptors are also reduced or neutralized, with segment registers often set to map the entire linear , further conserving system resources compared to segmented or paged alternatives. In single-address-space designs, the flat memory model provides excellent scalability by supporting large contiguous allocations up to the full limits of the architecture, such as 4 GB in 32-bit x86 or vastly larger in 64-bit modes. This unified view facilitates efficient handling of extensive data structures and arrays without fragmentation issues from segment limits, enabling applications to utilize the entire available as a seamless continuum.

Drawbacks

The flat memory model, while simplifying addressing, imposes limitations on memory protection granularity compared to segmented models. In architectures like x86, it typically employs a single large segment encompassing the entire , relying on paging for isolation and . This results in fixed 4 KB page sizes, causing internal fragmentation where partially used pages waste space—for instance, a small like a 1-byte occupies an entire page, leading to inefficient utilization. Additionally, paging can fragment logical data structures across multiple pages, increasing access overhead as the hardware must traverse page tables for each reference, potentially doubling the effort relative to contiguous segmented access. In and contexts, the flat model's treatment of all as a uniform, unrestricted space hinders advanced optimizations. By modeling pointers as simple integers capable of addressing any location, it overapproximates possible between memory regions, even when static analysis confirms no overlap. This constrains techniques like store forwarding or dead store elimination, which are essential for generating efficient code from high-level languages, thereby limiting performance gains in optimized binaries.

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