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Computer architecture
Computer architecture
Computer architecture
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Block diagram of a basic computer with uniprocessor CPU. Black lines indicate the flow of control signals, whereas red lines indicate the flow of processor instructions and data. Arrows indicate the direction of flow.

In computer science and computer engineering, a computer architecture is the structure of a computer system made from component parts.[1] It can sometimes be a high-level description that ignores details of the implementation.[2] At a more detailed level, the description may include the instruction set architecture design, microarchitecture design, logic design, and implementation.[3]

History

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The first documented computer architecture was in the correspondence between Charles Babbage and Ada Lovelace, describing the analytical engine. While building the computer Z1 in 1936, Konrad Zuse described in two patent applications for his future projects that machine instructions could be stored in the same storage used for data, i.e., the stored-program concept.[4][5] Two other early and important examples are:

The term "architecture" in computer literature can be traced to the work of Lyle R. Johnson and Frederick P. Brooks, Jr., members of the Machine Organization department in IBM's main research center in 1959. Johnson had the opportunity to write a proprietary research communication about the Stretch, an IBM-developed supercomputer for Los Alamos National Laboratory (at the time known as Los Alamos Scientific Laboratory). To describe the level of detail for discussing the luxuriously embellished computer, he noted that his description of formats, instruction types, hardware parameters, and speed enhancements were at the level of "system architecture", a term that seemed more useful than "machine organization".[8]

Subsequently, Brooks, a Stretch designer, opened Chapter 2 of a book called Planning a Computer System: Project Stretch by stating, "Computer architecture, like other architecture, is the art of determining the needs of the user of a structure and then designing to meet those needs as effectively as possible within economic and technological constraints."[9]

Brooks went on to help develop the IBM System/360 line of computers, in which "architecture" became a noun defining "what the user needs to know".[10] The System/360 line was succeeded by several compatible lines of computers, including the current IBM Z line. Later, computer users came to use the term in many less explicit ways.[11]

The earliest computer architectures were designed on paper and then directly built into the final hardware form.[12] Later, computer architecture prototypes were physically built in the form of a transistor–transistor logic (TTL) computer—such as the prototypes of the 6800 and the PA-RISC—tested, and tweaked, before committing to the final hardware form. As of the 1990s, new computer architectures are typically "built", tested, and tweaked—inside some other computer architecture in a computer architecture simulator; or inside a FPGA as a soft microprocessor; or both—before committing to the final hardware form.[13]

Subcategories

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The discipline of computer architecture has three main subcategories:[14]

There are other technologies in computer architecture. The following technologies are used in bigger companies like Intel, and were estimated in 2002[14] to count for 1% of all of computer architecture:

  • Macroarchitecture: architectural layers more abstract than microarchitecture
  • Assembly instruction set architecture: A smart assembler may convert an abstract assembly language common to a group of machines into slightly different machine language for different implementations.
  • Programmer-visible macroarchitecture: higher-level language tools such as compilers may define a consistent interface or contract to programmers using them, abstracting differences between underlying ISAs and microarchitectures. For example, the C, C++, or Java standards define different programmer-visible macroarchitectures.
  • Microcode: microcode is software that translates instructions to run on a chip. It acts like a wrapper around the hardware, presenting a preferred version of the hardware's instruction set interface. This instruction translation facility gives chip designers flexible options: E.g. 1. A new improved version of the chip can use microcode to present the exact same instruction set as the old chip version, so all software targeting that instruction set will run on the new chip without needing changes. E.g. 2. Microcode can present a variety of instruction sets for the same underlying chip, allowing it to run a wider variety of software.
  • Pin architecture: The hardware functions that a microprocessor should provide to a hardware platform, e.g., the x86 pins A20M, FERR/IGNNE or FLUSH. Also, messages that the processor should emit so that external caches can be invalidated (emptied). Pin architecture functions are more flexible than ISA functions because external hardware can adapt to new encodings, or change from a pin to a message. The term "architecture" fits, because the functions must be provided for compatible systems, even if the detailed method changes.

Roles

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Definition

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Computer architecture is concerned with balancing the performance, efficiency, cost, and reliability of a computer system. The case of instruction set architecture can be used to illustrate the balance of these competing factors. More complex instruction sets enable programmers to write more space efficient programs, since a single instruction can encode some higher-level abstraction (such as the x86 Loop instruction).[16] However, longer and more complex instructions take longer for the processor to decode and can be more costly to implement effectively. The increased complexity from a large instruction set also creates more room for unreliability when instructions interact in unexpected ways.

The implementation involves integrated circuit design, packaging, power, and cooling. Optimization of the design requires familiarity with topics from compilers and operating systems to logic design and packaging.[17]

Instruction set architecture

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Main article: Instruction set architecture

An instruction set architecture (ISA) is the interface between the computer's software and hardware and also can be viewed as the programmer's view of the machine. Computers do not understand high-level programming languages such as Java, C++, or most programming languages used. A processor only understands instructions encoded in some numerical fashion, usually as binary numbers. Software tools, such as compilers, translate those high level languages into instructions that the processor can understand.[18][19]

Besides instructions, the ISA defines items in the computer that are available to a program—e.g., data types, registers, addressing modes, and memory. Instructions locate these available items with register indexes (or names) and memory addressing modes.[20][21]

The ISA of a computer is usually described in a small instruction manual, which describes how the instructions are encoded. Also, it may define short (vaguely) mnemonic names for the instructions. The names can be recognized by a software development tool called an assembler. An assembler is a computer program that translates a human-readable form of the ISA into a computer-readable form. Disassemblers are also widely available, usually in debuggers and software programs to isolate and correct malfunctions in binary computer programs.[22]

ISAs vary in quality and completeness. A good ISA compromises between programmer convenience (how easy the code is to understand), size of the code (how much code is required to do a specific action), cost of the computer to interpret the instructions (more complexity means more hardware needed to decode and execute the instructions), and speed of the computer (with more complex decoding hardware comes longer decode time). Memory organization defines how instructions interact with the memory, and how memory interacts with itself.

During design emulation, emulators can run programs written in a proposed instruction set. Modern emulators can measure size, cost, and speed to determine whether a particular ISA is meeting its goals.

Computer organization

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Main article: Microarchitecture

Computer organization helps optimize performance-based products. For example, software engineers need to know the processing power of processors. They may need to optimize software in order to gain the most performance for the lowest price. This can require quite a detailed analysis of the computer's organization. For example, in an SD card, the designers might need to arrange the card so that the most data can be processed in the fastest possible way.

Computer organization also helps plan the selection of a processor for a particular project. Multimedia projects may need very rapid data access, while virtual machines may need fast interrupts. Sometimes certain tasks need additional components as well. For example, a computer capable of running a virtual machine needs virtual memory hardware so that the memory of different virtual computers can be kept separated. Computer organization and features also affect power consumption and processor cost.

Implementation

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Once an instruction set and microarchitecture have been designed, a practical machine must be developed. This design process is called the implementation. Implementation is usually not considered architectural design, but rather hardware design engineering. Implementation can be further broken down into several steps:

  • Logic implementation designs the circuits required at a logic-gate level.
  • Circuit implementation does transistor-level designs of basic elements (e.g., gates, multiplexers, latches) as well as of some larger blocks (ALUs, caches etc.) that may be implemented at the logic-gate level, or even at the physical level if the design calls for it.
  • Physical implementation draws physical circuits. The different circuit components are placed in a chip floor plan or on a board and the wires connecting them are created.
  • Design validation tests the computer as a whole to see if it works in all situations and all timings. Once the design validation process starts, the design at the logic level are tested using logic emulators. However, this is usually too slow to run a realistic test. So, after making corrections based on the first test, prototypes are constructed using Field-Programmable Gate-Arrays (FPGAs). Most hobby projects stop at this stage. The final step is to test prototype integrated circuits, which may require several redesigns.

For CPUs, the entire implementation process is organized differently and is often referred to as CPU design.

Design goals

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The exact form of a computer system depends on the constraints and goals. Computer architectures usually trade off standards, power versus performance, cost, memory capacity, latency (latency is the amount of time that it takes for information from one node to travel to the source) and throughput. Sometimes other considerations, such as features, size, weight, reliability, and expandability are also factors.

The most common scheme does an in-depth power analysis and figures out how to keep power consumption low while maintaining adequate performance.

Performance

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Modern computer performance is often described in instructions per cycle (IPC), which measures the efficiency of the architecture at any clock frequency; a faster IPC rate means the computer is faster. Older computers had IPC counts as low as 0.1 while modern processors easily reach nearly 1. Superscalar processors may reach three to five IPC by executing several instructions per clock cycle.[citation needed]

Counting machine-language instructions would be misleading because they can do varying amounts of work in different ISAs. The "instruction" in the standard measurements is not a count of the ISA's machine-language instructions, but a unit of measurement, usually based on the speed of the VAX computer architecture.

Many people used to measure a computer's speed by the clock rate (usually in MHz or GHz). This refers to the cycles per second of the main clock of the CPU. However, this metric is somewhat misleading, as a machine with a higher clock rate may not necessarily have greater performance. As a result, manufacturers have moved away from clock speed as a measure of performance.

Other factors influence speed, such as the mix of functional units, bus speeds, available memory, and the type and order of instructions in the programs.

There are two main types of speed: latency and throughput. Latency is the time between the start of a process and its completion. Throughput is the amount of work done per unit time. Interrupt latency is the guaranteed maximum response time of the system to an electronic event (like when the disk drive finishes moving some data).

Performance is affected by a very wide range of design choices — for example, pipelining a processor usually makes latency worse, but makes throughput better. Computers that control machinery usually need low interrupt latencies. These computers operate in a real-time environment and fail if an operation is not completed in a specified amount of time. For example, computer-controlled anti-lock brakes must begin braking within a predictable and limited time period after the brake pedal is sensed or else failure of the brake will occur.

Benchmarking takes all these factors into account by measuring the time a computer takes to run through a series of test programs. Although benchmarking shows strengths, it should not be how you choose a computer. Often the measured machines split on different measures. For example, one system might handle scientific applications quickly, while another might render video games more smoothly. Furthermore, designers may target and add special features to their products, through hardware or software, that permit a specific benchmark to execute quickly but do not offer similar advantages to general tasks.

Power efficiency

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Main articles: Low-power electronics and Performance per watt

Power efficiency is another important measurement in modern computers. Higher power efficiency can often be traded for lower speed or higher cost. The typical measurement when referring to power consumption in computer architecture is MIPS/W (millions of instructions per second per watt).

Modern circuits have less power required per transistor as the number of transistors per chip grows.[23] This is because each transistor that is put in a new chip requires its own power supply and requires new pathways to be built to power it.[clarification needed] However, the number of transistors per chip is starting to increase at a slower rate. Therefore, power efficiency is starting to become as important, if not more important than fitting more and more transistors into a single chip. Recent processor designs have shown this emphasis as they put more focus on power efficiency rather than cramming as many transistors into a single chip as possible.[24] In the world of embedded computers, power efficiency has long been an important goal next to throughput and latency.

Shifts in market demand

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Increases in clock frequency have grown more slowly over the past few years, compared to power reduction improvements. This has been driven by the end of Moore's Law and demand for longer battery life and reductions in size for mobile technology. This change in focus from higher clock rates to power consumption and miniaturization can be shown by the significant reductions in power consumption, as much as 50%, that were reported by Intel in their release of the Haswell microarchitecture; where they dropped their power consumption benchmark from 30–40 watts down to 10–20 watts.[25] Comparing this to the processing speed increase of 3 GHz to 4 GHz (2002 to 2006), it can be seen that the focus in research and development is shifting away from clock frequency and moving towards consuming less power and taking up less space.[26]

See also

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References

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Sources

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

Computer architecture

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Computer architecture refers to the conceptual structure and functional behavior of a computer system as perceived by the machine-language programmer, distinct from its physical implementation and internal data organization. This encompasses the attributes visible to software, such as the instruction set, addressing modes, and data types, which define how programs interact with the hardware. At its core, computer architecture bridges hardware design and software execution, focusing on optimizing performance, efficiency, and compatibility across diverse computing environments. The foundational model for most computer architectures is the , outlined in John von Neumann's 1945 report, which describes a where instructions and reside in a unified accessed sequentially by the (CPU). In this design, the CPU fetches instructions from , decodes them, and executes operations using components like the (ALU) for computations and registers for temporary . Key hardware elements include the —ranging from fast caches to slower but larger secondary storage—to balance speed and capacity; subsystems for peripheral interactions; and buses or interconnects for transfer between components. The (ISA) serves as the interface, specifying commands for movement, arithmetic, logic operations, and , while the underlying organization details how these are realized in hardware, such as through pipelining or parallel execution units. Historically, the formalization of computer architecture emerged with the in 1964, which introduced innovations like byte-addressable , a data format across models, and compatibility spanning a 50-fold performance range, enabling scalable designs without reprogramming. This shifted focus from ad-hoc hardware to standardized interfaces, influencing subsequent systems. Today, computer architecture evolves to address challenges like energy efficiency and massive parallelism, incorporating multi-core processors, specialized accelerators (e.g., GPUs for graphics and AI), and advanced technologies such as non-volatile RAM. Research emphasizes quantitative evaluation—using metrics like (CPI), throughput, and power consumption—to guide innovations in domains from embedded devices to supercomputers. These developments ensure architectures support emerging applications, including and , while maintaining with legacy software.

Overview

Definition and Scope

Computer architecture refers to the conceptual design and operational structure of a computer system, focusing on the attributes visible to the programmer, such as the instruction set, memory organization, and input/output interfaces. This discipline encompasses the science and art of selecting and interconnecting hardware components to create systems that meet functional, performance, and cost objectives, while ensuring compatibility between hardware and software at various abstraction levels. The scope of computer architecture centers on the hardware-software interface, defining how programs interact with the underlying hardware without delving into pure software design methodologies or the low-level physics of semiconductor components. It operates at multiple abstraction levels, from the high-level specification of system behavior to the organization that realizes these specifications, but excludes detailed circuit fabrication or operating system internals. This boundary ensures that architectural decisions prioritize programmer-visible functionality and system efficiency over physical engineering details. A key distinction exists between architecture, which comprises the high-level functional specifications as seen by the user or , and , which involves the physical realization through logical design, data flow organization, and hardware fabrication. This separation allows multiple implementations to conform to a single , enabling compatibility across diverse hardware while evolving independently. For instance, the x86 architectural family, originating from Intel's designs, specifies a complex instruction set (CISC) used in personal computers and servers, supporting over decades. Similarly, the ARM architectural family defines a (RISC) approach, emphasizing energy efficiency and for embedded systems, mobile devices, and servers.

Importance in Computing

Computer architecture fundamentally shapes the capabilities of systems by defining how hardware components interact to achieve desired levels, such as processing speed and energy efficiency. It determines through designs that support parallel processing and modular expansions, enabling systems to handle increasing workloads without proportional resource increases. Compatibility is ensured by standardizing interfaces like the (ISA), which allows software to run across diverse hardware implementations. The architecture profoundly influences by specifying how instructions are executed, resources are allocated, and data is managed, thereby guiding programmers in optimizing for specific hardware traits like pipelining and caching. This interaction allows developers to create more efficient applications that leverage architectural features, such as multi-core processing for concurrent tasks, reducing development time and costs. For instance, advancements in domain-specific architectures have accelerated software for by tailoring hardware to algorithmic needs, enabling high-level languages to achieve substantial performance gains. Applications of computer architecture span a wide range of devices and systems, from resource-constrained embedded systems in devices like automotive controllers and medical equipment, where real-time reliability is paramount, to high-throughput servers and supercomputers that process massive datasets for scientific simulations. In mobile devices, architectures balance power efficiency with computational demands to support ubiquitous connectivity and on-device AI. These designs ensure tailored across scales, from single-chip solutions in wearables to clustered processors in data centers. Economically, architectural innovations drive hardware market growth by enabling cost-effective scaling and new product categories, such as energy-efficient processors that extend device lifespans and reduce operational expenses in cloud infrastructure. Breakthroughs like open ISAs, such as , foster competition and lower barriers for startups, driving through faster innovation cycles and preventing stagnation in IT spending. Such advancements translate hardware improvements into broader economic value, supporting sectors like finance and healthcare with reliable, scalable computing.

Historical Development

Early Foundations

The foundations of modern computer architecture were laid in the 1940s through pioneering efforts to create programmable electronic digital computers. The Electronic Numerical Integrator and Computer (), completed in 1945 at the University of Pennsylvania's Moore School of Electrical Engineering, marked a significant milestone as the first general-purpose electronic digital computer, designed primarily for ballistic trajectory calculations by the U.S. Army Ordnance Department. Developed by and , ENIAC relied on physical reconfiguration via switches and patch cords for programming, which limited its flexibility but demonstrated the feasibility of high-speed electronic computation using vacuum tubes. joined the ENIAC project in 1944 as a consultant, and his exposure to its operations profoundly influenced subsequent designs, shifting focus toward more efficient programmability. Von Neumann's seminal 1945 report, "First Draft of a Report on the ," outlined the logical structure of the proposed Electronic Discrete Variable Automatic Computer (), introducing the stored-program concept that revolutionized computing by treating instructions and data as interchangeable numerical entities stored in a unified . This architecture, now known as the von Neumann model, comprised a central arithmetic unit for computations, a for sequencing operations, and a system enabling programs to be loaded, modified, and executed dynamically without hardware rewiring. The report emphasized binary representation for all data and instructions, establishing a foundational framework for digital systems. However, this access created an inherent limitation, later termed the von Neumann bottleneck, where the processor's single pathway to constrains performance by serializing fetches of instructions and data, a challenge rooted in the design's simplicity and scalability constraints. Building on these ideas, the , completed in 1949 by and his team at the , became the first operational to provide a regular computing service. EDSAC employed binary logic with 18-bit words (17 bits usable) and a single-address instruction format consisting of a 5-bit , 10-bit , and 1-bit length modifier for short (17-bit) or long (35-bit) operations, enabling efficient arithmetic and control tasks such as (A n: add contents of address n to accumulator) and (S n: subtract contents of address n from accumulator). Its memory used mercury delay lines for acoustic storage, initially offering 512 words of capacity, later expanded to 1,024 words, at speeds of roughly 500-600 . To address access speed disparities, early systems like and EDSAC incorporated rudimentary memory hierarchies, featuring fast immediate-access registers for active data, slower main memory (e.g., delay lines or electrostatic tubes), and auxiliary bulk storage like magnetic tapes, a concept von Neumann explicitly proposed to balance cost, capacity, and performance in resource-limited environments. These innovations from the 1940s to the 1960s established core principles that continue to underpin contemporary architectures.

Key Milestones and Evolutions

The 1970s marked a pivotal shift in computer architecture with the widespread adoption of pipelining and caching techniques, building on foundational designs from the prior decade. The , introduced in 1967, pioneered by overlapping fetch, decode, and execute stages to achieve higher throughput, particularly for scientific workloads requiring rapid floating-point operations. This approach influenced subsequent mainframe and designs throughout the 1970s, enabling processors to sustain instruction issue rates beyond single-cycle limits and setting the stage for performance scaling in commercial systems. Similarly, cache memory emerged as a key innovation to bridge the growing speed gap between processors and main memory; the Model 85, released in 1968, featured the first commercial integrated cache, a 16 KB buffer that reduced average memory access times by storing frequently used data closer to the CPU. By the mid-1970s, these hierarchies became standard in systems like the IBM 3033, dramatically improving effective and influencing the evolution toward hierarchical storage models still prevalent today. The 1980s witnessed the rise of Reduced Instruction Set Computing (RISC) architectures, challenging the dominance of Complex Instruction Set Computing (CISC) designs like Intel's x86. RISC emphasized a streamlined instruction set with fixed-length formats and load-store operations to simplify pipelining and increase clock speeds, as demonstrated in the Stanford MIPS project led by John Hennessy, whose 1982 design achieved high performance through a minimal set of 55 instructions optimized for VLSI implementation. Concurrently, the Berkeley RISC project under David Patterson produced the RISC I processor in 1982, featuring 31 instructions and a register-rich model that prioritized support for efficiency, directly inspiring commercial architectures like . In contrast, CISC architectures such as the and subsequent x86 evolutions retained variable-length instructions for and density, but RISC's simplicity enabled faster cycles and easier optimization, fueling the workstation boom with examples like MIPS R2000 (1985) and Sun (1987). This highlighted trade-offs in instruction complexity versus execution efficiency, with RISC gaining traction in embedded and . Entering the 1990s and 2000s, the end of and rising power walls drove the transition to multi-core processors, emphasizing parallelism over single-core clock speed increases. IBM's , unveiled in 2001, was the first commercial multi-core chip with two symmetric cores sharing a 1.41 MB L2 cache on a single die, with up to 32 MB off-chip L3 cache, enabling scalable (SMP) in servers and demonstrating up to 1.3 GHz per core with on-chip interconnects for low-latency communication. extended this to x86 with the line; while initial 2003 models were single-core, the dual-core 200 series in 2005 introduced links for multi-socket scalability, supporting up to four cores by 2006 and accelerating 64-bit adoption in data centers. followed with the in 2005, a dual-core design based on the architecture that packaged two Prescott cores at up to 3.6 GHz, targeting consumer desktops but revealing challenges like higher power draw that spurred the shift to Core microarchitecture. These developments established multi-core as the primary path for performance gains, with thread-level parallelism becoming essential for handling diverse workloads. In the 2010s and , heterogeneous computing integrated specialized accelerators like GPUs and AI units into unified system-on-chips (SoCs), optimizing for diverse computational demands beyond general-purpose CPUs. GPUs evolved from graphics rendering to parallel processing powerhouses, with NVIDIA's platform (2006 onward) enabling their use in AI training; by the 2010s, architectures like Fermi (2010), Volta (2017), and subsequent (2020) series delivered thousands of cores for matrix operations, achieving exaFLOP-scale performance in supercomputers like (using Volta GPUs). AI accelerators further specialized this trend, incorporating tensor cores and neural engines for inference. Apple's M-series chips exemplified this integration starting with the M1 in 2020, combining ARM-based CPU cores, a 7- or 8-core GPU, and a 16-core Neural on a unified that supports seamless task offloading, yielding up to 3.5x faster performance compared to prior Intel-based Macs. This heterogeneous model, seen also in AMD's Instinct GPUs and Google's TPUs, prioritizes workload-specific hardware for energy-efficient scaling in AI-driven applications. In the early , open-standard architectures like saw increased adoption in custom designs for data centers and edge devices, with implementations from companies like and Alibaba by 2025, while Apple's M-series advanced to the M4 chip in 2024, featuring enhanced efficiency for on-device AI processing.

Core Components

Instruction Set Architecture

The (ISA) defines the abstract interface between a computer's hardware and software, specifying the set of instructions that a processor can execute, along with the registers, types, and addressing modes available to programmers. It acts as a that ensures software compatibility across different implementations of the same ISA, allowing programs written in machine language to run correctly regardless of underlying hardware variations, as long as timing-independent behavior is preserved. This abstraction enables architects to evolve microarchitectures without altering the software ecosystem, though the ISA itself influences design choices like pipelining efficiency. Key components of an ISA include the opcode formats, which encode the operation to be performed; operand types, such as registers for fast data access, immediate values embedded in instructions, or memory locations for data storage; and control flow instructions like branches and jumps that alter execution sequence. The memory model specifies addressing schemes, including direct, indirect, and indexed modes, while data types range from integers and floats to vectors, determining how operands are interpreted and manipulated. Registers, typically a fixed set of general-purpose and special-purpose units, serve as the primary workspace for computations, with their number and size varying by ISA design. These elements collectively form the programmer-visible aspects of the processor, excluding implementation details like clock speed or cache hierarchy. ISAs are broadly classified into Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC), reflecting philosophical differences in instruction complexity and hardware-software balance. RISC architectures emphasize a small set of simple, fixed-length instructions—often 32 bits—with a load-store model that separates data movement (load/store) from computation (arithmetic/logic operations), promoting pipelining and optimization. In contrast, CISC designs feature a larger repertoire of variable-length instructions that can directly operate on memory operands, aiming to reduce size at the expense of decoding complexity. This dichotomy originated in the 1980s, with RISC gaining traction for its simplicity in , while CISC dominated legacy systems. and Patterson's seminal work on RISC highlighted how fewer, uniform instructions enable faster execution cycles compared to CISC's multifaceted opcodes. A prominent RISC example is the ARM ISA, which supports 32-bit fixed-length instructions in its base form and incorporates features like Thumb mode—a compressed 16-bit encoding of common instructions—to enhance code density by up to 30% in memory-constrained embedded systems, without sacrificing core functionality. allows seamless switching between 16-bit and 32-bit modes via dedicated instructions, optimizing for efficiency in mobile and IoT devices. Conversely, the x86 ISA exemplifies CISC evolution, starting as a 16-bit architecture in 1978 with variable-length instructions up to 6 bytes, then extending to 32 bits in 1985 and 64 bits in 2003 to support larger address spaces and multimedia via additions like SSE and AVX vector instructions. These extensions have layered RISC-like optimizations atop the original complex design, maintaining while adapting to modern workloads.

Microarchitecture and Organization

Microarchitecture refers to the internal hardware design that implements the (ISA), defining how instructions are executed through the coordination of elements and control logic. The consists of the functional units responsible for , including arithmetic logic units (ALUs) for integer operations and floating-point units (FPUs) for handling decimal calculations, which together form the execution units that perform computations specified by the ISA. The orchestrates these operations by generating control signals that direct data flow and activate specific execution units based on the fetched instruction. At the organization level, the employs finite state machines (FSMs) to manage sequential control, where each state corresponds to a phase of instruction execution, such as fetch, decode, execute, and write-back, with transitions triggered by control signals like clock pulses or condition flags. Control can be implemented via hardwired logic, which uses dedicated combinational circuits for fast, fixed signal generation, or microprogrammed approaches, where a sequence of microinstructions stored in control dynamically produces signals, offering greater flexibility for complex ISAs at the cost of added latency. Key structures include the register file, a high-speed array of storage locations for temporary data holding operands and results, typically with multiple read and write ports to support parallel access in superscalar designs. Buses serve as interconnects for transferring data between registers, execution units, and , with buses specifying locations, data buses carrying payloads, and control buses managing timing and direction. The (MMU) integrates into this organization by translating virtual es to physical ones, enforcing protection and enabling efficient access during instruction execution. A representative organizational distinction is between von Neumann and s: the von Neumann model uses a shared bus for both instructions and data, potentially creating bottlenecks during simultaneous fetches, while the employs separate paths for instructions and data, allowing concurrent access to improve throughput in data-intensive applications. In practice, many modern microarchitectures adopt a modified with separate level-1 (L1) instruction and data caches for concurrent access, while using unified higher-level caches and a shared to balance performance and simplicity.

Implementation Levels

Logic and Circuit Design

Logic and circuit design forms the foundational layer of computer architecture, translating high-level architectural concepts into physical electrical implementations using digital logic principles. At its core, Boolean algebra provides the mathematical framework for representing and manipulating binary signals in digital systems. Developed as a system of logic where variables take binary values (0 or 1), Boolean algebra uses operations such as AND (∧), OR (∨), and NOT (¬) to define logical expressions that correspond to circuit behaviors. These operations are realized through basic logic gates, which are the building blocks of all digital circuits: the AND gate outputs 1 only if all inputs are 1, the OR gate outputs 1 if any input is 1, and the NOT gate inverts the input value. Logic gates are combined to form two primary types of circuits: combinational and sequential. Combinational circuits produce outputs that depend solely on the current inputs, with no memory of previous states; examples include multiplexers and decoders, implemented using gates like , and XOR without feedback loops. In contrast, sequential circuits incorporate memory elements, allowing outputs to depend on both current inputs and prior states, enabling the storage and of data over time. This distinction is crucial for designing circuits that handle dynamic computations in processors. For state storage in sequential circuits, flip-flops serve as the fundamental memory units, capable of retaining a single bit of information stably until triggered. A basic SR (set-reset) flip-flop, constructed from cross-coupled NOR gates, can be extended to more robust types like (data) flip-flops, which capture the input value on the clock edge for reliable . Registers are arrays of flip-flops that store multi-bit words, such as 32-bit or 64-bit values, facilitating temporary holding during computations. Counters, built from interconnected flip-flops, increment or decrement a stored value in response to clock pulses, commonly used for sequencing operations or timing control; for instance, a ripple counter propagates carries sequentially through flip-flops, while synchronous counters update all bits simultaneously for faster operation. Arithmetic logic units (ALUs) exemplify the integration of for performing core operations like , , and logical functions on . An ALU typically comprises multiple sub-units, including and logic blocks, but its arithmetic core revolves around designs. The simplest adder is the ripple-carry adder (RCA), where each full adder stage generates a sum bit and propagates the carry to the next stage sequentially, resulting in a propagation delay that scales linearly with bit width (O(n) for n bits). To mitigate this delay, carry-lookahead adders (CLAs) precompute carry signals using generate (G) and propagate (P) terms across multiple bits, reducing the worst-case delay to O(log n) through parallel logic trees. These adder variants are selected based on trade-offs between area, power, and speed in ALU implementations. Clocking and synchronization ensure coordinated operation across circuits, particularly in sequential designs. Synchronous designs employ a global to trigger state changes at precise intervals, using flip-flops to sample inputs on rising or falling edges, which simplifies timing analysis but requires careful clock distribution to avoid skew. This approach dominates modern processors due to its predictability and compatibility with automated tools. Asynchronous designs, conversely, operate without a clock by using handshaking protocols (request-acknowledge signals) to synchronize transfer, offering advantages in power efficiency for variable workloads as circuits only activate when is present. However, asynchronous methods demand more complex avoidance and are less common in high-performance architectures. These logic and circuit elements collectively underpin microarchitectural structures like datapaths and control units.

System Integration and Fabrication

System integration in computer architecture encompasses the assembly of core components into functional systems, primarily through motherboard design that serves as the central platform for interconnecting the CPU, memory, storage, and peripherals. Motherboards facilitate electrical signal routing via traces and layers, ensuring reliable communication across the system while accommodating expansion slots and power distribution. Interconnects such as PCI Express (PCIe) provide high-speed, serial point-to-point links between the motherboard and peripherals like graphics cards and network adapters, enabling scalable bandwidth with data rates of 64 GT/s per lane in PCIe 6.0 configurations. I/O interfaces, including standards like USB and SATA, standardize data transfer to external devices, bridging the gap between internal system buses and diverse peripherals to support input/output operations efficiently. Semiconductor fabrication forms the foundation of by producing the integrated circuits that populate motherboards and chips. The dominant process is technology, which uses paired n-type and p-type transistors to achieve low power consumption and high in logic gates and cells. Key to scaling CMOS is , where (EUV) light patterns features on wafers; as of 2025, leading foundries like produce chips at 3 nm nodes using EUV for finer resolutions, with 2 nm processes expected to enter high-volume manufacturing by the end of 2025 to enable denser transistors. These fabrication steps, including wafer processing and doping, transform raw into functional dies ready for integration. Packaging techniques advance system integration by encapsulating and interconnecting multiple dies into compact modules, addressing limitations of monolithic designs. architectures, as exemplified by AMD's processors, divide complex systems into modular chiplets—such as compute cores and I/O dies—connected via high-speed Infinity Fabric links on a shared , allowing heterogeneous integration and easier scaling. Die stacking, often in 3D configurations, vertically layers components like cache memory over logic dies using through-silicon vias (TSVs) to boost density and reduce latency, as seen in AMD's 3D V-Cache implementation for cores. management in employs materials like thermal interface compounds and spreaders to dissipate from stacked or multi-chiplet structures, preventing thermal throttling and ensuring reliability under high workloads. Testing and verification ensure the integrity of integrated and fabricated systems before deployment, employing tools to model behavior and optimize production yields. Pre-silicon verification uses tools like VCS for logic and emulation, allowing designers to validate interconnects and I/O functionality against specifications without physical prototypes. In production, yield optimization relies on systems like Synopsys Yield Explorer, which analyzes test data to identify defects, correlate process variations, and refine fabrication parameters, achieving yield rates above 80% for advanced nodes through .

Design Objectives

Performance Metrics

Performance metrics in computer architecture quantify the effectiveness of designs in executing computational tasks, enabling comparisons across systems and guiding optimizations toward higher speed and efficiency. Key metrics include clock speed, which measures the frequency of processor cycles in gigahertz (GHz), determining how rapidly instructions can be processed; (IPC), the average number of instructions completed per clock cycle, reflecting the processor's ability to exploit ; and throughput, often expressed as millions of instructions per second (MIPS) for general-purpose computing or floating-point operations per second (FLOPS) for scientific workloads, providing an aggregate measure of computational output. These metrics are interrelated, as overall performance can be approximated by the product of clock speed and IPC, yielding MIPS as a derived indicator of system capability. A fundamental limit on performance gains, particularly in parallel architectures, is described by , which posits that the theoretical of a program is constrained by its sequential portions. Formulated by in 1967, the law states that even with infinite parallel resources, overall improvement diminishes if a significant remains serial. The SS is given by: S=1(1−P)+PSpS = \frac{1}{(1 - P) + \frac{P}{S_p}} where PP is the of the program that can be parallelized, and SpS_p is the achieved on the parallelizable portion. This formula underscores the need to minimize serial code to maximize benefits from parallelism. Standardized benchmarks facilitate objective evaluations of these metrics across architectures. The SPEC (Standard Performance Evaluation Corporation) suite, including SPEC CPU, assesses integer and floating-point using real-world applications, reporting scores normalized to a reference machine for comparability. Similarly, the TPC (Transaction Processing Performance Council) benchmarks, such as TPC-C for , measure throughput in transactions per minute while accounting for price-performance ratios, aiding assessments in database and enterprise environments. These tools ensure reproducible results under controlled conditions. Several architectural factors directly influence these metrics. Pipelining divides instruction execution into multiple stages (e.g., fetch, decode, execute), allowing overlapping operations to boost IPC, though deeper (more stages) increase latency from pipeline flushes. accuracy mitigates control hazards by speculatively executing likely paths; two-level adaptive predictors, which use global branch history, achieve accuracies around 97% on benchmark suites, reducing misprediction penalties that can stall for dozens of cycles. Cache hit rates, the proportion of requests satisfied from on-chip caches, minimize access delays to main ; high hit rates (e.g., 95% or better in L1 caches) sustain high throughput by keeping data close to the processor.

Power Efficiency and Constraints

Power efficiency in computer architecture refers to the optimization of energy consumption relative to computational output, a critical concern driven by thermal limits, battery constraints in mobile devices, and goals. Total power dissipation in digital circuits comprises dynamic and static components. Dynamic power arises from charging and discharging s during switching activities and is modeled by the equation Pdynamic=αCVdd2fP_{dynamic} = \alpha C V_{dd}^2 f, where α\alpha is the switching activity factor, CC is the load , VddV_{dd} is the supply voltage, and ff is the operating . This quadratic dependence on voltage makes it the dominant factor in active circuits. Static power, conversely, stems from leakage currents in s even when idle, primarily subthreshold leakage where current flows between source and drain below the , and gate leakage through the oxide layer. As sizes shrink under , static power has grown significantly, projected to constitute a major portion of total energy in high-performance microprocessors. Architects employ various techniques to mitigate these power components. Dynamic voltage and frequency scaling (DVFS) reduces dynamic power by lowering VddV_{dd} and ff during low-utilization phases, achieving up to 92% energy efficiency gains in benchmarks on modern processors by mapping performance monitoring unit events to optimal operating points. Clock gating disables clock signals to inactive logic blocks, preventing unnecessary toggling and reducing dynamic power by up to 40% in pipelined designs without substantial performance overhead. In mobile system-on-chips (SoCs), low-power modes such as isolate unused domains by inserting high-threshold sleep transistors to cut off leakage paths, a widely adopted method that balances with substantial static power savings in multi-domain processors. These strategies face inherent trade-offs, exacerbated by the breakdown of around 2005, which historically allowed uniform voltage reduction with transistor scaling to maintain power density. Post-breakdown, power density rises uncontrollably, leading to ""—regions of the chip that must remain powered off to avoid limits, restricting simultaneous activation of all transistors despite density gains. Power efficiency thus complements performance metrics, as aggressive scaling for speed often amplifies energy costs. Key evaluation metrics include , which quantifies throughput normalized by power draw to guide designs toward sustainable scaling, and the energy-delay product (EDP), defined as energy multiplied by execution delay, capturing the joint optimization of efficiency and latency in processor evaluations.

Parallel and Specialized Architectures

Parallel architectures enable concurrent execution of operations to achieve higher throughput, particularly for data-intensive applications, by classifying systems based on instruction and streams as per into SIMD and MIMD categories. SIMD systems execute one instruction across multiple points simultaneously, ideal for regular, data-parallel tasks like matrix operations. Vector processors, a classic SIMD implementation, use dedicated hardware to process arrays of data in a pipelined manner, as demonstrated by the , which featured 64-element vector registers and achieved peak performance of 160 megaflops through chained vector operations. MIMD architectures allow independent instructions on separate data streams, supporting irregular parallelism across diverse tasks. Multi-core processors represent a standard MIMD form, where each core operates autonomously with its own . Graphics processing units (GPUs), such as those using NVIDIA's platform, extend MIMD principles across thousands of lightweight cores, enabling massive thread-level parallelism for applications like while managing divergence through warp scheduling. Specialized architectures tailor hardware to domain-specific needs, optimizing for efficiency over generality. Application-specific instruction-set processors (ASIPs) incorporate custom instructions for targeted workloads, such as digital signal processors (DSPs) that accelerate signal manipulation in with specialized multiply-accumulate units. Neuromorphic chips mimic neural structures for AI tasks; IBM's TrueNorth, for instance, integrates 1 million neurons and 256 million synapses in a spiking network, consuming just 65 mW while supporting event-driven, asynchronous processing. Implementing parallelism introduces challenges, notably synchronization to coordinate threads and avoid race conditions, which can incur overhead from barriers or locks that serialize execution. quantifies speedup limits by highlighting that the serial fraction of a program constrains overall gains, even with ideal parallel scaling; for a workload with 5% serial time, maximum approaches 20x regardless of processor count. counters this by considering scaled problem sizes, asserting that efficiency improves with more processors as parallel portions dominate larger tasks, better suiting modern big-data scenarios. Practical examples include multi-socket servers, where AMD EPYC processors interconnect multiple sockets via Infinity Fabric to form MIMD systems with up to 192 cores per socket, facilitating scalable enterprise computing. FPGA-based reconfigurable architectures offer dynamic MIMD-like flexibility, allowing runtime customization of logic blocks for acceleration in cryptography or prototyping, bridging fixed and custom designs. Market demands for AI and cloud computing have accelerated adoption of these architectures for their ability to handle diverse, high-concurrency workloads.

Influences from Market and Technology Shifts

The evolution of computer architecture has been profoundly shaped by market demands, particularly the proliferation of mobile devices, which has elevated 's low-power architecture to dominance in that sector. By 2023, -based designs powered nearly every globally, driven by energy efficiency requirements that outpaced traditional x86 in battery-constrained environments. In parallel, the rise of has reinforced x86's role in scalable server environments, where hyperscalers like AWS and Azure rely on and processors for high-throughput workloads, though is increasingly adopted for cost-effective scaling in data centers. The has further accelerated integration of specialized accelerators, such as Google's TPUs and Nvidia GPUs, into architectures to handle matrix computations and training, with the global AI acceleration market projected to grow from $11.5 billion in 2024 to $72.17 billion by 2031 at a 30% CAGR. Technological advancements have also redirected architectural paradigms, as —predicting transistor density doubling every two years—begins to falter due to physical limits in scaling below 2nm nodes by 2025. This slowdown, attributed to challenges in and quantum tunneling effects, has prompted innovations like 3D chip stacking, which vertically integrates dies to exponentially increase transistor counts and bandwidth while mitigating the "memory wall" in multi-core systems. Additionally, the advent of poses existential threats to classical architectures by undermining cryptographic foundations; algorithms like Shor's on quantum hardware could decrypt RSA and ECC-based security in polynomial time, necessitating adaptations in for secure enclaves and hardware roots of trust. Economic factors exacerbate these shifts, with open-source instruction set architectures like challenging proprietary models such as and x86 by eliminating licensing fees and fostering customization, thereby reducing development costs for new chip designs. 's global adoption has surged, becoming the most prolific non-proprietary ISA, enabling diverse applications from IoT to servers without . Supply chain disruptions, highlighted by the 2020-2022 chip shortage, have compelled architects to prioritize resilient designs, incorporating diversified fabrication nodes and on-shoring to mitigate geopolitical risks in the Indo-Pacific-dominated semiconductor ecosystem. Looking ahead, emerges as a pivotal trend, processing data locally to reduce latency in IoT and networks, with 75% of enterprise data expected at the edge by 2025, influencing architectures toward heterogeneous integration of CPUs, GPUs, and NPUs. imperatives are driving eco-friendly designs, emphasizing low-power nodes and recyclable materials to curb the environmental footprint of data centers, which consume 1-1.5% of global , aligning architecture with carbon-neutral goals by 2030.

References

  1. https://dl.acm.org/doi/10.1147/rd.82.0087
  2. https://www.cs.umd.edu/~meesh/411/CA-online/chapter/computer-architectureintroduction/index.html
  3. https://textbooks.cs.ksu.edu/cc110/i-concepts/08-architecture/06-von-neumann/
  4. https://ece.ncsu.edu/research/cas/
  5. https://shop.elsevier.com/books/computer-architecture/hennessy/978-0-443-15406-5
  6. https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC272/S2005/Papers/IBM360-Amdahl_april64.pdf
  7. https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
  8. https://www.arm.com/architecture
  9. https://web.njit.edu/~sohna/cs650/why.html
  10. https://cacm.acm.org/research/a-new-golden-age-for-computer-architecture/
  11. https://riscv.org/
  12. https://iacoma.cs.uiuc.edu/iacoma-papers/ACAR2_REPORT.pdf
  13. https://plato.stanford.edu/entries/computing-history/
  14. http://web.mit.edu/sts.035/www/PDFs/edvac.pdf
  15. https://engineering.purdue.edu/~eigenman/reports/vN.pdf
  16. https://www.dcs.warwick.ac.uk/~edsac/Software/EdsacTG.pdf
  17. https://www2.seas.gwu.edu/~mlancast/cs211al/Appendices/appendix_l.pdf
  18. https://american.cs.ucdavis.edu/academic/readings/papers/ibm360-91.pdf
  19. https://people.engr.tamu.edu/djimenez/taco/utsa-www/cs5513-fall07/reader/smith-cache-memories.pdf
  20. https://www.ardent-tool.com/CPU/docs/AMD/anatomy/misc/articles/ajsmith.pdf
  21. https://www2.eecs.berkeley.edu/Pubs/TechRpts/1982/CSD-82-106.pdf
  22. https://public.dhe.ibm.com/software/mktsupport/techdocs/power4.pdf
  23. http://electro.fisica.unlp.edu.ar/arq/downloads/Papers/SMP/IEEE_Micro_2003_-_AMD_Opteron.pdf
  24. https://arxiv.org/pdf/2502.05317
  25. https://riscv.org/news/2024/10/risc-v-achieves-new-milestones-in-2024/
  26. https://queue.acm.org/detail.cfm?id=3639445
  27. https://www.arm.com/glossary/isa
  28. https://www.cise.ufl.edu/~mssz/CompOrg/CDA-lang.html
  29. https://dl.acm.org/doi/10.1145/2699682
  30. https://developer.arm.com/documentation/dui0068/b/arm-instruction-set-overview/thumb-instruction-set
  31. https://newsroom.intel.com/tech101/x86-architecture-foundation-of-modern-computing
  32. https://cseweb.ucsd.edu/classes/fa14/cse240A-a/pdf/04/Gonzalez_Processor_Microarchitecture_2010_Claypool.pdf
  33. https://users.ece.cmu.edu/~koopman/misc/byte87a.pdf
  34. https://academic.csuohio.edu/chu-pong/wp-content/uploads/sites/64/2023/02/rtl_chap10_fsm.pdf
  35. https://cs.wellesley.edu/~cs240/s21/lab/lab5/lab5overs.pdf
  36. http://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/1998.07.Virtual_memory_in_contemporary_microprocessors.pdf
  37. https://www.cse.wustl.edu/~lu/cse467s/slides/dsp.pdf
  38. https://ww2.coastal.edu/mmurphy2/oer/architecture/cpu/components/
  39. https://personal.utdallas.edu/~dodge/EE2310/lec4.pdf
  40. https://h3turing.vmhost.psu.edu/312ppts/Ch3SlidesNotes.pdf
  41. https://courses.cs.washington.edu/courses/cse369/16wi/lectures/01_Intro_Combinational-new.pdf
  42. https://www.cs.umd.edu/~meesh/411/CA-online/chapter/fixed-point-arithmetic-unit-i/index.html
  43. https://www.physics.wisc.edu/courses/home/spring2023/623/lecture_notes/digital/digital-02.html
  44. https://people.sabanciuniv.edu/erkays/cs303/ch06.pdf
  45. https://sites.pitt.edu/~juy9/142/slides/L4-ALU.pdf
  46. https://pages.hmc.edu/harris/class/e85/old/fall19/lect8.pdf
  47. https://www.hajim.rochester.edu/ece/sites/friedman/papers/Wiley_99_CDN.pdf
  48. https://people.ece.uw.edu/hauck/publications/AsynchArt.pdf
  49. https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf
  50. https://www.elepcb.com/blog/pci-and-pcie-in-pcb-layout-design/
  51. https://www.synopsys.com/glossary/what-is-pci-express.html
  52. https://dl.acm.org/doi/abs/10.5555/1074100.1074484
  53. https://irds.ieee.org/topics/new-semiconductor-technologies-and-applications
  54. https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm
  55. https://wccftech.com/tsmc-two-2nm-plants-sold-out-for-2026/
  56. https://www.amd.com/content/dam/amd/en/documents/solutions/technologies/chiplet-architecture-white-paper.pdf
  57. https://spectrum.ieee.org/amd-3d-stacking-intel-graphcore
  58. https://www.synopsys.com/
  59. https://semiengineering.com/knowledge_centers/manufacturing/yield-management-system-yms/
  60. https://dl.acm.org/doi/10.1145/1465482.1465560
  61. https://www.spec.org/
  62. https://www.tpc.org/
  63. https://dl.acm.org/doi/10.5555/996070.1009964
  64. https://dl.acm.org/doi/10.1109/MC.2003.1250885
  65. https://dl.acm.org/doi/10.5555/774861.774896
  66. https://dl.acm.org/doi/10.1145/3538645
  67. https://dl.acm.org/doi/10.5555/1899721.1899819
  68. https://dl.acm.org/doi/10.1145/2333660.2333680
  69. https://irds.ieee.org/images/files/pdf/2022/2022IRDS_BC.pdf
  70. https://dl.acm.org/doi/10.1145/2000064.2000108
  71. https://dl.acm.org/doi/10.1145/359327.359336
  72. https://www.amd.com/en/products/processors/server/epyc.html
  73. https://docs.nvidia.com/cuda/cuda-c-programming-guide/
  74. https://ieeexplore.ieee.org/document/5351271/
  75. https://research.ibm.com/publications/truenorth-design-and-tool-flow-of-a-65-mw-1-million-neuron-programmable-neurosynaptic-chip
  76. https://dl.acm.org/doi/10.1145/263699.263718
  77. https://www3.cs.stonybrook.edu/~rezaul/Spring-2019/CSE613/reading/Amdahl-1967.pdf
  78. https://www.doc.ic.ac.uk/~wl/papers/iee05tjt.pdf
  79. https://www.amd.com/en/solutions/data-center/insights/myths-and-urban-legends-about-dual-socket-servers.html
  80. https://www.cnbc.com/2023/11/09/how-arm-gained-chip-dominance-with-apple-nvidia-amazon-and-qualcomm.html
  81. https://semiengineering.com/data-center-cpu-dominance-is-shifting-to-amd-and-arm/
  82. https://www.industryarc.com/Research/AI-Acceleration-Market-801071
  83. https://www.splunk.com/en_us/blog/learn/moores-law.html
  84. https://news.mit.edu/2024/mit-engineers-grow-high-rise-3d-chips-1218
  85. https://www.sigarch.org/security-of-quantum-computer-architectures/
  86. https://www.csis.org/analysis/what-risc-v-means-future-chip-development
  87. https://riscv.org/blog/risc-v-impact-on-technology-and-innovation/
  88. https://www.csis.org/analysis/mapping-semiconductor-supply-chain-critical-role-indo-pacific-region
  89. https://www.otava.com/blog/2025-trends-in-edge-computing-security/
  90. https://www.mckinsey.com/capabilities/tech-and-ai/our-insights/the-top-trends-in-tech
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