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37°25′12″N 122°04′22″W / 37.4201°N 122.0728°W / 37.4201; -122.0728

MIPS Tech LLC,[1] formerly MIPS Computer Systems, Inc. and MIPS Technologies, Inc., is an American fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it.[2][3] MIPS provides processor architectures and cores for digital home, networking, embedded, Internet of things and mobile applications.[4][5]

Key Information

MIPS was founded in 1984 to commercialize the work being carried out at Stanford University on the MIPS architecture, a pioneering RISC design. The company generated intense interest in the late 1980s, seeing design wins with Digital Equipment Corporation (DEC) and Silicon Graphics (SGI), among others. By the early 1990s the market was crowded with new RISC designs and further design wins were limited. The company was purchased by SGI in 1992, by that time its only major customer, and won several new designs in the game console space. In 1998, SGI announced they would be transitioning off MIPS and spun off the company.

After several years operating as an independent design house, in 2013 the company was purchased by Imagination Technologies, best known for their PowerVR graphics processor family.[6] They were sold to Tallwood Venture Capital in 2017 and then purchased soon after by Wave Computing in 2018.[7] Wave declared bankruptcy in 2020, emerging in 2021 as MIPS and announcing that the MIPS architecture was being abandoned in favor of RISC-V designs.[8]

In May 2022, MIPS previewed its first RISC-V CPU IP cores, the eVocore P8700 and I8500 multiprocessors.[9] In December 2022, MIPS announced availability of the P8700.[10]

In July 2025, MIPS was acquired by GlobalFoundries.[11][12]

History

[edit]
Logo of MIPS Computer Systems
Logo of MIPS Computer Systems

MIPS Computer Systems Inc. was founded in 1984[13] by a group of researchers from Stanford University including John L. Hennessy and Chris Rowen. These researchers had worked on a project called MIPS (for Microprocessor without Interlocked Pipeline Stages), one of the projects that pioneered the RISC concept. Other principal founders were Skip Stritter, formerly a Motorola technologist, and John Moussouris, formerly of IBM.[14]

The initial CEO was Vaemond Crane, formerly President and CEO of Computer Consoles Inc., who arrived in February 1985 and departed in June 1989. He was replaced by Bob Miller, a former senior IBM and Data General executive. Miller ran the company through its IPO and subsequent sale to Silicon Graphics.

In 1986, MIPS Computer Systems designs were noticed by companies such as Cadnetix, Prime Computer and Silicon Graphics (SGI), these adopting the R2000 for new products, with SGI adopting the MIPS architecture for its computers having noted that the Motorola 68000 series of processors was "at the end of its price-performance curve".[15] Identifying the "time-to-market issues" of companies introducing workstation products, MIPS introduced a range of component kits, processor boards and memory boards, intended as "building blocks" for such companies to build into systems. Additionally, development systems such as the M/500 were sold, intended to support software development at systems vendors building MIPS-based hardware products.[16] In December 1989, MIPS held its first IPO. That year, Digital Equipment Corporation (DEC) released a Unix workstation based on the MIPS design.

After developing the R2000 and R3000 microprocessors, a management change brought along the larger dreams of being a computer vendor. The company found itself unable to compete in the computer market against much larger companies and was struggling to support the costs of developing both the chips and the systems (MIPS Magnum). To secure the supply of future generations of MIPS microprocessors (the 64-bit R4000), SGI acquired the company in 1992[17] for $333 million[18][19] and renamed it as MIPS Technologies Inc., a wholly owned subsidiary of SGI.[19]

MIPS RISC Certified Power emblem
MIPS RISC Certified Power emblem

During SGI's ownership of MIPS, the company introduced the R8000 in 1994 and the R10000[20] in 1996 and a follow-up the R12000 in 1997.[21] During this time, two future microprocessors code-named The Beast and Capitan were in development; these were cancelled after SGI decided to migrate to the Itanium architecture[22] in 1998.[18][23] As a result, MIPS was spun out as an intellectual property licensing company, offering licences to the MIPS architecture as well as microprocessor core designs.

On June 30, 1998, MIPS held an IPO after raising about $16.3 million with an offering price of $14 a share.[24][25][26] In 1999, SGI announced it would overhaul its operations; it planned to continue introducing new MIPS processors until 2002, but its server business would include Intel's processor architectures as well.[27] SGI spun MIPS out completely on June 20, 2000, by distributing all its interest as stock dividend to the stockholders.

In early 2008 MIPS laid off 28 employees from its processor business group. On August 13, 2008, MIPS announced a loss of $108.5 million for their fiscal fourth-quarter and that they would lay off another 15% of their workforce. At the time MIPS had 512 employees.[28] In May 2018, according to the company's presence on LinkedIn, there may be less than 50 employees.

Notable Contributors

[edit]

Notable people who have worked at MIPS include James Billmaier,[29] Steve Blank,[30] Joseph DiNucci,[31] John L. Hennessy,[32] Todd Bezenek,[33] David Hitz,[34] Earl Killian,[35][36] Dan Levin,[37] John Mashey,[38] John P. McCaskey, Bob Miller,[39] Stratton Sclavos,[40] and Skip Stritter.[41]

In 2010, Sandeep Vij was named CEO of MIPS Technologies.[42] Vij studied under John Hennessy as a Stanford University graduate student.[42] Prior to taking over at MIPS, Vij was an executive at Cavium Networks,[42] Xilinx and Altera.[43]

EE Times reported that MIPS had 150 employees as of November 1, 2010.[44] If the August 14, 2008 EDN article[28] was accurate about MIPS having over 500 employees at the time, then MIPS reduced their total workforce by 70% between 2008 and 2010.

MIPS branding as used by Imagination Technologies
MIPS branding as used by Imagination Technologies

In addition to its main R&D center in Sunnyvale, California,[45] MIPS has engineering facilities in Shanghai, China, Beaverton, Oregon, Bristol and Kings Langley, both in England.[46] It also has offices in Hsin-chu, Taiwan; Tokyo, Japan; Remscheid, Germany and Haifa, Israel.[47]

During the first quarter of 2013, 498 out of 580 of MIPS patents were sold to Bridge Crossing which was created by Allied Security Trust, with all processor-specific patents and the other parts of the company sold to Imagination Technologies.[48] Imagination had outbid Ceva Inc to buy MIPS with an offer of $100 million,[49] and was investing to develop the architecture for the embedded processor market.

In 2017, under financial pressure itself, Imagination Technologies sold the MIPS processor business to a California-based investment company, Tallwood Venture Capital.[50] Tallwood in turn sold the business to Wave Computing in 2018,[51] both of these companies reportedly having their origins with, or ownership links to, a co-founder of Chips and Technologies and S3 Graphics.[52] Despite the regulatory obstacles that had forced Imagination to divest itself of the MIPS business prior to its own acquisition by Canyon Bridge, bankruptcy proceedings for Wave Computing indicated that the company had in 2018 and 2019 transferred full licensing rights for the MIPS architecture for China, Hong Kong and Macau to CIP United, a Shanghai-based company.[53]

In 2021, MIPS announced it would begin making chips based on the RISC-V architecture.[54] In 2022, the company announced availability of its first RISC-V CPU IP core, the eVocore P8700.[10]

In September 2023, MIPS named former Texas Instruments (TI) executive Sameer Wasson CEO. Wasson spent 18 years at TI, most recently as vice president, Business Unit (BU) Manager, Processors.[55]

Company timeline

[edit]
Year
1981 Dr. John Hennessy at Stanford University founds and leads Stanford MIPS, a research program aimed at building a microprocessor using RISC principles.
1984 MIPS Computer Systems, Inc. co-founded by Dr. John Hennessy, Skip Stritter, and Dr. John Moussouris[56]
1986 First product ships: R2000 microprocessor, Unix workstation, and optimizing compilers
1988 R3000 microprocessor
1989 First IPO in November as MIPS Computer Systems with Bob Miller as CEO
1991 R4000 microprocessor
1992 SGI acquires MIPS Computer Systems. Transforms it into internal MIPS Group, and then incorporates and renames it to MIPS Technologies, Inc. (a wholly owned subsidiary of SGI)
1994 R8000 microprocessor
1994 Sony PlayStation released, using an R3000 CPU with custom GTE coprocessor
1996 R10000 microprocessor; Nintendo 64 released, incorporating a R4300i processor and coprocessor from MIPS
1998 Re-IPO as MIPS Technologies, Inc.
1999 Sony PlayStation 2 released, using an R5900 CPU with custom vector co-processors
2002 Acquires Algorithmics Ltd, a UK-based MIPS development hardware/software and consultancy company.
September 6, 2005 Acquires First Silicon Solutions (FS2), a Lake Oswego, Oregon company as a wholly owned subsidiary. FS2 specializes in silicon IP, design services and OCI (On-Chip Instrumentation) development tools for programming, testing, debug and trace of embedded systems in SoC, SOPC, FPGA, ASSP and ASIC devices.
2007 MIPS Technologies acquires Portugal-based mixed-signal intellectual property company Chipidea
February 2009 MIPS Joins Linux Foundation[57]
May 8, 2009 Chipidea is sold to Synopsys.
June 2009 Android is ported to MIPS[58]
September 30, 2009 MIPS Technologies joins the Open Handset Alliance[59]
January 2010 Sandeep Vij appointed as CEO[60]
January 2011 MIPS introduces the first Android-MIPS based Set top box at CES.[61]
April 2011 MIPS Technologies ports Google's Android 3.0, "Honeycomb", to the MIPS architecture[62][63]
August 2012 MIPS Technologies ports Google's Android 4.1, "Jelly Bean". With Indian company Karbonn Mobiles announces world's second tablet running Android 4.1.[64]
February 8, 2013 MIPS Technologies is sold to Imagination Technologies for $100 million.[65]
September 22, 2017 MIPS business is sold by Imagination Technologies to Tallwood Venture Capital as Tallwood MIPS Inc. for $65 million.[50]
June 2018 MIPS Tech Inc. is acquired by Wave Computing.[51]
May 2019 Art Swift is appointed CEO of Wave Computing.[66]
September 2019 After Swift quietly leaves Wave Computing after four months, Sanjai Kohli is appointed as the new CEO.[67]
April 2020 Wave Computing files for bankruptcy.[68]
March 2021 Wave Computing emerges from bankruptcy, renames itself as "MIPS" and joins RISC-V International. Development of the MIPS architecture ceases. All future designs are announced to be based on the RISC-V architecture.[69][70] Sanjai Kohli continues as MIPS CEO.[70]
May 2022 MIPS announced its first RISC-V CPU IP cores, the eVocore P8700 and I8500 multiprocessors.[9]
September 2023 Sameer Wasson is appointed MIPS CEO.[55]
January 2024 MIPS adds two former SiFive executives to its executive team, appointing Drew Barbier as VP of products and Brad Burgess as chief architect.[71]
July 2025 GlobalFoundries agrees to acquire MIPS[72]

Products

[edit]
Main article: List of MIPS architecture processors

MIPS Technologies created the processor architecture that is licensed to chip makers.[73][74] Before the acquisition, the company had 125+ licensees who ship more than 500 million MIPS-based processors each year.[75]

MIPS processor architectures and cores are used in home entertainment,[76] networking[77] and communications products. The company licensed its 32- and 64-bit architectures as well as 32-bit cores.[78]

The MIPS32 architecture is a high-performance 32-bit instruction set architecture (ISA) that is used in applications such as 32-bit microcontrollers, home entertainment, home networking devices and mobile designs.[79] MIPS customers license the architecture to develop their own processors or license off-the-shelf cores from MIPS that are based on the architecture.[80]

The MIPS64 architecture is a high performance 64-bit instruction set architecture that is widely used in networking infrastructure equipment through MIPS licensees such as Cavium Networks[81] and Broadcom.[82]

SmartCE (Connected Entertainment) is a reference platform that integrates Android, Adobe Flash platform for TV, Skype, the Home Jinni ConnecTV application and other applications.[83][84] SmartCE lets OEM customers create integrated products more quickly.

MIPS processor core families

[edit]

The MIPS processor cores are divided by Imagination into three major families:[85]

  • Warrior: hardware virtualization, hardware multi-threading, and SIMD[86]
  • Aptiv: microAptiv (compact, real-time embedded processor core), interAptiv (multiprocessor, multi-threaded core with a nine-stage pipeline), proAptiv (super-scalar, deeply out-of-order processor core with high CoreMark/MHz score)[92]
  • Classic. 4K, M14K,[79] 24K,[93] 34K,[94] 74K,[95] 1004K[96] (multicore and multithreaded) and 1074K (superscalar and multithreaded) families.

MIPS eVocore RISC-V CPU IP cores

[edit]

The MIPS eVocore CPUs are the first RISC-V CPU IP cores from MIPS. Both cores provide support for privileged hardware virtualization, user defined custom extensions, multi-threading, hybrid debug, and functional safety.[9] They include:

  • eVocore P8700: multiprocessing system combining a deep pipeline with multi-issue out-of-order (OOO) execution and multi-threading. It can scale up to 64 clusters, 512 cores and 1,024 harts/threads.[9]
  • eVocore I8500: in-order multiprocessing system. Each core combines multi-threading and a triple-issue pipeline.[9]

Licensees

[edit]

MIPS Technologies had a strong customer licensee base in home electronics and portable media players; for example, 75 percent of Blu-ray Disc players were running on MIPS Technologies processors.[97] In the digital home, the company's processors were predominantly found in digital TVs and set-top boxes.[83] The Sony PlayStation Portable used two processors based on the MIPS32 4K processor.

Within the networking segment, licensees include Cavium Networks and Broadcom.[77] Cavium has used up to 48 MIPS cores for its OCTEON family network reference designs.[98] Broadcom ships Linux-ready MIPS64-based XLP, XLR, and XLS multicore, multithreaded processors.[99] Licensees using MIPS to build smartphones and tablets include Actions Semiconductor and Ingenic Semiconductor.[100] Tablets based on MIPS include the Cruz tablets from Velocity Micro.[101] TCL Corporation is using MIPS processors for the development of smartphones.[102]

Companies can also obtain an MIPS architectural licence for designing their own CPU cores using the MIPS architecture. Distinct MIPS architecture implementations by licensees include Broadcom's BRCM 5000.

Other licensees include Broadcom, which has developed MIPS-based CPUs for over a decade,[103] Microchip Technology, which leverages MIPS processors for its 32-bit PIC32 microcontrollers,[104] Qualcomm Atheros, MediaTek and Mobileye, whose EyeQ chips are based on cores licensed from MIPS.[105]

The first announced licensee for MIPS' RISC-V CPUs is Mobileye, who adopted the MIPS eVocore P8700 for autonomous driving SoCs.[106]

Operating systems

[edit]

MIPS is widely supported by Unix-like systems, including Linux,[107] FreeBSD, NetBSD,[108] and OpenBSD.

Google's processor-agnostic[75] Android operating system is built on the Linux kernel.[109] MIPS originally ported Android to its architecture for embedded products beyond the mobile handset, where it was originally targeted by Google but MIPS support was dropped in 2018.[110] In 2010, MIPS and its licensee Sigma Designs announced the world's first Android set-top boxes.[61] By porting to Android, MIPS processors power smartphones and tablets running on the Android operating system.[111]

OpenWrt is an embedded operating system based on the Linux kernel. While it currently runs on a variety of processor architectures, it was originally developed for the Linksys WRT54G, which used a 32-bit MIPS processor from Broadcom. The OpenWrt Table of Hardware now includes MIPS-based devices from Atheros, Broadcom, Cavium, Lantiq, MediaTek, etc.[112]

Real-time operating systems that run on MIPS include CMX Systems, eCosCentric's eCos,[113] ENEA OSE,[114] Express Logic's ThreadX,[115] FreeRTOS, Green Hills Software's Integrity, LynuxWorks' LynxOS, Mentor Graphics, Micrium's Micro-Controller Operating Systems (μC/OS), QNX Software Systems' QNX, Quadros Systems Inc.'s RTXC Quadros RTOS, Segger's embOS and Wind River's VxWorks.

HPE NonStop Guardian OS has a version running on MIPS.

See also

[edit]

References

[edit]

Further reading

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

MIPS Technologies

View on Grokipedia
from Grokipedia
MIPS Technologies, Inc. is a fabless design company specializing in processor (IP) cores based on reduced instruction set computing (RISC) architectures, with a primary focus on enabling physical AI in autonomous platforms for automotive, industrial, and embedded markets. Founded in 1984, the company pioneered RISC innovations, introducing its first microprocessor, the R2000, in 1986, which powered landmark systems such as workstations, early game consoles, networking equipment, and automotive applications. Over its four-decade history, MIPS Technologies evolved from developing proprietary MIPS ISA cores to embracing the open-source standard in 2021, driven by the need for a modular, cost-effective ecosystem to support scalable, multi-threaded processors for high-performance edge computing. This transition followed a major restructuring in March 2021, when the company emerged from Wave Computing's Chapter 11 bankruptcy under new ownership by Tallwood Venture Capital, streamlining operations to prioritize RISC-based IP development. Key products include the MIPS Atlas portfolio, a suite of RISC-V compute subsystems optimized for safety-critical applications, featuring advanced multi-threading and compatibility with standards like for automotive functional safety. In July 2025, announced its acquisition of MIPS to bolster AI and processor IP capabilities, with the deal completing on August 14, 2025, allowing MIPS to operate as a standalone within the while expanding access to diverse process technologies and ecosystems. Today, under CEO Sanjai , MIPS continues to innovate in efficient, configurable cores for physical AI platforms, partnering with entities like International, Arteris, and to deliver solutions for industrial , intelligent power systems, and autonomous vehicles.

History

Founding and Early Development

MIPS Computer Systems, the predecessor to MIPS Technologies, was established in 1984 as a spinoff from Stanford University's MIPS research project, founded by along with John Moussouris and other researchers to commercialize the innovative (Reduced Instruction Set Computer) design known as MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages. The Stanford MIPS project, initiated in 1981 under Hennessy's leadership, aimed to develop a high-performance by simplifying the instruction set and leveraging advanced pipelining techniques, drawing from early RISC principles to achieve greater efficiency in VLSI implementation. This commercialization effort marked one of the first major transitions of academic RISC research into industry, positioning MIPS to challenge complex instruction set architectures dominant at the time. In 1985, MIPS Computer Systems unveiled its first commercial product, the R2000 microprocessor, a 32-bit that implemented the inaugural MIPS I (ISA) and emphasized a streamlined design for superior performance through reduced complexity. The R2000 featured a five-stage and operated at clock speeds up to 15 MHz, delivering around 6-8 million , which represented a significant advancement in processor efficiency for the era. Key technical hallmarks of the early MIPS ISA included a , where only dedicated load and store instructions accessed memory while arithmetic operations occurred exclusively on registers, and pipelining without hardware interlocks, requiring optimizations to resolve data dependencies and thereby minimizing hardware overhead. These features enabled faster execution cycles and easier scalability to future VLSI processes, establishing MIPS as a benchmark for clean, high-performance RISC designs. Early adoption of the was driven by partnerships with leading workstation manufacturers, notably Inc. (SGI), which integrated the R2000 into its Professional IRIS series workstations starting in 1988 to power graphics-intensive applications. SGI's use of MIPS processors in systems like the IRIS 4D/60 highlighted the architecture's suitability for demanding computational environments, contributing to its rapid uptake in professional graphics and engineering sectors. Additionally, the gained strong traction in and settings, facilitated by Hennessy's Stanford connections and the availability of educational tools, fostering widespread experimentation and refinement of RISC concepts through the mid-1990s.

Acquisitions and Ownership Changes

In 1992, Inc. (SGI) acquired MIPS Computer Systems for $406.1 million in cash and , integrating the processor designer into its operations to power SGI's line of high-performance workstations and servers. This move allowed SGI to control the development of MIPS-based RISC processors central to its graphics-intensive computing ecosystem, while eliminating redundancies in product lines and leveraging MIPS technology for broader market expansion. By the late 1990s, as SGI shifted strategic focus toward architectures amid competitive pressures, it pursued independence for its MIPS division through a planned spin-off. In April 1998, SGI announced the distribution of all 25 million shares of MIPS Technologies' Class B to its shareholders as a , effectively launching MIPS as a standalone valued at approximately $1 billion at the time. This separation enabled MIPS to operate more autonomously, targeting embedded systems and networking markets beyond SGI's workstation-centric needs, though early post-spin-off performance was volatile with shares dropping sharply on debut. Facing financial difficulties in the early , including declining revenues and mounting losses, MIPS Technologies restructured by selling 498 patents and related rights to Bridge Crossing LLC—a including —for $350 million in November 2012, providing critical liquidity while retaining 82 patents for ongoing operations. Shortly thereafter, in February 2013, acquired MIPS' operating business for $100 million in cash, valuing the IP portfolio at a fraction of its earlier patent windfall and shifting emphasis toward embedded and applications under Imagination's broader GPU and CPU strategy. The transaction included debt assumption and helped MIPS stabilize amid a competitive landscape dominated by architectures. In September 2017, amid Imagination's own sale process to Canyon Bridge Capital, the MIPS business was divested to Tallwood MIPS Inc.—backed by Tallwood Venture Capital—for $65 million in cash, marking a reduced valuation from the 2013 acquisition and allowing MIPS to refocus on core IP licensing for embedded markets. Tallwood's involvement emphasized long-term independence, with MIPS rebranding efforts highlighting its processor cores for IoT and networking sectors. MIPS was subsequently acquired by AI startup Wave Computing in June 2018 for undisclosed terms, aiming to integrate MIPS IP into Wave's dataflow architectures for machine learning applications, though Wave's aggressive expansion led to financial strain. By April 2020, Wave filed for Chapter 11 bankruptcy with over $100 million in debt, including obligations from prior funding rounds, prompting an asset auction that restructured the company and separated MIPS operations. In March 2021, Tallwood Venture Capital emerged victorious with a $61 million bid, assuming majority ownership of the reorganized MIPS entity and enabling debt forgiveness while preserving the IP portfolio for continued development.

Transition to RISC-V and Recent Shifts

In 2021, following its emergence from proceedings initiated in 2020, MIPS Technologies announced a strategic pivot away from further development of its proprietary MIPS instruction set architecture (ISA), citing the growing industry preference for open-standard alternatives amid challenges in licensing and market adoption. This shift aligned with broader trends favoring extensible, royalty-free architectures to foster innovation and reduce . The decision marked the end of active MIPS ISA evolution, redirecting resources toward the open-source ISA, which offered greater flexibility for customization in embedded systems. As part of this transition, MIPS introduced its eVocore lineup in 2022, comprising the first -based processor IP cores, including the high-performance P8700 out-of-order multiprocessor and the efficiency-focused I8500 in-order core. These cores became available starting in late 2022, with the P8700 multiprocessor IP launching commercially in January 2023, specifically engineered for embedded applications requiring scalable and low-latency . Targeted at sectors like networking, automotive, and early AI edge devices, the eVocore family emphasized compatibility with extensions for vector and custom instructions, enabling MIPS to re-enter competitive markets without the constraints of proprietary IP. By March 2025, MIPS further evolved its strategy, announcing plans to develop proprietary chip designs in parallel with its licensing model, with a primary emphasis on "physical AI" solutions for real-time decision-making in robotics and autonomous vehicles. This initiative included the launch of the Atlas portfolio of compute subsystems, integrating cores with AI accelerators to support event-driven computing at the edge. The move aimed to address demands for integrated hardware in dynamic environments, such as and , while maintaining openness through foundations. Later that year, on July 8, 2025, announced its acquisition of MIPS for an undisclosed sum, with the deal closing on August 14, positioning MIPS as a standalone unit to enhance ' IP offerings for AI-optimized semiconductor fabrication. This integration was intended to streamline design-to-manufacturing workflows, bolstering capabilities in custom silicon for edge AI applications.

Products and Technologies

MIPS Architecture Processor Cores

The MIPS architecture processor cores encompass several families developed primarily for general-purpose computing, workstations, and embedded applications, evolving from 32-bit designs in the to 64-bit implementations with advanced features by the . The R-series cores formed the foundation, starting with the R2000, a 32-bit announced in 1985 that introduced a load/store RISC design with multiple-cycle multiply and divide instructions to enhance performance in early commercial systems. This was followed by the R3000 in 1988, which improved clock speeds and integration while maintaining compatibility, targeting workstations and servers from vendors like and . The family marked a significant advancement in 1991, introducing the first 64-bit MIPS implementation with superscalar execution, allowing multiple instructions to be processed per cycle for improved throughput. Fabricated in a 1.0 μm process with 1.35 million transistors, the featured on-chip instruction and data caches, branch prediction, and full compatibility with prior R-series binaries, enabling its use in environments. Subsequent variants like the R4400, released in 1993, doubled on-chip cache sizes to 16 KB each for instruction and data, achieving clock speeds up to 250 MHz and delivering approximately 117 SPECint92 performance at 200 MHz, scaling to higher real-world application throughput in multiprocessor configurations. Shifting focus to embedded systems in the , the M-series cores optimized for low-power, synthesizable designs in microcontrollers and SoCs. The MIPS32 M4K core, introduced around 2002, targeted cost-sensitive control applications with a compact footprint of 0.3 mm² in 0.13 μm process technology, clock speeds exceeding 300 MHz, and power efficiency as low as 0.10 mW/MHz, making it suitable for deeply embedded tasks like and industrial controls. Its architectural enhancements, including dynamic branch prediction and optional DSP extensions, balanced performance and energy use without compromising the MIPS32 instruction set compatibility. Key innovations across these families included multi-threading support via the MIPS MT Application Specific Extension, first implemented in the 34K core in 2005, which enabled fine-grained multithreading to improve throughput in networking and by scheduling multiple threads on a single core. Later, MIPS32/64 Release 6 in 2014 added through the VZ module, supporting up to 15 guest partitions for enhanced security and multi-OS environments in embedded and server applications. These features extended the architecture's versatility, with embedded cores like the M4K emphasizing power efficiency for battery-operated devices. Development of new MIPS architecture processor cores effectively ceased after 2020, following the company's strategic pivot away from proprietary designs, leaving existing implementations for legacy support in licensees' products.

RISC-V Based IP Cores

In 2022, MIPS introduced the eVocore family of RISC-V-based processor IP cores as its first offerings under the open RISC-V instruction set architecture (ISA), designed to leverage the company's legacy in high-performance RISC designs by adapting them for RISC-V compatibility. These cores serve as drop-in replacements for legacy MIPS architectures in embedded systems, supporting both RV32 and RV64 configurations while incorporating custom extensions for enhanced functionality, such as out-of-order execution and multi-threading to maintain performance parity with prior MIPS implementations. The eVocore lineup emphasizes licensable IP for system-on-chip (SoC) integration, targeting applications in networking, datacenters, and automotive systems where scalability and efficiency are critical. The eVocore family includes variants tailored to different performance and efficiency needs. The P-series, exemplified by the eVocore P8700, focuses on high-performance applications with a deep-pipelined, out-of-order superscalar that supports multi-issue execution and vector processing extensions suitable for AI and workloads. This variant delivers superior single-threaded performance compared to contemporary IP and scales to 64 clusters with up to 512 cores and 1,024 hardware threads, enabling coherent multi-core processing for compute-intensive tasks. In contrast, the I8500, an in-order triple-issue processor, targets efficient orchestration in hyperscale, storage, automotive, and industrial SoCs, featuring performance-per-watt optimization while scaling to 64 clusters, 512 cores, and 2,048 threads. Both series incorporate user-defined instructions for custom accelerators, ensuring flexibility in environments. Key integration features of the eVocore cores include multi-core scalability through cluster-based designs with directory-based cache coherency, enabling seamless expansion for multi-processor systems. is addressed via physical memory protection (PMP) modules, supporting safety standards like ASIL-D for automotive use cases, alongside for isolated execution environments. Compatibility with the existing MIPS software ecosystem is maintained through support for MIPS development tools and an open software stack, allowing licensees to port legacy code and utilize familiar and verification flows. By late 2022, the eVocore P8700 had already been licensed for next-generation automotive applications, including integration with Mobileye's autonomous driving platforms, demonstrating early adoption in high-volume sectors.

AI-Focused Chip Designs

In 2025, MIPS Technologies launched the Atlas portfolio, a series of multi-core -based compute subsystems designed specifically for physical AI applications requiring real-time inference and processing at . This initiative marks MIPS' entry into complete chip-level solutions optimized for autonomous systems, integrating neural processing units (NPUs) alongside cores to handle sensor , decision-making, and control actions. The portfolio is structured around three functional categories—Sense, Think, and Act—to address the full pipeline of physical AI workloads, enabling low-latency operations in resource-constrained environments such as and vehicles. The Atlas family features configurable multi-core architectures with integrated NPU acceleration for efficient AI inference. Key components include the P8700 and I8500 in the category for high-throughput ingestion and , the S8200 in the Think category as a dedicated NPU subsystem for reinforcement learning and generative AI models with matrix-vector coprocessors, and the M8500 in the Act category for deterministic, sub-10 μs control loops in real-time actuation. These subsystems emphasize capabilities and low-latency processing, allowing seamless integration of heterogeneous accelerators while maintaining power efficiency for edge deployment. This launch represents a strategic shift for MIPS from IP licensing to a fabless semiconductor model, facilitated by its acquisition by GlobalFoundries in July 2025, with the deal completing on August 14, 2025, expanding access to diverse process technologies and ecosystems for automotive-grade reliability. The Atlas chips target industrial automation, such as robotic arms for precise manipulation, and automotive applications including advanced driver-assistance systems (ADAS) and autonomous vehicles, with volume shipments projected to begin in 2026 and initial customer production ramping in 2027.

Business and Ecosystem

Licensing Model and Revenue Streams

MIPS Technologies has traditionally operated on a fabless (IP) licensing model, generating through upfront license fees for access to its processor cores and architectures, combined with per-unit royalties on products incorporating the licensed IP. Under typical agreements, customers pay a fixed upfront fee for the right to use MIPS-developed cores, with the fee scale varying based on usage scope—such as limited or unlimited deployments—often reaching higher amounts for broader, perpetual access rights. Royalties, calculated as a percentage of sales or a fixed amount per shipped unit, form a significant portion of ongoing , historically ranging from $1 to $3 per device in embedded markets, though rates adjust according to volume commitments and application complexity. This dual-stream approach allows MIPS to recoup development costs initially while benefiting from long-term by licensees. The company's revenue model evolved from its founding in the , when it focused on high-volume licensing to workstation and computing partners like , emphasizing upfront contracts for custom RISC designs. By the late and early , royalties surged due to adoption in consumer devices, such as Nintendo's gaming consoles, pushing annual revenues to $84.9 million in 2001, with royalties comprising over 70% of total income during that period. As MIPS shifted toward embedded and mobile applications in the , the model incorporated more flexible terms, including options for certain legacy architectures to spur adoption amid competition from . By the , following its pivot to RISC-V-based IP under the Atlas portfolio, MIPS adopted a hybrid structure blending traditional licensing with direct support for custom silicon, further diversified in August 2025 through its acquisition by , which integrates IP licensing with foundry manufacturing services to enable end-to-end chip production revenue. Following the August 2025 acquisition, MIPS has begun integrating its IP with GlobalFoundries' manufacturing processes to offer end-to-end solutions, with initial announcements focusing on enhanced AI capabilities as of late 2025. Financial performance has reflected this evolution, with peak revenues in the early driven by embedded licensing deals, but subsequent years saw fluctuations tied to licensee shipments, reaching an estimated $86.2 million in 2024, bolstered by growing adoption in AI and . Post-acquisition, the model anticipates enhanced stability through bundled IP and fabrication offerings, though it remains vulnerable to cycles, where demand downturns can delay royalty recognition and contract signings. Additionally, competition from open-source alternatives like pure implementations poses risks, pressuring MIPS to differentiate via proprietary extensions and support to maintain royalty streams.

Major Licensees and Partnerships

MIPS Technologies' early success was driven by key partnerships with major semiconductor and computing firms. Silicon Graphics Inc. (SGI), which initially developed the , spun off MIPS Technologies in 1998 to focus on IP licensing, establishing a foundational licensee relationship that propelled the company's growth in workstation and graphics markets. NEC Electronics licensed MIPS RISC technology to manufacture the VR series of high-performance microprocessors, targeting consumer and embedded applications. Computer Entertainment collaborated closely with MIPS and to develop the processor for the console, based on the custom MIPS R5900 core, which powered over 155 million units sold worldwide. , a long-term partner since the , licensed MIPS architectures for networking chips and embedded systems in automotive and digital consumer products, contributing to more than a decade of joint system solutions. In the sector, MIPS cores achieved significant market penetration; for instance, approximately 75% of Blu-ray Disc players in the 2000s utilized MIPS-based processors from licensees like and Sigma Designs. By 2020, cumulative shipments of MIPS-based chips exceeded 5 billion units, reflecting the architecture's widespread adoption across embedded devices. Following its acquisition by Wave Computing in and subsequent rebranding to MIPS in 2021 with a pivot to , the company expanded its licensee base in emerging markets. licensed multi-threaded MIPS I-class CPUs for LTE modems in smartphones and extended the agreement for high-performance wireless, networking, and IoT applications in next-generation products. Wave Computing's integration of MIPS technology influenced AI-focused startups, leveraging the IP for parallel processing in workloads before the company's restructuring. In 2025, MIPS announced strategic partnerships to bolster its offerings. agreed to acquire MIPS in July, completing the transaction on August 14, 2025 to integrate MIPS' AI and processor IP with advanced manufacturing capabilities, enhancing supply chain security for edge and . Additionally, MIPS partnered with Semiconductor in June to develop custom -based intelligent power solutions for industrial , AI power delivery, and automotive applications, aligning with MIPS' strategic shift toward robotics-focused chip design. These collaborations underscore MIPS' transition to open-standard architectures while maintaining over 8.5 billion cumulative MIPS-based chips shipped to date.

Supported Operating Systems and Software

MIPS processors have historically supported a range of operating systems, beginning with legacy implementations in the . The port for was initiated in the early , enabling widespread use in embedded systems and workstations, with ongoing maintenance through official kernel documentation and community efforts. ' , a proprietary variant of , was specifically developed for MIPS-based workstations and servers, providing advanced graphics and multiprocessing capabilities until its discontinuation in 2013. briefly ported to MIPS in the early , supporting versions up to NT 4.0 for select hardware like DECstations, though adoption was limited due to competition from x86 platforms. Following MIPS Technologies' transition to RISC-V in 2021, compatibility with modern operating systems has shifted toward open-source ecosystems. The mainline has provided robust support since version 4.15 in 2017, with enhanced integration for MIPS-derived cores accelerating development for embedded and server applications post-2021. , a popular for embedded devices, offers official ports for 32-bit and 64-bit cores, including machine-mode execution tailored for low-power IoT applications. Android adaptations for , upstreamed into the Android Open Source Project in 2022, focus on IoT and wearable devices, with initial support for the RVA22 profile and vector extensions enabling efficient mobile-like functionality on resource-constrained hardware. Development tools for MIPS and its RISC-V successors emphasize open-source and vendor-specific solutions to facilitate software creation and testing. The GNU Compiler Collection (GCC) has long supported MIPS instruction sets through dedicated backends, while RISC-V compatibility was added starting with GCC 7 in 2017, allowing seamless cross-compilation for both architectures in embedded and high-performance contexts. MIPS-specific software development kits, such as those including the QtSpim simulator, provide a graphical interface for executing and debugging MIPS32 assembly code, aiding educational and prototyping efforts without hardware. In 2025, as part of the MIPS Atlas portfolio, RISC-V toolchains expanded to include optimized SDKs like the M8500 series, which bundle compilers, debuggers, and integration for real-time AI and automotive applications, with further enhancements following the integration with later that year. Migrating software from MIPS to presents challenges due to the architectures' incompatibility at the binary level, necessitating recompilation of or implementation of emulation layers for legacy binaries. MIPS Technologies recommends source-level porting strategies, leveraging tools like GCC for retargeting, though dynamic remains an option for performance-critical embedded codebases to minimize disruption during transitions.

Applications and Impact

Key Industry Applications

MIPS Technologies' processor architectures have found widespread adoption in , particularly in gaming consoles and networking equipment. The , released by in 2000, utilized the , a custom MIPS R5900 CPU clocked at 294.912 MHz, which powered its advanced graphics and multimedia capabilities. This console achieved remarkable commercial success, with over 160 million units sold worldwide as confirmed by in 2024. In networking, MIPS cores have been integral to routers and modems; for instance, the employed 32-bit MIPS processors to handle Ethernet and connectivity, enabling efficient packet processing in home and small office environments. Similarly, integrated MIPS-based processors into broadband access devices, contributing to their dominance in DSL and markets. In embedded systems, MIPS architectures powered a significant portion of set-top boxes and automotive solutions during the 2000s and beyond. MIPS held a leading position in digital home devices, including digital televisions, set-top boxes, and Blu-ray players, where its cores facilitated decoding and processing. For example, partnerships like those with Laboratories enabled MIPS processors to support advanced audio technologies in Blu-ray disc players and HD DVD set-top boxes. In automotive applications, MIPS-based processors were used in the EyeQ3 chip for computer vision systems in the , enabling features like for detection of road signs, lane markings, and obstacles. Additionally, MIPS cores supported in-car networking solutions from companies like , optimizing data transfer for multimedia and sensor integration in vehicles. With MIPS' transition to RISC-V-based designs, the architecture has expanded into modern AI applications at the edge, particularly in smart home devices and autonomous systems. RISC-V cores from MIPS, such as the eVocore series, target energy-efficient processing for smart home gateways and IoT hubs, enabling real-time control of sensors and appliances. In 2025, MIPS introduced the Atlas product suite, featuring RISC-V compute subsystems optimized for physical AI in edge devices, including support for multi-modal sensing and low-latency decision-making in autonomous drones. Following the completion of its acquisition by on August 14, 2025, MIPS continues to operate independently, leveraging GF's process technologies to advance RISC-V solutions for edge AI in automotive and industrial sectors. MIPS maintains strong market penetration in system-on-chips (SoCs) for IoT applications, driven by its established and focus on high-volume embedded markets. The company's expansion in the has capitalized on growing demand for SoCs in consumer and industrial devices, underscoring its role in powering billions of connected units annually.

Contributions to Computing

MIPS Technologies played a pivotal role in pioneering Reduced Instruction Set Computing (RISC) principles, emphasizing simplicity and efficiency in processor design that contrasted sharply with Complex Instruction Set Computing (CISC) architectures. The MIPS instruction set architecture (ISA), with its core set of approximately 55 basic instructions focused on load/store operations and register-based processing, served as a benchmark for streamlined execution, enabling faster pipelining and reduced hardware complexity compared to CISC systems like the x86, which feature over 300 instructions including complex memory operations. This design philosophy directly influenced subsequent RISC architectures, including ARM and PowerPC, which adopted similar load/store models and fixed-length instructions to prioritize performance in resource-constrained environments. Early benchmarks, such as those comparing MIPS processors to VAX CISC systems, demonstrated up to 3-5 times better cycles-per-instruction efficiency, underscoring MIPS's contributions to the RISC paradigm's dominance in high-speed computing. The has had a profound educational impact, becoming a staple in university curricula due to its elegant simplicity, which facilitates teaching fundamental concepts like pipelining, caching, and without the intricacies of more complex ISAs. Widely adopted in academic settings since the 1980s, MIPS-based simulations and hardware kits have trained generations of engineers, contributing to the talent pool at leading tech firms; for instance, its use in courses at institutions like Stanford and MIT has influenced alumni who advanced processor innovations at companies including and Apple. , MIPS's parent at the time, explicitly offered MIPS blueprints for academic use in 2015, highlighting its suitability for hands-on learning in embedded systems and . This pedagogical legacy has democratized access to advanced , fostering innovation in software and hardware . MIPS's pivot to RISC-V in the early 2020s marked a significant contribution to open-source processor ecosystems, accelerating the adoption of royalty-free ISAs and reducing barriers to customization in diverse applications. By abandoning its proprietary MIPS ISA in favor of RISC-V cores, such as the multi-threaded eVocore series announced in 2022, MIPS facilitated broader software development and interoperability, with collaborations like those with Synopsys enabling early toolchain support. This shift aligned with explosive growth in the RISC-V ecosystem, driven by sectors like automotive and AI, and contributing to a surge in startups—evidenced by new ventures like Ahead Computing raising $21.5 million in 2025 for RISC-V chips. Initiatives like the RISC-V Software Ecosystem (RISE) project, launched in 2023 with industry leaders, further amplified MIPS's open-source legacy by enhancing tools such as LLVM and GCC for RISC-V. Through these advancements, MIPS has broadened access to in embedded devices, challenging x86's hegemony by enabling cost-effective, power-efficient alternatives tailored for IoT, networking, and edge AI. The architecture's focus on scalable, multi-core designs has empowered developers to integrate custom accelerators without licensing fees, as seen in RISC-V's rise to over 10 billion cores shipped by 2025, fostering innovation in non-x86 domains like smart devices and autonomous systems. This has reduced reliance on proprietary ecosystems, promoting a more diverse and inclusive computing landscape.

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