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A Toshiba R4000 microprocessor
A IDT R4000 microprocessor
MIPS R4000 die shot

The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.

Models

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There are three configurations of the R4000: the R4000PC, an entry-level model with no support for a secondary cache; the R4000SC, a model with secondary cache but no multiprocessor capability; and the R4000MC, a model with secondary cache and support for the cache coherency protocols required by multiprocessor systems.

Description

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The R4000 is a scalar superpipelined microprocessor with an eight-stage integer pipeline. During the first stage (IF), a virtual address for an instruction is generated and the instruction translation lookaside buffer (TLB) begins the translation of the address to a physical address. In the second stage (IS), translation is completed and the instruction is fetched from an internal 8 KB instruction cache. The instruction cache is direct-mapped and virtually indexed, physically tagged. It has a 16- or 32-byte line size. Architecturally, it could be expanded to 32 KB.

During the third stage (RF), the instruction is decoded and the register file is read. The MIPS III defines two register files, one for the integer unit and the other for floating-point. Each register file is 64 bits wide and contained 32 entries. The integer register file has two read ports and one write port, while the floating-point register file has two read ports and two write ports. Execution begins at stage four (EX) for both integer and floating-point instructions; and is written back to the register files when completed in stage eight (WB). Results may be bypassed if possible.

Integer execution

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The R4000 has an arithmetic logic unit (ALU), a shifter, multiplier and divider and load aligner for executing integer instructions. The ALU consists of a 64-bit carry-select adder and a logic unit and is pipelined. The shifter is a 32-bit barrel shifter. It performs 64-bit shifts in two cycles, stalling the pipeline as a result. This design was chosen to save die area. The multiplier and divider are not pipelined and have significant latencies: multiplies have a 10- or 20-cycle latency for 32-bit or 64-bit integers, respectively; whereas divides have a 69- or 133-cycle latency for 32-bit or 64-bit integers, respectively. Most instructions have a single cycle latency. The ALU adder is also used for calculating virtual addresses for loads, stores and branches.

Load and store instructions are executed by the integer pipeline, and access the on-chip 8 KB data cache.

Floating-point execution

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The R4000 has an on-die IEEE 754-1985-compliant floating-point unit (FPU), referred to as the R4010. The FPU is a coprocessor designated CP1[1] (the MIPS ISA defined four coprocessors, designated CP0 to CP3). The FPU can operate in two modes, 32- or 64-bit which are selected by setting a bit, the FR bit, in the CPU status register. In 32-bit mode, the 32 floating-point registers become 32 bits wide when used to hold single-precision floating-point numbers. When used to hold double-precision numbers, there are 16 floating-point registers (the registers are paired).

The FPU can operate in parallel with the ALU unless there is a data or resource dependency, which causes it to stall. It contains three sub-units: an adder, a multiplier and a divider. The multiplier and divider can execute an instruction in parallel with the adder, but they use the adder in their final stages of execution, thus imposing limits to overlapping execution. Thus, under certain conditions, it can execute up to three instructions at any time, one in each unit. The FPU is capable of retiring one instruction per cycle.

The adder and multiplier are pipelined. The multiplier has a four-stage multiplier pipeline. It is clocked at twice the clock frequency of the microprocessor for adequate performance and uses dynamic logic to achieve the high clock frequency. Division has a 23- or 36-cycle latency for single- or double-precision operations and square-root has a 54- or 112-cycle latency. Division and square-root uses the SRT algorithm.

Memory management

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The memory management unit (MMU) uses a 48-entry translation lookaside buffer to translate virtual addresses. The R4000 uses a 64-bit virtual address, but only implements 40 of the 64 bits, allowing 1 TB of virtual memory; the remaining bits are checked to ensure that they contain zero. The R4000 uses a 36-bit physical address, thus is able to address 64 GB of physical memory.

Secondary cache

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The R4000 (SC and MC configurations only) supports an external secondary cache with a capacity of 128 KB to 4 MB. The cache is accessed via a dedicated 128-bit data bus. The secondary cache can be configured either as a unified cache or as a split instruction and data cache. In the latter configuration, each cache can have a capacity of 128 KB to 2 MB.[2] The secondary cache is physically indexed, physically tagged and has a programmable line size of 128, 256, 512 or 1,024 bytes. The cache controller is on-die. The cache is built from standard static random access memory (SRAM). The data and tag buses are ECC-protected.

System bus

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The R4000 uses a 64-bit system bus called the SysAD bus. The SysAD bus was an address and data multiplexed bus, that is, it used the same set of wires to transfer data and addresses. While this reduces bandwidth, it is also less expensive than providing a separate address bus, which requires more pins and increases the complexity of the system. The SysAD bus can be configured to operate at half, a third or a quarter of the internal clock frequency. The SysAD bus generates its clock signal by dividing the operating frequency.

Transistor count, die dimensions and process details

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The R4000 contains 1.2 million transistors.[3] It was designed for a 1.0 μm two-layer metal complementary metal–oxide–semiconductor (CMOS) process. As MIPS was a fabless company, the R4000 was fabricated by partners in their own processes, which had a 0.8 μm minimum feature size.[4]

Clocking

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The R4000 generates the various clock signals from a master clock signal generated externally. For the operating frequency, the R4000 multiplies the master clock signal by two by use of an on-die phase-locked loop (PLL).

Packaging

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The R4000PC is packaged in a 179-pin ceramic pin grid array (CPGA). The R4000SC and R4000MC are packaged in a 447-pin ceramic staggered pin grid array (SPGA). The pin out of the R4000MC is different from the R4000SC, with some pins which are unused on the R4000SC used for signals to implement cache coherency on the R4000MC. The pin-out of the R4000PC is similar to that of the PGA-packaged R4200 and R4600 microprocessors. This characteristic enables a properly designed system to use any of the three microprocessors.

R4400

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An example of a R4400MC microprocessor fabricated by Toshiba
A LSI Logic R4400 microprocessor
NEC VR4400MC die shot

The R4400 is a further development of the R4000. It was announced in early November 1992. Samples of the microprocessor had been shipped to selected customers before then, with general availability in January 1993. The R4400 operates at clock frequencies of 100, 133, 150, 200, and 250 MHz. The only major improvement from the R4000 is larger primary caches, which were doubled in capacity to 16 KB each from 8 KB each. It contained 2.3 million transistors.

The R4400 was licensed by Integrated Device Technology (IDT), LSI Logic, NEC, Performance Semiconductor, Siemens AG and Toshiba. IDT, NEC, Siemens and Toshiba fabricated and marketed the microprocessor. LSI Logic used the R4400 in custom products. Performance Semiconductor sold their logic division to Cypress Semiconductor where the MIPS microprocessor products were discontinued.

NEC marketed their version as the VR4400. The first version, a 150 MHz part, was announced in November 1992. Early versions were fabricated in a 0.6 μm process.[5] In mid-1995, a 250 MHz part began sampling. It was fabricated in a 0.35 μm four-layer-metal process.[6] NEC also produced the MR4401, a ceramic multi-chip module (MCM) that contained a VR4400SC with ten 1 Mbit SRAM chips that implemented a 1 MB secondary cache. The MCM was pin-compatible with the R4x00PC. The first version, a 150 MHz part, was announced in 1994. In 1995, a 200 MHz part was announced.

Toshiba marketed their version as the TC86R4400. A 200 MHz part containing 2.3 million transistors and measuring 134 mm2 fabricated in a 0.3 μm process was introduced in mid-1994. The R4400PC was priced at $1,600, the R4400SC at $1,950, and the R4400MC at $2,150 in quantities of 10,000.[7]

Usage

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The R4400 is used by:

Chipsets

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The R4000 and R4400 microprocessors were interfaced to the system by custom ASICs or by commercially available chipsets. System vendors such as SGI developed their own ASICs for their systems. Commercial chipsets were developed, fabricated and marketed by companies such as Toshiba with their the Tiger Shark chipset, which provided a i486-compatible bus.[13]

Notes

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References

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

R4000

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from Grokipedia
The R4000 is a 64-bit reduced instruction set computing (RISC) microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Introduced in 1991, it represents the first true 64-bit RISC processor, extending the capabilities of prior MIPS designs like the R3000 by supporting 64-bit virtual addresses and registers while maintaining full backward compatibility with 32-bit MIPS software. The R4000 was engineered amid the shift toward larger address spaces and higher in computing systems, incorporating superpipelining across eight stages to enable concurrent instruction and achieve superior benchmark results, such as top SPEC among contemporary microprocessors. Fabricated using a 1.0-micron process with approximately 1.1 to 1.3 million transistors, it integrated key components including a (FPU), (MMU), 8 KB instruction cache, 8 KB cache, and support for external secondary caches up to 4 MB. Clock speeds reached up to 100 MHz internally (derived from a 50 MHz external clock), with a 64-bit bus and 36-bit bus, allowing operation in both big-endian and little-endian modes as well as 32-bit or 64-bit configurations. Following its release, (restructured after acquisition by in 1992) produced variants such as the R4000PC (primary cache only), R4000SC (with secondary cache controller), and R4000MC (multiprocessor support), manufactured by partners including , , LSI Logic, and . These adaptations enabled deployment in diverse applications, from low-power embedded systems like Zenith Internet TVs and Alteon network routers to high-end graphics workstations by . The R4000's architecture influenced subsequent MIPS processors and contributed to advancements in during the early 1990s, bridging the gap between 32-bit desktops and scalable server environments while emphasizing programmable interfaces for flexible .

Development and History

Background and Design Goals

The MIPS R4000 represented a pivotal evolution in the company's R-series processors, transitioning from the 32-bit —introduced in —to a 64-bit superpipelined implementation of the MIPS (ISA). This shift was motivated by the need to address growing demands for larger memory addressing and enhanced computational capabilities in environments, building directly on the R3000's pipelined design while extending register widths, data paths, and virtual address spaces to 64 bits. The development began in the late 1980s, with MIPS Computer Systems deciding by late to pursue a true 64-bit CPU as its next-generation processor. Central to the R4000's design goals was achieving high performance, targeting approximately 100 SPECmarks by 1993 through a superpipelined that aimed for an execution rate of about one instruction per cycle via an 8-stage , alongside support for clock speeds up to 100 MHz. The processor was engineered to provide full 64-bit operations across registers, the (ALU), (FPU), and , enabling efficient handling of large datasets and extended addressing while maintaining complete with 32-bit MIPS software from earlier R-series models like the R2000, , and R6000. This compatibility ensured seamless migration for existing applications in user mode, a key consideration for adoption in UNIX workstations and embedded systems. The R4000's architecture drew heavily from foundational RISC principles, including load-store design, fixed-length instructions, and reliance on optimizing compilers, which had been advanced through academic and industry efforts in the late 1970s and early 1980s. Key influences included MIPS co-founder John Hennessy's work on simplified instruction sets at Stanford, alongside competitive pressures from rival RISC architectures such as ' and Hewlett-Packard's , which were vying for dominance in the workstation market during the late 1980s. The core design team at MIPS Computer Systems, including engineers like Sunil Mirapuri, Michael Woodacre, and Nader Vasseghi, integrated these elements to create a highly integrated single-chip solution with on-board caches and .

Release and Initial Adoption

The MIPS R4000 microprocessor was officially announced by MIPS Computer Systems on October 1, 1991, marking it as one of the first commercially available 64-bit RISC processors and the inaugural implementation of the MIPS III instruction set architecture. This launch came as part of the Advanced Computing Environment (ACE) initiative, a consortium involving partners like Compaq, Digital Equipment Corporation (DEC), and Microsoft, aimed at standardizing hardware and software for high-performance computing. First shipments of the chip began in early 1992, enabling initial system integrations shortly thereafter. Initial specifications featured an external master clock of 50 MHz, doubling to a 100 MHz internal pipeline clock for enhanced instruction throughput, with power consumption under 2 watts at this frequency. However, early production encountered challenges, including high costs exceeding $300 per chip and yield limitations that necessitated fabrication across multiple partners such as Integrated Device Technology (IDT), Performance Semiconductor, LSI Logic, Siemens-Nixdorf, and NEC to meet demand. These factors positioned the R4000 as a premium component, primarily for professional and enterprise applications rather than consumer markets. Adoption accelerated through key partnerships, notably with (SGI), which integrated the R4000 into its IRIS workstation released in January 1992—the first 64-bit SGI system—and extended its use to early supercomputing via the Challenge server series for scalable . These deployments highlighted the R4000's suitability for graphics-intensive and scientific workloads, despite initial hurdles, and helped establish in high-end computing niches during the early .

Core Architecture

Integer Execution Unit

The integer execution unit of the MIPS R4000 employs a superpipelined design with eight stages to enable higher clock frequencies while maintaining compatibility with the MIPS . These stages consist of IF (first half of instruction fetch, including PC selection and primary cache access initiation), IS (second half of instruction fetch), RF ( access and decode), EX (execution of ALU operations and condition evaluation), DF (first half of data memory access), DS (second half of data memory access and result selection), TC (tag check for cache hit/miss determination), and WB (writeback to the ). This structure extends the classic five-stage by subdividing fetch, decode, execute, memory, and writeback phases, allowing the processor to sustain one instruction completion per cycle in despite the deeper . The R4000 operates as a scalar processor, issuing and completing one instruction per cycle in an in-order manner, without superscalar dual-issue capabilities; however, out-of-order completion is not supported, as results are committed in program order during the WB stage. The unit includes a 64-bit (ALU) capable of performing operations such as , , bitwise logic (AND, OR, XOR, NOR), comparisons, and shifts on 64-bit operands, with dedicated hardware for (using a 2-bit Booth recoding , yielding 10-cycle latency for 32-bit results and 20 cycles for 64-bit) and division (1-bit per , with 32 cycles for 32-bit quotients and 64 cycles for 64-bit). Representative examples include 64-bit add (ADD) for basic and shift left logical (SLL) for variable shifts up to 63 bits, emphasizing the unit's support for both 32-bit legacy and native 64-bit computations under the MIPS III . The load/store unit is tightly integrated into the , handling address generation in the EX stage and memory operations across DF, DS, and TC stages to support 64-bit aligned and unaligned accesses; loads produce results available for forwarding from the DS/TC boundary, while stores commit data during TC upon cache hit confirmation. This design accommodates the 64-bit virtual addressing and data paths, enabling efficient load (e.g., LD for 64-bit) and store (SD) instructions without separate address generation hardware beyond the ALU. handling relies on a static delayed branch mechanism rather than dynamic , requiring a one-instruction that is always executed; untaken branches incur no additional penalty beyond the slot, but taken branches resolved in EX may stall the by up to three cycles if the cannot mitigate the fetch disruption, with no history table employed.

Floating-Point Execution Unit

The R4000 incorporates a dedicated (FPU) as Coprocessor 1 (CP1), tightly integrated on-chip to extend the CPU's instruction set for operations. This FPU employs an eight-stage superd architecture that aligns with the pipeline, enabling overlapping execution of FP instructions with the pipeline. The facilitates seamless interaction between the CPU and , with FP instructions mapped to formats that allow the CPU to stall if the FPU is busy, ensuring data dependencies are resolved before proceeding. The FPU fully complies with the standard, providing accurate representation and computation for floating-point numbers, including support for single-precision (32-bit), double-precision (64-bit), and limited quadruple-precision operations through paired registers. It features specialized functional units for addition/subtraction, , and division, with the including stages such as Unpack (U), Shift (S), Mantissa Add (A), Multiplier (M/N), (R), and Exception Test (E), which instructions traverse in operation-specific sequences. For instance, addition and subtraction operations typically complete in 4 cycles for both single and double precision, while requires 7 cycles for single precision and 8 cycles for double precision; division latencies are longer at 23 cycles (single) and 36 cycles (double), reflecting the iterative nature of these computations. These latencies allow for efficient pipelining, where subsequent instructions can initiate after the repeat rate (e.g., 3 cycles for add, 4 for multiply), minimizing stalls in well-scheduled code. Exception handling in the FPU adheres to recommendations, detecting and signaling conditions such as underflow, overflow, and denormalized operands during execution. These exceptions are recorded in the Floating-Point Control/Status Register (FCR31), which includes fields for , Enable, and Flags to prioritize and manage traps— for example, overflow and underflow take precedence over inexact results. Upon detection, the FPU signals a trap to the CPU, which uses the (EPC) in Coprocessor 0 to invoke software handlers, allowing precise recovery or emulation as needed; denormalized numbers are handled with gradual underflow to maintain accuracy without immediate trapping unless enabled. This mechanism ensures robust operation in numerical applications, with the FPU supporting fused multiply-add instructions that combine multiplication and addition in a single pipelined pass to reduce rounding errors.

Memory Management Unit

The MIPS R4000 (MMU) implements a 64-bit virtual addressing scheme with to 32-bit addressing, enabling a vast divided into distinct segments that vary by mode. In 32-bit , segments include KUSEG for user-mode access (0 to 2^{31} or 2 GB), KSEG0 and KSEG1 for kernel-mode direct physical mapping (cached and uncached, respectively, each 2^{29} or 512 MB), and KSEG2/KSSEG for kernel-mode and supervisor TLB-mapped regions (each 512 MB). In native 64-bit mode, extended segments provide larger spaces, such as XKUSEG for user-mode (up to 2^{40} or 1 TB), and XKSEG for kernel-mode TLB-mapped regions (up to 1 TB). This design supports both 32-bit and 64-bit operations, with virtual addresses translated to 36-bit physical addresses in 64-bit mode, allowing for efficient handling of large memory configurations in multiprocessor systems. At the core of the MMU is a fully associative 48-entry (TLB) with 64-bit entries, each mapping two consecutive pages (odd/even pairs) for a total of 96 effective pages and supporting software expansion through refill mechanisms. The TLB entries include fields for virtual page number (VPN), physical frame number (PFN), identifier (ASID) for , page mask for variable sizing, and attribute bits such as valid (V), dirty (D) for writability, and global for shared mappings. Page sizes range from 4 KB to 16 MB in powers-of-four increments (4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB), facilitated by multi-level page tables managed in software to accommodate hierarchical translation structures during misses. Protection is enforced through user/kernel mode separation via the Status register's KSU (Kernel/Supervisor/User) bits, restricting access to segments accordingly, alongside per-page permissions controlled by TLB attributes: the valid bit governs read and execute access (with instruction fetches treated as reads), while the enables write permissions. Violations trigger privilege or access exceptions, ensuring secure isolation between user and kernel spaces. TLB misses are handled by generating specific exceptions—such as TLB Refill for fast handler intervention or general TLB Miss/Invalid for full traps—which invoke software routines to probe multi-level page tables using or XContext registers, load the appropriate translation into the TLB via instructions like TLBWI (write indexed) or TLBWR (write random), and restart the faulting instruction from the Exception Program Counter (EPC). This software-managed approach allows flexible OS policies while minimizing hardware overhead. Integer load and store instructions interact with the MMU by generating virtual addresses that undergo TLB lookup for translation and protection checks prior to cache access.

Cache and System Interface

Secondary Cache Design

The R4000 microprocessor incorporates an on-chip primary cache system based on a Harvard architecture, featuring a separate 8 KB instruction cache (I-cache) and an 8 KB data cache (D-cache). Both caches are direct-mapped with virtual indexing and physical tagging, with software-programmable line sizes of 16 or 32 bytes to optimize access latency within the processor's pipeline. The I-cache supports up to two accesses per clock cycle for instruction fetches, while the D-cache handles load and store operations through dedicated 64-bit data paths. The external secondary cache interface enables support for off-chip cache implementations ranging from 128 KB to 4 MB in joint (unified instruction/data) mode or up to 2 MB in split (separate instruction/data) mode, configured as direct-mapped. This secondary cache is physically indexed and tagged, with line sizes programmable from 16 to 128 bytes (4 to 32 words), and requires an external tag RAM array that is 25 bits wide per entry, including valid, dirty, and error-checking fields with 7-bit ECC for single-error correction and double-error detection. Cache indexing relies on physical addresses generated by the to ensure consistency across virtual-to-physical translations. The tag RAM is managed via processor registers such as TagLo and TagHi, allowing software control over cache operations like index invalidation and tag loading. Cache coherency in the R4000 follows a MESI-like protocol extended for multiprocessor environments, with five states per cache line: Invalid, Shared, Clean Exclusive, Dirty Exclusive, and Dirty Shared. This protocol maintains consistency between the primary and secondary caches, as well as across multiple processors, using interventions such as write invalidates for shared data and updates for modified lines. In multiprocessor setups, coherency attributes like Uncached, Noncoherent, Sharable, Update, and Exclusive are applied to memory regions to enforce appropriate . The secondary cache employs a write-back policy, where modified (dirty) lines are retained until eviction, at which point they are written back to main . To handle write-back efficiently, the R4000 includes a victim buffer that temporarily stores dirty lines displaced from the cache, reducing bus traffic and supporting burst transfers of 4- or 8-word blocks during write cycles. This design minimizes latency for write operations while ensuring in both uniprocessor and multiprocessor configurations.

System Bus Specifications

The R4000 employs a 64-bit multiplexed and bus known as the SysAD bus, which serves as the primary interface for and I/O interactions in MIPS-based systems. This bidirectional bus combines and signals on the same 64 wires, enabling efficient transfers by first asserting the during the initial cycle and then multiplexing on subsequent cycles. Operating within a 36-bit space (supporting up to 64 GB), the SysAD bus facilitates both big-endian and little-endian byte ordering and includes an 8-bit check bus (SysADC) for error detection on the main lines, along with a 9-bit command bus (SysCmd) protected by a (SysCmdP) to specify transaction types. Bus arbitration is handled externally via a centralized controller, accommodating both single-processor and multiprocessor configurations with built-in support for cache coherency through snoop protocols. The processor asserts a request signal (Req) to gain bus mastery, which is granted by the external arbiter via the Gnt signal; alternatively, external agents can request control using the low-active ExtRqst* input, with the processor responding via the low-active Release* output to relinquish the bus for one cycle. This mechanism ensures orderly access in shared environments, with the system clock (SysClk) driving all transactions on its rising edge and running at half the processor clock frequency for synchronization. Electrical specifications align with TTL-compatible levels, requiring a stable +5V supply (VccOk above 4.75V for over 100 ms) and supporting peak data rates of 400 Mbytes/second at 50 MHz, with timings controlled by delays of 0.5T, 0.75T, or T relative to the master clock period. Transaction types on the SysAD bus include single-beat reads and writes for individual 64-bit doublewords, as well as burst modes optimized for cache line fills, transferring four consecutive 64-bit words (256 bits total) in a single operation to minimize latency. Additional commands cover invalidates and updates for cache maintenance, snoops for coherence in multiprocessor setups, and specialized loads/stores (e.g., LDL/SDR for partial doubleword handling across boundaries). The ValidIn* and ValidOut* signals (low-active) indicate valid from external agents or the processor, respectively, while the IvdErr* signal reports invalid errors during transactions. Secondary cache tags are interfaced through this bus for coherence checks. The following table summarizes key SysAD bus signals:
SignalTypeDescription
SysAD[63:0]Bidirectional64-bit multiplexed address/ lines.
SysADC[7:0]Bidirectional8-bit check bits for SysAD detection.
SysCmd[8:0]Bidirectional9-bit bus encoding transaction commands and identifiers.
SysCmdPBidirectional for SysCmd integrity.
SysClkInputSystem clock for latching and sampling (half processor clock rate).
ReqOutputProcessor bus request assertion.
GntInputExternal grant for bus access.
ExtRqst*InputLow-active external bus request (U2 timing).
Release*OutputLow-active bus release to external agent.
ValidIn*InputLow-active valid indicator from external source.
ValidOut*OutputLow-active valid indicator from processor.
IvdErr*BidirectionalInvalid reporting during bus operations.

Physical Implementation

Process Technology and Die Details

The R4000 microprocessor was initially fabricated using a 1.0 μm process with two layers of metal interconnection. As a fabless design from , production was handled by licensed partners including , , LSI Logic, and , who adapted the core to their specific fabrication capabilities. The initial R4000 die measured 213 mm² and incorporated 1.35 million transistors, enabling its superscalar and superpipelined architecture within the constraints of early semiconductor manufacturing. Subsequent iterations, such as the 100 MHz clocked version, reduced the die size to 165 mm² while maintaining approximately 1.3 million transistors, reflecting optimizations in layout density. Power dissipation for the R4000 varied with operating and supply voltage, typically scaling linearly with clock speed under constant voltage conditions; related variants like the R4400 consumed around 20 W at 150 MHz and 5 V. Initial models operated at 5 V, contributing to thermal management challenges in high-performance systems.

Clocking Mechanisms

The R4000 utilizes an on-chip (PLL) to generate its internal processor clock (PClock) by multiplying the external master clock (MasterClock) by two, enabling the pipeline to operate at twice the system clock rate for improved . This PLL synchronizes key internal clocks—including PClock, system clock (SClock), transmit clock (TClock), and receive clock (RClock)—to the MasterClock input, using dedicated passive components such as resistors and capacitors connected to PLLCap pins for stable operation and lock acquisition during reset. The PLL's design incorporates quiet power supplies (VccP and VssP) to mitigate noise, ensuring reliable frequency multiplication up to 2x while aligning phases across the chip. Clock distribution in the R4000 emphasizes phase alignment to the eight-stage , with signals routed to minimize skew between MasterClock and internal clocks; this is achieved through SyncIn/SyncOut mechanisms that adjust timing delays (e.g., 0.5T, 0.75T, or 1T of the MasterClock period) and a Δi/Δt to suppress during high-frequency transitions. SClock, derived by dividing PClock by configurable ratios of 2, 3, or 4 via boot-mode settings or the Config register, drives the external system interface while maintaining with pipeline stages. Initial production of the R4000 supported external MasterClock frequencies ranging from 25 to 50 MHz, yielding internal PClock rates of 50 to 100 MHz. For stable PLL locking and operation, the input MasterClock must exhibit a near-50% and low , with vendor-specified tolerances (typically under 500 ps peak-to-peak) to prevent failures or performance degradation.

Packaging Options

The R4000 offered distinct packaging variants to support a range of system designs, from high-end workstations requiring full bus and cache interfaces to cost-optimized embedded or desktop applications. The primary package for models with complete system bus support, such as the R4000SC and R4000MC, was a 447-pin staggered (SPGA) or / (LGA/PGA), enabling connections for the 64-bit SysAD bus, 128-bit secondary cache data path, and additional control signals. An alternative packaging option targeted cost-reduced systems with limited cache requirements, utilizing a 179-pin (CPGA) in the R4000PC configuration, which excluded secondary cache pins while preserving essential system interface connectivity. Thermal management in these packages emphasized robust heat dissipation due to the processor's superpipelined and power needs at frequencies up to 50 MHz, with a dedicated heatsink required for the PGA variants to maintain operational integrity. Power and ground pin assignments were strategically distributed for reliability, featuring multiple Vcc and Vss pins (e.g., A2, A4 for Vcc and A3, A6 for Vss in the 179-pin package) alongside isolated VccP and VssP pins (e.g., K17 and K16) for the PLL to reduce noise and ensure stable clocking. While the original R4000 series adhered to PGA and CPGA formats, later derivatives like the R5000 introduced (BGA) packaging, such as the 272-pin BGA, for enhanced pin density and integration, though adoption remained limited in the core R4000 lineup.

Variants and Derivatives

Primary R4000 Models

The primary R4000 models consist of the R4000PC, R4000SC, and R4000MC variants, each optimized for distinct performance and system integration needs while sharing the core 64-bit MIPS III architecture with integrated integer and floating-point units. These models were introduced by in 1991, with initial sampling in late 1991 and volume production commencing in early 1992, remaining available through 1995 before being largely supplanted by enhanced derivatives. Production volumes for the R4000 family contributed to MIPS exceeding 1 million chip shipments overall by 1993, though specific figures for individual models are not publicly detailed in contemporary reports. The R4000PC targets cost-sensitive uniprocessor systems like desktops and embedded controllers, incorporating 8 KB on-chip instruction and caches with no interface for external secondary cache. It operates at external clock speeds of 40–50 MHz (internal up to 100 MHz via clock doubling) and uses a 179-pin PGA package with a 64-bit multiplexed interface providing up to 400 MB/s bandwidth at 50 MHz. This model supports six dedicated pins and lacks cache coherency logic, prioritizing simplicity and low power over high-end scalability. In contrast, the R4000SC serves high-performance uniprocessor applications such as workstations and servers, featuring the same 8 KB primary caches alongside a dedicated 128-bit external secondary cache interface supporting 128 KB to 4 MB of off-chip cache organized in 4–32 word lines. It runs at 40–50 MHz external clocks (internal up to 100 MHz) and employs a 447-pin LGA or PGA package, including a 25-bit tag bus for secondary cache management and a single pin, but without support. This configuration enables higher and hit rates compared to the R4000PC, at the cost of increased system complexity. The R4000MC extends the R4000SC design for multiprocessor environments, adding enhanced snoop logic and cache coherency protocols to handle invalidate, update, and acknowledgment signals across multiple processors. It retains the 8 KB primary caches and secondary cache interface (128 KB–4 MB), operates at similar 40–50 MHz external speeds, and uses the 447-pin LGA/PGA package with additional pins for non-maskable interrupts and multiprocessor bus . This variant supports master/checker modes and is suited for systems, providing protocol-level coherence without requiring external controllers.
ModelPrimary CachesSecondary Cache InterfaceClock Speeds (External/Internal)PackageKey Differentiator
R4000PC8 KB None40–50 / 80–100 MHz179-pin PGACost-optimized uniprocessor
R4000SC8 KB 128-bit (128 KB–4 MB)40–50 / 80–100 MHz447-pin LGA/PGAHigh-performance uniprocessor
R4000MC8 KB 128-bit (128 KB–4 MB)40–50 / 80–100 MHz447-pin LGA/PGAMultiprocessor coherency
All models implement sub-micron fabrication for 1.2 million transistors and maintain full software compatibility with prior MIPS R2000/ processors, facilitating migration without code changes.

R4400 Enhancements

The R4400 was introduced in 1993 as a higher-performance variant of the R4000 core, targeting clock speeds from 100 MHz to 150 MHz and manufactured on a 0.6 μm process. This upgrade delivered a 60-80% performance increase over the baseline 50 MHz R4000 models, primarily through architectural refinements and elevated operating frequencies. A major enhancement was the expansion of on-chip caches to 16 KB for instructions and 16 KB for data, effectively doubling the 8 KB capacity of each in the original R4000 and improving hit rates for frequently accessed code and operands. The design also incorporated an internal (PLL) for clock generation, enabling the processor's internal pipeline clock (PClock) to operate at twice the external master clock , such as achieving 150 MHz internally from a 75 MHz external input. The R4400 maintained full pin compatibility with the R4000SC, allowing seamless integration into existing systems without board redesigns. However, these performance gains came at the cost of increased , typically ranging from 15 to 20 at full speed, depending on the supply voltage (3.3 V or 5 V).

Applications and Support

Notable Usage Cases

The R4000 microprocessor found prominent deployment in (SGI) workstations, particularly the and models, which revolutionized 3D graphics rendering and visualization from 1992 to 1994. These systems, leveraging the R4000's 64-bit , enabled real-time manipulation of complex geometric models and textures, supporting applications in , , and scientific simulation. For instance, the deskside workstation, introduced in 1992, delivered high-performance 3D graphics, making it a staple for Hollywood visual effects pipelines and workflows. In supercomputing contexts, the R4000 powered early clusters through SGI's scalable architectures, facilitating parallel processing for numerical simulations and data-intensive tasks in research institutions. These integrations contributed to advancements in fields like and molecular modeling during the mid-1990s. The processor also saw adoption in embedded and military applications, including and systems, where its scalar performance—up to 100 MIPS in board-level modules—supported acquisition and analysis in radiation-exposed environments like aircraft carriers. Radiation-tolerant configurations of the R4000 family were employed to handle from onboard , ensuring reliability in mission-critical operations. Additionally, the R4000 powered low-power embedded systems, such as Internet TVs for decoding and display processing, and Alteon Networks' routers for high-speed networking tasks in the mid-1990s. MIPS Technologies shipped over 1 million RISC processors in 1993, underscoring its dominant role in the high-end Unix segment and driving widespread adoption across professional computing ecosystems. The R4400 variant extended this legacy in high-speed deployments, such as upgraded SGI servers for demanding visualization tasks.

Compatible Chipsets

The R4000 family interfaced with external systems primarily through the , a 64-bit multiplexed address/data bus operating at up to 50 MHz, which required compatible to handle memory, I/O, and peripherals. One prominent commercially available was Acer's PICA (Performance-enhanced Input-output and CPU Architecture), an eight-chip set designed specifically for the R4000 and R4400PC processors. The PICA served as a northbridge equivalent, integrating support for a 128 KB or 256 KB second-level cache using specialized SRAM, up to 256 MB of main DRAM (in 64- or 128-bit widths with page-mode access for 200 MB/s peak bandwidth), and a 64-bit PICA bus at 25 MHz for high-speed memory and graphics interfaces. It also provided connectivity to EISA or ISA expansion buses via a 32-bit remote bus, enabling compatibility with standard PC peripherals while targeting systems. Graphics acceleration was facilitated through the PICA bus, allowing integration of existing 32-bit graphics chips with minimal additional logic. Silicon Graphics Inc. (SGI) developed custom tailored for visual computing workloads in their R4000-based workstations, such as the and series. The MC () chip acted as the core northbridge, managing interfaces between the R4000 CPU, up to 512 MB of 36-bit wide SIMM-based main memory, the GIO64 expansion bus (at 33 MHz with DMA engines for and I/O transfers), and EISA peripherals. Complementing the MC were supporting ASICs like the MUX for data multiplexing and parity handling, and the HPC3 for I/O control, which included DMA masters for efficient pipelines in applications. These custom designs optimized for SGI's GIO64 bus, emphasizing high-throughput DMA for visual tasks without native support for standard PC buses. Third-party vendors offered specialized implementations for embedded applications. LSI Logic produced the EZ4021, a synthesizable MIPS core based on the R4000 architecture (implementing MIPS III ISA), targeted at mid- to high-end embedded systems requiring 64-bit processing with integrated peripherals. These were often deployed on custom boards for networking and control tasks, leveraging the core's compatibility with R4000 bus protocols. Altera provided FPGA-based soft cores approximating R4000 functionality for prototyping and low-volume embedded designs, though these required additional logic for full . A key limitation across these chipsets was the absence of native PCI support, as the R4000 relied on buses like the MIPS or GIO64; peripheral expansion to PCI devices necessitated separate bridge chips, such as those from , to translate between bus domains and maintain compatibility with emerging standards.

References

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