TMS9918

The TMS9918 was packaged in a 40-pin dual in-line package (DIP). Power was provided as +5V on pin 33, V_CC, and ground on pin 12, V_SS. A quartz crystal running at 10.7386 MHz, three times the NTSC colorburst frequency, was connected across pins 40, XT1, and 39, XT2. Video output was on pin 36, COMVID, and input, if used, on pin 35, EXTV, with their connector's shield connection connected to ground.^[3]

In order to achieve the memory performance needed to support full-color operation, the system used a dedicated area of DRAM they referred to as VRAM. To operate this memory, the system included a separate set of pins forming an 8-bit address bus on pins 3 (AD7) through 10 (AD0) and an 8-bit data bus on pins 25 (RD7) through 32 (RD0), supported by a read/write control on pin 11, and RAS and CAS on pins 1 and 2.^[3]

Communications with the host computer were through a separate 8-bit data bus on pins 17 through 24, D7 to D0. Pin 13, MODE, controls whether the data on that bus is an address or data. To write to the TMS9918, the CPU first sets the mode and writes data to an internal address register, then writes the data to the bus and changes the mode to cause the data to be deposited into that address. After the data byte is read, the TMS9918 increments the pointer in the address register, allowing a series of bytes to be written in succession.^[4]

The TMS9918 logically arranges graphics in a number of layers, 32 sprite layers on top, a graphics or text layer, a "backdrop" with a single solid color filling the screen, and finally an external video layer. The backdrop plane is slightly larger than the others, so it completely fills the screen. The system uses a 15-color palette, along with color 0 which is transparent. At any pixel location on the screen, the system sees if a particular object is in that location, and whether or not it is set to transparent. If it is transparent it looks at the next object, and so on, until it reaches the external video layer (which is often not used).^[5] The following descriptions are ordered in this same fashion.

A key feature of the 9918 series was its powerful sprite support. It used a series of 8 bytes in VRAM to store patterns for 8 by 8 pixel sprites, one byte for each line of 8 pixels. It also had a second mode with 16 by 16 pixel sprites, 2 bytes per row and 16 rows.^[6] Additionally, either size of sprite could be magnified two times to make the spites larger on the screen. The pattern data for the sprites, in 8 or 32 byte long entries, was held in a block of memory known as the sprite generator table (SGT).^[7]

In addition to the 8 or 32 byte long entries holding the patterns, there was a separate sprite attribute table (SAT) that defined how the data was interpreted and displayed. This included 8-bit values for the horizontal and vertical position of the sprite, a pointer to the start of the data for that sprite in the SGT (which they called the name), and a color code in the lower four bits, for a total of 4 bytes per sprite for a total of 128 bytes in the SAT.^[6]

To determine what color to display at any given pixel on the screen, the system looked to see which sprites were visible at that location, and then searched down the patterns until it found the first one that held a 1 in that location, then drew the color found in the SAT at that pixel. This caused the sprites to be displayed in order, such that lower numbered sprites appeared on top of higher numbered ones. That meant, for instance, that sprite 0 always appeared on top. If there was no sprite on the screen at that location with a 1, that pixel was transparent, and the background graphics would be displayed instead.^[8]

As the sprites were drawn in order, it is sometimes necessary to change that order to produce the desired layering effects. This is the purpose of the "name" field entries in the SAT. For instance, if one wants to change the display so sprite 10 appears in front of 5, the values in the name field entries of the two can be swapped, avoiding the need to move the pattern data. Through careful arrangement of the sprite ordering, the system can easily produce pseudo-3D and parallax scrolling effects.^[9]

Due to performance issues, only four sprites can be displayed on any one scan line. If more are specified on a given line, they will simply not be displayed. The VDP has a status register that reports the number of the first sprite that had to be dropped. It is up to the programmer to design their system to ensure this limit is not reached. One trick to emulate more sprites on a line can be achieved by changing the priorities by swapping the name values every other frame so that one set of four is displayed on one frame and then another on the next. This allows up to eight sprites on a line, but results in noticeable flickering.

The sprite collision flag is set when non-zero pattern bits of two sprites coincide, even if either sprite has transparent colour. The VDP does not indicate which sprites have collided, simply that at least two have done so. This is normally used to trigger more advanced collision detection routines inside the software, which can then determine the exact location of the collision and act upon it.

The graphics of the 9918 were based on an underlying 256 wide by 192 high pixel layout.^[5] These numbers are typical for systems of the era which used analog video signals for output in a progressive scan display. This is close to the maximum resolution achieved on television sets of the era, which was around 320 by 240, due to the complexity of the NTSC radio-frequency signals.^[a]

There were four ways the graphics layer could be used:

Mode 0, or Text Mode, broke the screen into a 40 by 24 layout of "blocks", each 6 pixels wide and 8 high. Each block could hold a value from 0 to 255, normally representing an expanded ASCII character set. The patterns for each of the 256 characters was stored in VRAM and could be changed by loading the VRAM values using the CPU. Each line of the characters was defined as a series of "on" or "off" pixels stored in one byte per line, and 8 bytes per character. Because the blocks were 6 by 8 on the screen, it was up to the designer to lay out the characters in a 5 by 7 grid to leave space between them. The color for the "on" and "off" bits in the patterns could be any of the 15 colors available, and stored in VRAM.^[3]

Mode 1, or Graphics I, was essentially a modification of Text Mode that broke the screen into a 32 by 24 layout, so that each block was 8 by 8 pixels instead of 6 by 8. The pattern for any given pixel on the screen was looked up from the same 256-entry table of bit patterns as the one holding characters in Text Mode. As there were 768 possible locations and only 256 possible patterns, this mode was limited in the sorts of displays it could produce. Graphics I also added a separate section of VRAM that held the color values for the on and off pixels for any given block, with 768 entries. This meant every block of 8 by 8 pixels could have its own two colors, but the pixels within any block all had to be the same.^[7] This is not an uncommon solution for the era, and leads to a well-known problem known as attribute clash when it is not possible to choose colors that to not result in the edges of the cells being visible.

Mode 2, or Graphics II, was a further modification of Graphics I, allowing separate patterns for all 768 blocks, as well as separate color settings for each line within the blocks. This meant any block could use all 15 colors, although only two per line. This display allows any image to be drawn and more colors to be displayed, producing a display that is pixel-addressable and suitable for high-resolution drawing of arbitrary images. The cost is that it requires 32 color entries for each of the 192 lines, as well as an extended pattern map with 768 separate entries, increasing the VRAM needed to hold all of the data to about 12 KB.^[10]

Mode 3, or Multicolor Mode, broke the screen into 64 by 48 blocks, for a total of 3072 blocks. There were no patterns in this mode, the entire cell was either on or off. There was a color table entry for each block, so every block could select its own color. This produced a low-resolution but high-color display using less than 3 KB of VRAM.^[11]

One limitation of the system is that it did not include hardware fine scrolling support, and could only scroll along cell boundaries, normally 8 lines high. Scrolling was accomplished by moving the pattern already stored in VRAM and then adding data for the new line or column, which took some time to perform. Additionally, as all of the graphics modes were essentially character modes with custom characters in each cell, patterns that spanned cells, like lines or circles, had to calculate the pixels for each line of any given cell and upload those values into the character sets.

Technically, mode 2 is a character mode with a colorful character set. The screen is horizontally divided into three 256×64 pixel areas, each of which gets its own character set. By sequentially printing the characters 0 through 255 in all three areas, the program can simulate a graphics mode where each pixel can be set individually. However, the resulting framebuffer is non-linear.

The program can also use three identical character sets, and then deal with the screen like a text mode with a colorful character set. Background patterns and sprites then consist of colorful characters. This was commonly used in games, because only 32×24 bytes would have to be moved to fill and scroll the entire screen.

The challenge of using TMS9918 mode 2 was that every 8×1 pixel area could have only two colors, foreground and background. They could be freely picked out of the 16 color palette, but for each 8×1 area, only two colors could exist. When rendering a straight line diagonally, one easily could exceed the maximum 2 colors per 8×1 area and end up with "color spill".

Texas Instruments originally only documented the four modes listed above. However, the bit that enables mode 2 is actually a modifier bit for the other modes. Enabling it does three things:^[12]

1. Expands the color table size to hold entries for each cell.
2. Divides the screen horizontally into thirds.
3. Changes two address bits of the pattern and color tables into mask bits, which controls whether each third of the screen has its own pattern and color table (mode 2) or not (mode 1).

By toggling this bit in code, three additional modes are possible. Note that although genuine TMS9918A chips support these modes, clones and emulators may not.

• Mode 0 (Text) + Mode 2 (Graphic 2): Known as Bitmap Text Mode. This mode allows for two-color bitmap images, with no color table. This saves memory, at the expense of a slightly reduced horizontal resolution (text mode has a horizontal resolution of 240 pixels instead of 256 pixels like the graphic modes do).
• Mode 1 (Graphic 1) + Mode 2 (Graphic 2): Known as Half-Bitmap Mode. Texas Instruments actually documented this "undocumented" screen mode in their manual titled "Video Display Processors Programmers Guide SPPU004".^[13] In section 8.4.2, "Playing Games with VRAM Addressing",^[13] they discuss how this mode combines the memory savings of mode 1 with the color detail of mode 2. However, as they go on to say this mode limits the number of sprites that can be displayed to 8 instead of 32. Therefore, the term "undocumented" used to describe this mode is a misnomer. However, because this manual was not widely known, this mode is generally considered to be one of the undocumented modes. Generally, the only reason to use this mode over Mode 2 is to reduce memory consumption.
• Mode 3 (Multicolor) + Mode 2 (Graphic 2): Known as Bitmap Multicolor Mode. This mode is more of a novelty, as it offers nothing beyond what the standard Multicolor mode can already do.

Another key feature of the 9918 series was its ability to read an external video source and pass that signal through to the output assuming all of the objects above it are transparent. This allows the system to produce graphics which could then be overlaid on an analog source like a video camera or videotape. To make sure the two displays line up properly, the clock from the external source needs to be fed in as well, replacing the clock signal that would normally be generated by a quartz crystal. Some system to match the output strength of the input signal to the output also needs to be provided so one signal does not overwhelm the other.^[14]

The TMS9918 family chips used a composite video palette. Colors were generated based on a combination of luminance and chrominance values for the TMS9918A and Y, and R-Y (Pr) and B-Y (Pb)values are for the TMS9928A/9929A.^[15]

The TMS9918 has a fixed 16-color palette, composed of 15 displayed colors and a "transparent" color, color 0.

• When "transparent" is used for sprites, it will show the graphics plane.
• When "transparent" is used for the text/graphics plane, it will show the backdrop.
• When "transparent" is used for the backdrop, it will show the external video signal (if enabled) otherwise black.

According to "Table 2.3 - Color Assignments" on the datasheet outputs levels are the following:^[15]

Notes: Colors are merely illustrative, using automated YPbPr to sRGB conversion assuming SMPTE C colorimetry - see the next section for alternate color conversions.

All of the ICs in this family are usually referred to by the TMS9918 name, sometimes with an "A" postfix. The "A" indicates a second version of the chip which added new features, most prominently the addition of a bitmap mode (Graphic II).

The key features of this chip are, as highlighted in a 1980 presentation by Karl Guttag (one of the designers):^[1]

• 256 by 192 full color pixels per screen
• 15 different colors and/or shades
• Non-interlaced color composite video output
• Direct wiring to RAS/CAS type dynamic RAMs
• Automatic refresh of dynamic RAMs
• General 8-bit memory mapped type CPU interface
• CPU accesses RAM via VDP (no need for DMA)
• 32 dynamic characters per screen
• Thirty-two 8×8 patterns per row, 24 rows per screen
• Text mode with forty 6×8 patterns per row
• Multicolor mode with 64 by 48 memory mappable color squares
• External video input and control
• Single supply +5 volt operation
• Standard N-Channel silicon gate technology

The TMS9918 was only used in the TI-99/4; the TI-99/4A and the other computers had the A version VDC.

The TMS9918A and TMS9928A output a 60 Hz video signal, while the TMS9929A outputs 50 Hz. The difference between "1" and the "2" in "TMS9918A" and "TMS9928A" is that the "1" version outputs composite NTSC video, while the "2" versions (including the TMS9929A) outputs analog Y luminance and R-Y and B-Y colour difference signals. The need for the latter was predominant in the 50 Hz world, including Europe, due to the different video signal standards PAL and SECAM. It was more cost-effective to output Y, R-Y and B-Y and encode them into PAL or SECAM in the RF modulator, than to try to have a different console for every different color standard. The "1" version also features an external composite video input which made it a handy chip to use in video "titlers" that could overlay text or graphics on video, while the "2" version does not.

The original variants of the TMS9918 were depletion-load NMOS and manufactured on a 4.5 μm process; it was one of the first depletion load NMOS chips Texas Instruments manufactured in contrast to the TMS9900 microprocessor which used the older enhancement load NMOS process that required three supply voltages. Due to the large die size and relatively high internal speed, the TMS9918 ran warm enough to necessitate a heat sink; some devices such as the Taiwanese DINA console (a hybrid Colecovision/SG-1000) neglected to install sinks and suffered from malfunctions of the chip. By 1983 Texas Instruments had shrunk the die size to 3 μm which ran cooler and no longer required a sink; MSX machines and the Sega SG-1000 used the newer 3 μm TMS9918 while most Colecovisions had the original 4.5 μm variant (the final run of the consoles produced in 1985 had the newer model TMS9918).

A later variant of the TMS9918 series chips, the TMS9118, TMS9128, and TMS9129, were released in the mid-late 1980s, but were never very popular. The function of one pin is changed, and the mapping of the video memory allows two 16K×4-bit chips to be used instead of the eight 16K×1-bit chips the TMS99xx needs. Otherwise the chips are completely identical to the TMS9918A, TMS9928A and TMS9929A respectively.

^{[original research?]}

Converting Y, R-Y and B-Y to RGB requires considering how Y originated:

 Y = R * 0.30 + G * 0.59 + B * 0.11

This leads to the following formulas:

 R = R-Y + Y
 B = B-Y + Y
 G = (Y - 0.30 * R - 0.11 * B) / 0.59

But for all colors that have no chrominance - thus black, gray and white - R-Y and B-Y are not 0% but all have an offset of 47%. So this offset has to be subtracted from all R-Y and B-Y values at first. Due to the fact that in practice this one step will never be done alone, it's no problem that some results will be negative:

Next comes the conversion to RGB. All results must be in the range from 0% to 100%:

The erroneous value of 113% for R of color "light red" might seem to come from a typo within the datasheet and there R-Y must not be greater than 80%. But measuring the output signals of the chip with an oscilloscope shows that all values in the table are correct. So the error is inside the chip and drives the red signal into saturation. For this reason this value is to be corrected to 100%.

Up to that time only cathode ray tubes had been available for computer monitors as well as for televisions, and that these CRTs had a gamma. The TMS9918 series chips had been designed to work with televisions and their CRTs had a gamma of 1.6 (remark: CRTs of Macintosh monitors had 1.8 and the CRTs of PC monitors had 2.2). Digital flat panels do not have gamma. For this reason the colors of the TMS9918 look somewhat pale here as in the first table above. The below table uses the gamma-corrected values, which are (written in hexadecimal):

The used steps are: Round all values to two decimal places, then raise to the power of 1.6 for gamma correction and finally transform the range of values from 0...100 to 0...255.

• Video RAM: direct wiring to 4, 8, or 16 KB
• Text modes: 40 × 24 and 32 × 24
• Resolution: 256 × 192
• Colours: 15 colours + transparent
• Sprites: 32, 1 colour, max 4 per horizontal line

Texas Instruments' TMS9918A was succeeded by the Yamaha V9938, which added additional bitmap modes, more colorful sprites, a vertical full-screen scroll register, vertical and horizontal offset registers, a hardware blitter and a customizable palette. The V9938 was designed for the MSX2 standard of computers, and later used in a third-party upgrade to the TI-99/4A: the Geneve 9640 "computer-on-a-card".

The V9938, in turn, was succeeded by the V9958 which added some additional high-colour modes and a horizontal two-page scroll register. These chips were used in the MSX2+/turboR systems.

Toshiba made a clone called the T6950 which does not support the undocumented pattern / color table masking feature in graphics 2 mode.^{[16][better source needed]} Later, Toshiba released the T7937A MSX-Engine with a built-in VDP with working masking features. Both VDPs by Toshiba feature a palette which is slightly different (more vivid colors) from the TI VDPs.

The VDP of the Master System game console is an evolution of the TMS9918. This was further evolved into the VDP of the Genesis/Mega Drive game console, which replaces most of the graphics modes from the Master System VDP with more capable versions.

• TMS34010, a 1986 microprocessor with dedicated graphics instructions
• Atari 8-bit computers have comparable graphics hardware introduced the same year
• Motorola 6845, a display controller widely used in 8-bit computers
• Motorola 6847
• Yamaha V9938
• Yamaha V9958
• List of 8-bit computer hardware graphics