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Semiconductor device fabrication

MOSFET scaling (process nodes)
20 μm – 1968 10 μm – 1971 6 μm – 1974 3 μm – 1977 1.5 μm – 1981 1 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 90 nm – 2003 65 nm – 2005 45 nm – 2007 32 nm – 2009 28 nm – 2010 22 nm – 2012 14 nm – 2014 10 nm – 2016 7 nm – 2018 5 nm – 2020 3 nm – 2022 2 nm – 2025
Future 1 nm ~ 2027
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
v t e

The 350 nanometer process (350 nm process) is a level of semiconductor process technology that was reached in the 1995–1996 timeframe by leading semiconductor companies like Intel and IBM.

Example processes

[edit]

SGS-Thomson 5LM^[1]

Products featuring 350 nm manufacturing process

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MTI VR4300i (1995), used in the Nintendo 64 game console.
Intel Pentium (P54CS, 1995), Pentium Pro (1995) and initial Pentium II CPUs (Klamath, 1997).
AMD K5 (1996) and original AMD K6 (Model 6, 1997) CPUs.
МЦСТ-R150 (2001).
Parallax Propeller (2006), 8 core microcontroller.^[2]
Atmel ATmega328, used in the Arduino UNO.^[3]^[4]
Nvidia RIVA 128 (1997) GPU^[1]

References

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^ ^a ^b Logan, Andrew (1997-09-10). "RIVA 128 gains support as preferred Direct3D developer platform press release". NVIDIA Home. Archived from the original on 1998-06-13. Retrieved 2023-12-03.
^ "Propeller I semiconductor process technology? Is it 350nm or 180nm?". Parallax Forums. Retrieved 2015-09-13.{{cite web}}: CS1 maint: deprecated archival service (link)
^ Petryk, Dmytro; Dyka, Zoya (2018). "Optical Fault Injections: a Setup Comparison". S2CID 198917285. {{cite journal}}: Cite journal requires |journal= (help)
^ Guillen, Oscar; Gruber, Michael; De Santis, Fabrizio (2017). "Low-Cost Setup for Localized Semi-invasive Optical Fault Injection Attacks: How Low Can We Go?". Constructive Side-Channel Analysis and Secure Design. Lecture Notes in Computer Science. Vol. 10348. pp. 207–222. doi:10.1007/978-3-319-64647-3_13. ISBN 978-3-319-64646-6.

Preceded by 600 nm	CMOS manufacturing processes	Succeeded by 250 nm

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350 nm process

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The 350 nm process, also known as the 0.35 μm process, is a semiconductor manufacturing technology that defines the minimum half-pitch feature size for fabricating integrated circuits at 350 nanometers, enabling denser transistor packing, higher clock speeds, and reduced power consumption relative to prior generations such as the 500 nm or 600 nm nodes.^[1] This process node marked a key milestone in CMOS (complementary metal-oxide-semiconductor) lithography, utilizing deep ultraviolet (DUV) light sources typically at wavelengths around 248 nm for patterning, and it supported the integration of multiple metal layers (up to 4–6) along with features like shallow trench isolation and silicide contacts to enhance performance.^[1] Commercial high-volume production ramped up in 1995, following a historical scaling trend of approximately 0.7× linear dimensions every two years, as outlined in industry roadmaps.^[1] Intel pioneered the adoption of the 350 nm process for microprocessors, announcing the first 120 MHz Pentium CPU on this node in March 1995, which became the first commercial x86 processor to achieve such scaling and set the stage for subsequent enhancements like the Pentium MMX in 1997, built on an enhanced 0.35 μm CMOS process with MMX instructions for multimedia acceleration.^[2]^[3] Other notable early implementations included Sony's 16 Mb SRAM chip in 1994 and NEC's VR4300 MIPS processor for the Nintendo 64 console in 1995, demonstrating the node's versatility for memory, logic, and embedded applications. By the late 1990s, the process was widely employed across the industry for high-performance computing, with companies like DEC and Hitachi producing 350 nm microprocessors, before being succeeded by the 250 nm node around 1998–1999. Despite the shift to finer nodes for cutting-edge digital logic, the 350 nm process remains relevant today for cost-sensitive, mature applications requiring analog, mixed-signal, power management, or sensor integration, owing to its reliability, low defect rates, and support for high-voltage (up to 100 V) and non-volatile memory options.^[4] Foundry services like X-FAB's modular 350 nm family (including XH035 for automotive-grade sensors up to 125°C and XA035 for high-temperature operation up to 175°C) incorporate specialized features such as ultra-low-noise 3.3 V PMOS transistors, high-sensitivity photodiodes, and EEPROM, catering to robust optoelectronics, data storage, and industrial interfaces.^[4] This enduring utility underscores the 350 nm process's role in bridging legacy and specialized semiconductor ecosystems, even as global efforts—such as Russia's completion in 2025 of domestic 350 nm lithography tools, with first commercial delivery in September 2025—highlight its accessibility for emerging national industries amid supply chain constraints.^[5]

History and Development

Timeline of Introduction

The development of the 350 nm semiconductor process began with initial research and prototyping efforts in the early 1990s, building on the preceding 600 nm node that had entered production around 1993-1994.^[6]^[1] These activities focused on scaling down feature sizes to improve transistor density and performance, guided by emerging industry roadmaps that established a roughly two-year cycle for node advancements.^[1] An early milestone was Sony's 16 Mbit SRAM chip implemented on the 0.35 μm process in 1994. By late 1995, the process achieved commercial viability, with the first integrated circuit manufacturing starting that year, marking a significant step in high-volume semiconductor production.^[7] A key milestone was Intel's launch of its CMOS-6 process in the first quarter of 1995, which utilized a 0.35-micron gate length and enabled broader compatibility with existing designs.^[8] Parallel developments at IBM during 1995-1996 included advancements in 0.35-micron CMOS technology, such as sample availability for high-speed processors, contributing to the node's maturation.^[9] Widespread adoption occurred between 1996 and 1997, as major foundries like TSMC scaled up production, with TSMC entering volume manufacturing of 0.35-micron SRAM in June 1996 ahead of schedule.^[10] The process began phasing out in 1998-1999, supplanted by the emerging 250 nm node as part of the continued roadmap progression.^[7]^[1]

Key Companies and Innovations

Intel led the development of the 350 nm process through its CMOS-6 technology, introduced commercially in 1995, which featured advanced salicide using titanium disilicide (TiSi₂) to significantly reduce source/drain and gate resistances, enabling higher transistor performance and lower power consumption.^[11] This innovation addressed key challenges in scaling CMOS devices by minimizing parasitic resistances while maintaining reliability in sub-micron features.^[11] IBM contributed through extensive collaborative efforts, including joint ventures such as MiCRUS with Cirrus Logic established in 1994 and operational from 1995, which focused on CMOS scaling to 350 nm and achieved early yield improvements through shared fabrication expertise and process optimizations.^[12] These partnerships facilitated broader adoption of 350 nm CMOS by integrating bipolar and CMOS technologies, enhancing overall manufacturing efficiency and device density.^[12] TSMC played a pivotal role as a pure-play foundry, launching its 0.35 μm CMOS process in volume production in 1996, which democratized access to advanced 350 nm technology for non-integrated device manufacturers (non-IDM) by offering flexible, high-volume manufacturing without in-house design constraints.^[10] This model spurred innovation across the industry by providing cost-effective scaling options and rapid prototyping for diverse applications.^[10] Japanese firms, particularly NEC, advanced graphics-specific optimizations at the 350 nm node, leveraging their 0.35 μm process for high-performance embedded graphics processors, such as the Reality Co-Processor in the Nintendo 64, which integrated vector units and texture mapping with reduced latency through customized interconnects and transistor layouts.^[13] Other Japanese companies like Hitachi contributed to similar refinements, emphasizing low-power graphics ICs suitable for consumer electronics.^[7] Key patents and innovations further standardized the 350 nm process. Industry collaborations through SEMI developed design rules for 350 nm, promoting interoperability in lithography and interconnect standards to accelerate adoption across global fabs.^[1]

Technical Aspects

Lithography and Feature Sizes

The 350 nm process relied on i-line photolithography, utilizing ultraviolet light at a wavelength of 365 nm emitted by mercury arc lamps as the primary illumination source for patterning features onto photoresist-coated wafers.^[14] This wavelength, part of the mercury spectrum's i-line (from ionized mercury), enabled projection systems such as steppers to achieve the necessary resolution for sub-micron features through reduction optics, typically with a 5:1 or 4:1 mask-to-wafer reduction ratio.^[15] The process involved coating wafers with photoresist, exposing them through a photomask aligned via the stepper, and developing the resist to transfer the pattern for subsequent etching or deposition steps.^[16] Key dimensional parameters defined the node's capabilities, with the drawn gate length (L_drawn) specified at 0.35 µm to represent the nominal transistor channel length as laid out in the design.^[17] However, due to effects like lateral dopant diffusion during implantation and thermal processing, the effective channel length (L_eff) was typically reduced to around 0.25 µm, impacting short-channel effects and device performance.^[8] Minimum feature sizes included metal pitches ranging from 0.7 to 1.0 µm, allowing for interconnect routing while maintaining manufacturability, and contact/via dimensions of approximately 0.4 µm to ensure reliable electrical connections without excessive resistance.^[17] These dimensions were patterned using steppers with numerical apertures (NA) of 0.5 to 0.6, pushing the limits of optical imaging for the era.^[18] The fundamental resolution limit followed the Rayleigh criterion, expressed as

\text{CD} = k_1 \frac{\lambda}{\text{NA}}

where CD is the critical dimension (e.g., minimum resolvable feature), λ = 365 nm, NA ≈ 0.5–0.6, and k₁ (a process factor accounting for mask quality, resist response, and illumination) ranged from 0.6 to 0.8.^[19] This equation highlights how the 350 nm node balanced wavelength and optics to achieve CDs near 0.35 µm, though practical yields required optimizations like off-axis illumination to improve contrast.^[20] Significant challenges arose from optical proximity effects (OPE), where diffraction from adjacent features caused linewidth variations and reduced image fidelity, particularly in dense layouts.^[21] To mitigate these, optical proximity correction (OPC) techniques adjusted mask patterns to compensate for distortions, while in high-density regions, phase-shift masks (PSMs)—such as attenuated or rim-type designs—were introduced to create constructive interference and enhance resolution by up to 20–30% for features like 0.35 µm contacts.^[22] These advancements, often applied selectively to critical layers, enabled reliable patterning despite the diffraction-limited nature of i-line systems.^[23]

Materials and Fabrication Steps

The 350 nm CMOS process primarily utilized a gate stack consisting of a thin thermal silicon dioxide (SiO₂) layer as the gate dielectric, with a typical thickness of approximately 7 nm, topped by polycrystalline silicon (polysilicon) gates.^[17] Later implementations incorporated cobalt disilicide (CoSi₂) as a self-aligned silicide (salicide) for source/drain and gate contacts to reduce sheet resistance and improve performance.^[7] Isolation and inter-layer dielectrics were predominantly SiO₂, though initial explorations of low-k materials were limited due to integration challenges and compatibility issues with the thermal budget.^[24] Interconnects employed aluminum (Al) metallization layers, typically sputter-deposited, while tungsten (W) plugs filled vias to connect multi-level metal layers and prevent electromigration.^[24] Fabrication began with wafer preparation using 200 mm p-type silicon substrates, followed by thermal oxidation to grow the field oxide for device isolation via the local oxidation of silicon (LOCOS) process.^[17] Doping for n-wells and p-wells was achieved through ion implantation, with subsequent source/drain extensions and pockets also formed by implantation and rapid thermal annealing (RTA). The gate dielectric was grown via dry thermal oxidation to the target thickness, after which low-pressure chemical vapor deposition (LPCVD) deposited the polysilicon gate layer, patterned using reactive ion etching (RIE).^[25] Sidewall spacers were formed by depositing and anisotropically etching SiO₂ or Si₃N₄, followed by self-aligned source/drain implantation. Metallization involved sputtering Al for interconnects, with chemical vapor deposition (CVD) of W for via plugs after barrier layer deposition (e.g., TiN). The CoSi₂ salicide process entailed sputtering cobalt, followed by two RTA steps at around 500–700°C to form CoSi and then CoSi₂, with selective etching to remove unreacted metal.^[26] Key yield factors in the 350 nm process included defect densities typically ranging from 1 to 5 per cm², influenced by particle contamination and lithography overlay errors, which necessitated cleanroom protocols and alignment tolerances below 100 nm.^[1] Thermal budget constraints were critical during silicide formation, as excessive temperatures above 800°C could degrade the thin gate oxide or cause dopant redistribution, limiting process windows to RTA durations of seconds.^[26]

Applications

Microprocessors and CPUs

The Intel Pentium P54CS, introduced in 1995, represented a key advancement in personal computing processors fabricated using a 0.35 µm CMOS process.^[2] Operating at clock speeds from 75 MHz to 200 MHz, it powered early Pentium-based PCs with a superscalar architecture featuring two integer pipelines and a floating-point unit, enabling improved performance for multimedia and general applications. The chip contained approximately 3.3 million transistors on a die size of about 90 mm², which contributed to higher yields and cost efficiency compared to prior generations.^[2] The Intel Pentium Pro, launched in 1995 and targeted at servers and workstations, employed a dual-cavity design that integrated the processor core with L2 cache dies for enhanced data access speeds.^[27] Clocked at 133–200 MHz, it introduced out-of-order execution and a deeper pipeline, significantly boosting integer and floating-point performance for enterprise workloads over the original Pentium. Early variants used a 0.6 µm process for the core, while later cache integrations leveraged 0.35 µm technology to support higher densities and speeds.^[27] This architecture laid groundwork for future x86 designs, emphasizing scalability in multi-user environments. The initial Intel Pentium II, codenamed Klamath and released in 1997, utilized a 0.35 µm process in a slot-based package that housed the CPU die and separate L2 cache for mobile and desktop use. Available at 233–300 MHz with MMX extensions for multimedia acceleration, it delivered up to 7.5 million transistors and improved branch prediction, offering about 20–30% better performance than the Pentium Pro at equivalent clocks. Klamath served as a transitional product, with subsequent Deschutes variants shrinking to 0.25 µm for further efficiency gains. The MTI VR4300i, a MIPS R4300i-based processor developed in 1995 for embedded applications, operated at 93.75 MHz on a 0.35 µm process and powered the Nintendo 64 console.^[28] Its embedded core included a 64-bit RISC architecture with an integrated floating-point unit, enabling efficient handling of 3D graphics and game logic through vector extensions.^[29] This design prioritized low power and compact integration, achieving reliable performance in resource-constrained gaming hardware without compromising on instruction throughput. The AMD K6, introduced in 1997, competed in the x86 market with clock speeds of 166–300 MHz using a 0.35 µm process and SuperSocket 7 compatibility for upgradeable PC systems.^[30] Featuring 8.8 million transistors and 3DNow! extensions for enhanced 3D rendering, it incorporated a superscalar pipeline with MMX support, providing competitive integer performance against Intel's Pentium II at lower costs.^[30] The architecture emphasized multimedia acceleration, making it a popular choice for budget-oriented desktops during the late 1990s transition to faster nodes.

Graphics and Specialized ICs

The NVIDIA RIVA 128, released in 1997, marked NVIDIA's entry into consumer 3D graphics acceleration as the company's first dedicated GPU supporting DirectX 5.0 for gaming applications. Fabricated on a 350 nm process by STMicroelectronics, it featured a core clock speed of 100 MHz and approximately 3.5 million transistors, enabling efficient 2D/3D rendering with hardware texture mapping and a 128-bit memory interface.^[31]^[32] This chip's integrated design offloaded significant processing from the host CPU, supporting resolutions up to 1600x1200 in 2D and accelerating early PC gaming titles through its floating-point setup engine. In the realm of console graphics, the Silicon Graphics (SGI) Reality Coprocessor (RCP), introduced in 1996 for the Nintendo 64, represented a pioneering integration of graphics and audio processing on 350 nm technology manufactured by NEC. Operating at 62.5 MHz, the RCP combined the Reality Signal Processor (RSP) for vector-based geometry transformations and the Reality Display Processor (RDP) for rasterization and texturing, delivering up to 100 million pixels per second in fill rate.^[33] This fixed-function architecture, with its microcode-programmable RSP enabling custom vector processing, powered the N64's distinctive 3D visuals while interfacing briefly with the system's MIPS-based CPU for overall pipeline efficiency.^[34] For specialized embedded applications, the Parallax Propeller P8X32A microcontroller, launched in 2006, utilized a 350 nm process to implement an 8-core architecture capable of 80 MHz operation across its symmetric multiprocessing cores. Designed for low-power scenarios such as sensor interfacing and real-time control, each core handled independent tasks via a shared hub, supporting applications in robotics and hobbyist projects with minimal external components.^[35] Its 350 nm fabrication allowed for robust 3.3V operation and high integration density in a 40-pin DIP package. Beyond graphics, the 350 nm process enabled early application-specific integrated circuits (ASICs) tailored for networking and telecommunications, including Ethernet controllers and analog-mixed-signal chips. These designs prioritized reliability and power efficiency over cutting-edge speed, facilitating widespread adoption in routers and modems during the process node's commercial peak.^[36]

Legacy and Modern Relevance

Transition to Smaller Nodes

The transition from the 350 nm process to the 250 nm node, introduced by major manufacturers between 1998 and 1999, represented a critical step in sustaining Moore's Law through enhanced scaling. A pivotal change was the adoption of copper interconnects in place of aluminum, driven by the need to combat electromigration failures as interconnect dimensions shrank below 0.5 μm; copper's higher electromigration resistance and lower resistivity enabled reliable signal propagation at increased current densities without excessive voiding or hillock formation. Complementing this, shallower source/drain junctions—typically reduced to depths of around 50-70 nm—were implemented to mitigate short-channel effects and improve junction integrity, further addressing electromigration risks in contact regions while boosting transistor drive currents.^[37]^[38]^[39] The 350 nm process laid essential groundwork for this shift, particularly through the established reliability of self-aligned silicide (salicide) contacts, such as titanium or cobalt disilicide, which provided low sheet resistance (around 3-5 Ω/sq) and thermal stability up to 800°C, ensuring robust source/drain and gate contacts during high-volume production. However, as gate lengths approached 0.25 μm, fundamental limitations in further gate scaling emerged, including velocity saturation, increased gate oxide tunneling, and diminishing returns on performance gains from dimensional reduction alone; these challenges spurred early research explorations into strained silicon channels in the late 1990s to enhance carrier mobility by 20-50% via lattice mismatch with underlying SiGe layers, offering a pathway to extend CMOS performance without aggressive oxide thinning.^[40]^[41] This node transition delivered substantial industry impacts, with transistor densities roughly doubling—from approximately 25,000-50,000 transistors/mm² in logic circuits at 350 nm to 50,000-100,000/mm² at 250 nm—driven by quadratic scaling benefits and optimized layout rules, enabling chips like early microprocessors to integrate millions more transistors on comparable die areas. While roadmap projections anticipated cost efficiencies from larger 300 mm wafers promising up to 2.5× area improvements over 200 mm substrates, high-volume 250 nm fabrication remained on 200 mm wafers, with 300 mm pilot lines emerging in the late 1990s but achieving broad adoption post-2000 for finer nodes.^[6] The International Technology Roadmap for Semiconductors (ITRS) 1997 outlined aggressive two-year cycles for node progression, projecting the 250 nm generation to follow the 350 nm by 1998 while emphasizing the necessity of shifting from i-line (365 nm) lithography—adequate for 350 nm features—to deep ultraviolet (DUV) at 248 nm for resolving critical dimensions below 300 nm with acceptable overlay and depth-of-focus margins. This lithography evolution, combined with resolution enhancement techniques like off-axis illumination, was deemed essential to maintain defect densities under 0.1/cm² and support the projected 30-50% performance gains per node.^[42]^[43]

Current and Emerging Uses

Despite the dominance of sub-100 nm process nodes in high-performance computing, the 350 nm process persists in legacy maintenance applications where long-term reliability, low risk of obsolescence, and established supply chains outweigh the need for cutting-edge performance. In industrial controls, such chips are employed in programmable logic controllers and monitoring systems for factories and utilities, leveraging their proven durability in harsh environments. Automotive electronic control units (ECUs) continue to incorporate 350 nm components for non-critical functions like basic engine management and sensor interfaces, as these nodes provide sufficient functionality with minimal susceptibility to supply disruptions. Military hardware, including avionics, radar systems, and communication modules, relies on 350 nm derivatives for their radiation tolerance and extended qualification lifecycles, ensuring operational continuity in defense platforms.^[44]^[45]^[46] Recent developments in geopolitically constrained markets have revitalized interest in 350 nm technology. In 2024-2025, Russia advanced domestic production capabilities amid Western sanctions limiting access to advanced equipment, culminating in the completion of a 350 nm lithography stepper by the Zelenograd Nanotechnology Center (ZNTC) in collaboration with Belarus-based Planar. This system supports 200 mm wafers and employs solid-state laser technology for patterning, enabling fabrication of mature-node integrated circuits for essential applications. The tool addresses immediate needs in Russia's semiconductor ecosystem, facilitating production for automotive, power management, and military integrated circuits without reliance on imported machinery. Orders for the stepper were reported shortly after its unveiling, and by September 2025, the first commercial delivery was reported, signaling initial adoption in sanctioned environments.^[47]^[48]^[49]^[50] Emerging applications in cost-sensitive sectors further underscore the 350 nm process's relevance. In developing regions, low-cost Internet of Things (IoT) sensors for agriculture and environmental monitoring utilize 350 nm chips due to their economical fabrication and adequate performance for basic data acquisition tasks. Medical devices, such as portable diagnostic tools and wearable health monitors prevalent in underserved markets, incorporate these nodes for simple analog-to-digital conversion and signal processing, prioritizing affordability over power efficiency. Radiation-hardened variants based on 350 nm silicon-on-insulator (SOI) processes are deployed in space applications, including satellite subsystems and deep-space probes, where they withstand cosmic radiation while meeting size and cost constraints for non-cutting-edge missions.^[51]^[52]^[53] Supply chain challenges persist for 350 nm production, centered on aging fabrication facilities and inherent inefficiencies compared to modern nodes. Reliance on older foundries, such as TSMC's early 200 mm wafer plants like Fabs 3, 5, and 6, sustains availability but exposes vulnerabilities to equipment obsolescence and geopolitical tensions. While production costs for 350 nm wafers remain approximately 10-20% of those for 3 nm equivalents—around $2,000-$4,000 per wafer versus $20,000—the higher power consumption of these larger-feature devices, often 5-10 times that of sub-10 nm nodes, limits their suitability for energy-constrained designs. These factors drive ongoing investments in mature-node resilience to support global demand in constrained sectors.^[54]^[55]^[56]

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350 nm process

350 nm process

350 nm process

Example processes

Products featuring 350 nm manufacturing process

References

350 nm process

History and Development

Timeline of Introduction

Key Companies and Innovations

Technical Aspects

Lithography and Feature Sizes

Materials and Fabrication Steps

Applications

Microprocessors and CPUs

Graphics and Specialized ICs

Legacy and Modern Relevance

Transition to Smaller Nodes

Current and Emerging Uses

References