Hubbry Logo
PhotomaskPhotomaskMain
Open search
Photomask
Community hub
Photomask
logo
8 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
Photomask
Photomask
Photomask
View on Wikipedia
from Wikipedia
A photomask. This photomask has 20 copies, also called layers, of the same circuit pattern or design.
A schematic illustration of a photomask (top) and an IC layer printed using it (bottom)

A photomask (also simply called a mask) is an opaque plate with transparent areas that allow light to shine through in a defined pattern. Photomasks are commonly used in photolithography for the production of integrated circuits (ICs or "chips") to produce a pattern on a thin wafer of material (usually silicon). In semiconductor manufacturing, a mask is sometimes called a reticle.[1][2]

In photolithography, several masks are used in turn, each one reproducing a layer of the completed design, and together known as a mask set. A curvilinear photomask has patterns with curves, which is a departure from conventional photomasks which only have patterns that are completely vertical or horizontal, known as manhattan geometry. These photomasks require special equipment to manufacture.[3]

History

[edit]

For IC production in the 1960s and early 1970s, an opaque rubylith film laminated onto a transparent mylar sheet was used. The design of one layer was cut into the rubylith, initially by hand on an illuminated drafting table (later by machine (plotter)) and the unwanted rubylith was peeled off by hand, forming the master image of that layer of the chip, often called "artwork". Increasingly complex and thus larger chips required larger and larger rubyliths, eventually even filling the wall of a room, and artworks were to be photographically reduced to produce photomasks (Eventually this whole process was replaced by the optical pattern generator to produce the master image). At this point the master image could be arrayed into a multi-chip image called a reticle. The reticle was originally a 10X larger image of a single chip.

The reticle was, by step-and-repeater photolithography and etching, used to produce a photomask with an image size the same as the final chip. The photomask might be used directly in the fab or be used as a master-photomask to produce the final actual working photomasks.

As feature size shrank, the only way to properly focus the image was to place it in direct contact with the wafer. These contact aligners often lifted some of the photoresist off the wafer and onto the photomask and it had to be cleaned or discarded. This drove the adoption of reverse master photomasks (see above), which were used to produce (with contact photolithography and etching) the needed many actual working photomasks. Later, projection photo-lithography meant photomask lifetime was indefinite. Still later direct-step-on-wafer stepper photo-lithography used reticles directly and ended the use of photomasks.

Photomask materials changed over time. Initially soda glass[4] was used with silver halide opacity. Later borosilicate[5] and then fused silica to control expansion, and chromium which has better opacity to ultraviolet light were introduced. The original pattern generators have since been replaced by electron beam lithography and laser-driven mask writer or maskless lithography systems which generate reticles directly from the original computerized design.

Overview

[edit]
See also: Photographic plate
A simulated photomask. The thicker features are the integrated circuit that is desired to be printed on the wafer. The thinner features are assists that do not print themselves but help the integrated circuit print better out-of-focus. The zig-zag appearance of the photomask is because optical proximity correction was applied to it to create a better print.

Lithographic photomasks are typically transparent fused silica plates covered with a pattern defined with a chromium (Cr) or Fe2O3 metal absorbing film.[6] Photomasks are used at wavelengths of 365 nm, 248 nm, and 193 nm. Photomasks have also been developed for other forms of radiation such as 157 nm, 13.5 nm (EUV), X-ray, electrons, and ions; but these require entirely new materials for the substrate and the pattern film.[6]

A set of photomasks, each defining a pattern layer in integrated circuit fabrication, is fed into a photolithography stepper or scanner, and individually selected for exposure. In multi-patterning techniques, a photomask would correspond to a subset of the layer pattern.

Historically in photolithography for the mass production of integrated circuit devices, there was a distinction between the term photoreticle or simply reticle, and the term photomask. In the case of a photomask, there is a one-to-one correspondence between the mask pattern and the wafer pattern. The mask covered the entire surface of the wafer which was exposed in its entirety in one shot. This was the standard for the 1:1 mask aligners that were succeeded by steppers and scanners with reduction optics.[7] As used in steppers and scanners which use image projection,[8] the reticle commonly contains only one copy, also called one layer of the designed VLSI circuit. (However, some photolithography fabrications utilize reticles with more than one layer placed side by side onto the same mask, used as copies to create several identical integrated circuits from one photomask). In modern usage, the terms reticle and photomask are synonymous.[9]

In a modern stepper or scanner, the pattern in the photomask is projected and shrunk by four or five times onto the wafer surface.[10] To achieve complete wafer coverage, the wafer is repeatedly "stepped" from position to position under the optical column or the stepper lens until full exposure of the wafer is achieved. A photomask with several copies of the integrated circuit design is used to reduce the number of steppings required to expose the entire wafer, thus increasing productivity.

Features 150 nm or below in size generally require phase-shifting to enhance the image quality to acceptable values. This can be achieved in many ways. The two most common methods are to use an attenuated phase-shifting background film on the mask to increase the contrast of small intensity peaks, or to etch the exposed quartz so that the edge between the etched and unetched areas can be used to image nearly zero intensity. In the second case, unwanted edges would need to be trimmed out with another exposure. The former method is attenuated phase-shifting, and is often considered a weak enhancement, requiring special illumination for the most enhancement, while the latter method is known as alternating-aperture phase-shifting, and is the most popular strong enhancement technique.

As leading-edge semiconductor features shrink, photomask features that are 4× larger must inevitably shrink as well. This could pose challenges since the absorber film will need to become thinner, and hence less opaque.[11] A 2005 study by IMEC found that thinner absorbers degrade image contrast and therefore contribute to line-edge roughness, using state-of-the-art photolithography tools.[12] One possibility is to eliminate absorbers altogether and use "chromeless" masks, relying solely on phase-shifting for imaging.[13][14]

The emergence of immersion lithography has a strong impact on photomask requirements. The commonly used attenuated phase-shifting mask is more sensitive to the higher incidence angles applied in "hyper-NA" lithography, due to the longer optical path through the patterned film.[15] During manufacturing, inspection using a special form of microscopy called CD-SEM (Critical-Dimension Scanning Electron Microscopy) is used to measure critical dimensions on photomasks which are the dimensions of the patterns on a photomask.[16]

EUV lithography

[edit]

EUV photomasks work by reflecting light,[17] which is achieved by using multiple alternating layers of molybdenum and silicon.

Mask error enhancement factor (MEEF)

[edit]

Leading-edge photomasks (pre-corrected) images of the final chip patterns are magnified by four times. This magnification factor has been a key benefit in reducing pattern sensitivity to imaging errors. However, as features continue to shrink, two trends come into play: the first is that the mask error factor begins to exceed one, i.e., the dimension error on the wafer may be more than 1/4 the dimension error on the mask,[18] and the second is that the mask feature is becoming smaller, and the dimension tolerance is approaching a few nanometers. For example, a 25 nm wafer pattern should correspond to a 100 nm mask pattern, but the wafer tolerance could be 1.25 nm (5% spec), which translates into 5 nm on the photomask. The variation of electron beam scattering in directly writing the photomask pattern can easily well exceed this.[19][20]

Pellicles

[edit]

The term "pellicle" is used to mean "film", "thin film", or "membrane." Beginning in the 1960s, thin film stretched on a metal frame, also known as a "pellicle", was used as a beam splitter for optical instruments. It has been used in a number of instruments to split a beam of light without causing an optical path shift due to its small film thickness. In 1978, Shea et al. at IBM patented a process to use the "pellicle" as a dust cover to protect a photomask or reticle. In the context of this entry, "pellicle" means "thin film dust cover to protect a photomask".

Particle contamination can be a significant problem in semiconductor manufacturing. A photomask is protected from particles by a pellicle – a thin transparent film stretched over a frame that is glued over one side of the photomask. The pellicle is far enough away from the mask patterns so that moderate-to-small sized particles that land on the pellicle will be too far out of focus to print. Although they are designed to keep particles away, pellicles become a part of the imaging system and their optical properties need to be taken into account. Pellicles material are nitrocellulose and made for various transmission wavelengths. Current pellicles are made from polysilicon, and companies are exploring other materials for high-NA EUV, such as CNT (carbon nanotubes)[21][22][23], and future chip making processes.[24][25]

Pellicle mounting machine MLI

Leading commercial photomask manufacturers

[edit]
Main article: Mask shop

The SPIE Annual Conference, Photomask Technology reports the SEMATECH Mask Industry Assessment which includes current industry analysis and the results of their annual photomask manufacturers survey. The following companies are listed in order of their global market share (2009 info):[26]

Major chipmakers such as Intel, Globalfoundries, IBM, NEC, TSMC, UMC, Samsung, and Micron Technology, have their own large maskmaking facilities or joint ventures with the abovementioned companies.

The worldwide photomask market was estimated as $3.2 billion in 2012[27] and $3.1 billion in 2013. Almost half of the market was from captive mask shops (in-house mask shops of major chipmakers).[28]

The costs of creating new mask shop for 180 nm processes were estimated in 2005 as $40 million, and for 130 nm - more than $100 million.[29]

The purchase price of a photomask, in 2006, could range from $250 to $100,000[30] for a single high-end phase-shift mask. As many as 30 masks (of varying price) may be required to form a complete mask set. As modern chips are built in several layers stacked on top of each other, at least one mask is required for each of these layers.

See also

[edit]

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Photomask

View on Grokipedia
from Grokipedia
A photomask, also known as a , is a high-precision template consisting of a transparent substrate, typically or , coated with an opaque pattern that allows selective transmission of to project intricate circuit designs onto wafers during . This process is fundamental to (IC) fabrication, enabling the creation of microscopic features essential for modern electronics. Photomasks are constructed from a fused silica () plate, commonly measuring 6 inches by 6 inches, overlaid with an opaque film such as to block light in designated areas, while transparent or phase-altering regions permit patterned exposure. A protective pellicle, a thin , is often attached to shield the mask from contaminants during use in fabrication facilities. The patterns on the mask are generated from electronic design data using advanced tools like electron-beam or writers, followed by and rigorous to ensure defect-free precision down to nanometer scales. Several types of photomasks exist to meet the demands of evolving nodes, including binary masks, which use simple chrome-on-glass structures for basic light blocking and transmission; phase-shift masks, which manipulate light wavefronts through thickness variations or attenuated materials like silicide to enhance resolution and reduce effects; and (EUV) masks, which employ multilayer reflective coatings of and to handle 13.5 nm wavelengths for sub-10 nm patterning. A single IC may require a mask set of 5 to 40 masks, with advanced nodes like 10 nm utilizing up to 76 masks to achieve complex architectures. In manufacturing, photomasks serve as the master originals for transferring patterns via exposure tools such as steppers and scanners, directly influencing device yield, performance, and reliability. Beyond ICs, they are applied in fabricating flat panel displays (FPDs), micro-electro-mechanical systems (), and other microstructured devices, underscoring their versatility in high-volume processes. Ongoing advancements in mask technology, including multi-beam writing and curvilinear patterns, continue to address challenges posed by shrinking feature sizes and increasing complexity in the industry.

Fundamentals

Definition and Purpose

A photomask is a transparent substrate featuring opaque patterns that functions as a master template for projecting designs onto wafers through . This device enables the precise transfer of intricate patterns, with features scaled down to nanometers, from the mask to photoresist-coated wafers via controlled light exposure, facilitating the high-volume production of microchips in fabrication. In the , the photomask serves as the foundational blueprint for every layer in chip fabrication, profoundly influencing manufacturing yield, resolution capabilities, and overall production costs. Its critical role persists across technology nodes, from early 10-micrometer scales to the 2 nm processes, with mass production beginning in the second half of 2025 (as of November 2025), underscoring its enduring significance in enabling smaller, more efficient devices. Photomasks remain essential even as evolves toward (EUV) systems for these advanced nodes. The concept of the photomask originated in the late 1950s and early 1960s with the advent of contact printing techniques in development, establishing it as a cornerstone of technology that has adapted to successive innovations without losing its core function.

Basic Components

A photomask consists of a flat, transparent substrate that serves as the foundational element, providing mechanical support while ensuring optical clarity for light transmission during the process. This substrate is typically synthetic , which offers high purity and low to maintain pattern integrity under exposure conditions. The core of the photomask's functionality lies in its patterned regions, where opaque areas known as absorbers block to define the circuit features transferred to the . These regions include active patterns that replicate the , as well as alignment marks for precise wafer-to-mask registration and test structures used to verify pattern fidelity and process parameters. In a standard binary photomask, these opaque features are formed by selectively removing portions of the absorber layer, creating transparent openings that allow to pass through and expose the . The typical layout of a binary photomask follows a chrome-on-glass () structure, in which an opaque chrome layer is deposited on the transparent substrate and patterned to form the desired lines and features. This design includes designated areas for attaching a protective pellicle frame, which secures a thin over the mask to prevent particle without interfering with light transmission. The configuration ensures high contrast between opaque and transparent areas, essential for accurate pattern projection in optical systems. Standard photomasks are manufactured in square dimensions, with the most common size being 6 inches by 6 inches (152.4 mm by 152.4 mm) and a thickness of approximately 0.090 inches (2.28 mm) to balance rigidity and compatibility with handling equipment. This sizing accommodates multiple exposures per mask in production environments. Within the photomask's active area, functional zones are organized to optimize efficiency, featuring multiple identical die patterns arranged in rows and columns to enable stepping across the surface. Between these dies, lines provide designated paths for subsequent of the into individual chips, while fiducials—precise reference marks—facilitate alignment during both mask writing and exposure steps. These elements ensure seamless integration into the semiconductor manufacturing workflow.

Historical Development

Early Innovations

The development of photomasks emerged in the and as a critical enabler for the burgeoning field of integrated circuits, coinciding with the invention of the planar manufacturing process at . In 1959, physicist at Fairchild conceived the planar design, which relied on to pattern oxide layers on wafers, necessitating precise masks to transfer circuit patterns. This innovation was first commercialized in 1960 when Fairchild produced the 2N1613 planar , marking the initial practical use of photomasks in semiconductor fabrication. Key pioneers at Fairchild, including Hoerni and engineer , drove these early efforts; Last led the team that fabricated the first planar integrated circuits in 1961 using hand-crafted masks, overcoming challenges in aligning multiple layers for monolithic devices. A significant milestone came in the with the introduction of chrome-on-glass photomasks, which replaced earlier emulsion-on-glass versions by depositing a thin chrome layer on glass substrates for superior opacity, durability, and resistance to defects during repeated use in tools. This shift improved mask longevity and precision, essential for scaling production of early ICs. Early photomask fabrication involved manual techniques, such as drawing patterns on film—a red acetate layer on a transparent base—using drafting tools, followed by photographic reduction to the final 1:1 scale via mercury arc lamps and contact printing onto . These processes were labor-intensive and prone to errors, with resolutions typically limited to 5-10 micrometers due to the constraints of hand alignment and stability. By the late , tools like photorepeaters began automating reduction steps, but manual intervention remained dominant. Photomasks saw broader adoption with the rise of metal-oxide-semiconductor (MOS) technology around 1967, as Fairchild and other firms integrated them into processes for fabricating MOS transistors and logic circuits, enabling higher densities than bipolar designs. A major limitation of early contact printing—where masks directly touched wafers, causing wear, contamination, and yield losses—was addressed through the transition to projection systems in the early 1970s, such as PerkinElmer's Micralign tools, which projected mask patterns optically to minimize physical contact and extend mask usability. This evolution supported the production of features down to 2-5 micrometers while boosting wafer throughput.

Advancements in Lithography Nodes

The evolution of photomasks in the and was driven by the need to enhance resolution as nodes approached sub-micron scales, aligning with predictions of doubling densities approximately every two years. In 1982, researchers, led by Marc Levenson, introduced phase-shift masks (PSM) to exploit interference effects for improved image contrast, enabling patterning at 250 nm half-pitch nodes using i-line at 365 nm wavelength. This innovation addressed limitations in conventional binary masks by introducing phase differences in transmitted light, marking a pivotal step in resolution enhancement techniques (RET). By the early , (OPC) emerged as a complementary method to mitigate diffraction-induced distortions, with initial implementations targeting 180 nm nodes through deliberate mask pattern adjustments. Entering the 2000s, photomask advancements focused on integrating more sophisticated RETs to support aggressive scaling to 90 nm and 45 nm nodes, where traditional 193 nm ArF faced severe resolution challenges. Embedded attenuated PSM (att-PSM) gained widespread adoption during this period, allowing 6-10% light transmission through phase-shifting layers to enhance edge contrast without the complexity of alternating phase designs. These masks proved essential for critical layers in logic devices, improving and reducing line- roughness at these nodes. Concurrently, electron-beam (e-beam) writing systems evolved to handle increasingly complex patterns required by OPC and att-PSM, with advanced variable-shaped beam tools reducing exposure times for intricate geometries through optimized shot strategies. This shift enabled the fabrication of masks with millions of sub-resolution features, supporting the intricate layouts demanded by shrinking feature sizes. In the 2010s, photomask development integrated with to extend 193 nm tools to 10 nm nodes, incorporating water immersion to effectively reduce and boost for finer pitches. This era also saw the pre-EUV reliance on techniques, such as self-aligned double and triple patterning, to achieve 14 nm node densities by decomposing single masks into multiple exposures, thereby multiplying effective resolution while managing overlay challenges. The transition to () lithography began in 2019 with production implementation at 7 nm nodes, using reflective EUV photomasks to pattern features down to 2 nm, enabled by 13.5 nm sources and initial 0.33 NA . By 2025, pilot programs for high-NA EUV (0.55 NA) advanced photomask requirements, demonstrating single-patterning viability for sub-2 nm features through optimized absorber stacks and pellicles to minimize defects in high-throughput environments. These developments, propelled by imperatives, reduced patterning steps and enhanced yield for next-generation nodes. Recent innovations in 2025 have leveraged AI-assisted to streamline photomask production, with algorithms enabling curvilinear mask patterns that reduce e-beam write times compared to Manhattan-style layouts, accelerating throughput for advanced nodes. This approach integrates predictive modeling for OPC and RET, fostering efficiency gains while maintaining precision in EUV-era complexity.

Design and Types

Binary Photomasks

Binary photomasks, also known as chrome-on-glass (COG) masks, are the simplest type of transmissive photomasks used in , consisting of fully opaque chrome regions that block light transmission and fully transparent regions that allow complete passage of light. These masks operate on binary , where the pattern defines clear contrasts between exposed and unexposed areas on the without any phase-shifting elements. The design of binary photomasks features straightforward patterns of chrome etched onto a fused silica substrate, enabling reliable patterning for features larger than 100 nm in standard deep (DUV) systems. This simplicity avoids complex , making them ideal for applications in and logic chip production at technology nodes of 28 nm and above, where they serve as a cost-effective option for mature semiconductor processes. Binary photomasks provide key advantages in fabrication and operation, including straightforward manufacturing via standard electron-beam lithography and etching, which supports high throughput in production environments. Their ideal on/off transmission characteristics yield a binary contrast of 1, defined as the normalized difference between maximum (transparent) and minimum (opaque) light intensity, ensuring sharp delineation in aerial images for conventional patterning. However, limitations arise from diffraction effects inherent to their amplitude-only modulation, which degrade resolution and contrast for features below 100 nm, necessitating alternative mask technologies for finer nodes.

Phase-Shift Masks

Phase-shift masks (PSMs) enhance resolution in optical by exploiting phase differences in transmitted waves to produce destructive interference at feature edges, thereby improving contrast and enabling sharper patterns compared to binary masks. This technique introduces a 180-degree phase shift between adjacent transparent regions, causing out-of-phase waves to cancel each other near edges and create darker lines in the aerial . This can result in up to a twofold improvement in resolution for periodic line features compared to conventional binary masks, depending on the configuration. Two primary types of PSMs are commonly employed: alternating PSMs and embedded attenuated PSMs. Alternating PSMs, also known as Levenson masks, utilize or alternating patterns where adjacent clear areas are etched to create the 180-degree phase shift, particularly effective for periodic line features through strong destructive interference. Embedded attenuated PSMs, on the other hand, incorporate a semi-transparent layer (typically ) that allows 6-10% light transmission while imparting the phase shift, making them suitable for random patterns by reducing the need for complex phase assignment. Key design elements of PSMs include precise to form phase-shifting layers and integration of (OPC) to mitigate diffraction-induced distortions. The depth in the substrate is calculated as d≈λ2(n−1)d \approx \frac{\lambda}{2(n-1)}, where λ\lambda is the exposure and nn is the of , ensuring the exact 180-degree phase difference. OPC is applied to PSM layouts by adding sub-resolution assist features and adjusting edges to compensate for proximity effects, enhancing pattern fidelity across varying densities. PSMs have been critical for fabricating logic devices at advanced nodes from 65 nm down to 10 nm, where they enable the printing of sub-wavelength features through enhanced contrast in deep lithography. Prior to the widespread adoption of (EUV) systems, PSMs were integral to schemes, such as double patterning, to achieve the required resolution for high-density interconnects and transistors in microprocessors. The of PSMs introduces significant challenges, primarily due to their increased fabrication complexity, which can significantly increase costs compared to binary masks through the need for specialized blanks, precise , and advanced . This complexity also demands careful phase conflict resolution in alternating designs and tighter control over material uniformity in attenuated types to avoid printability defects.

Materials and Fabrication

Substrate and Absorber Materials

The substrate of a photomask serves as the foundational transparent or reflective base, selected for its optical transparency, thermal stability, and minimal distortion under conditions. Fused silica, an amorphous form of , is the predominant substrate for deep ultraviolet (DUV) photomasks due to its exceptionally low coefficient of —approximately 0.5 × 10⁻⁶/°C—which prevents pattern warping during exposure and handling. It also exhibits high transmission exceeding 90% at 193 nm wavelengths, ensuring efficient light propagation in advanced ArF systems. For older technology nodes, such as those above 180 nm, soda-lime glass substrates are employed, offering cost-effectiveness while providing adequate optical flatness and transmittance for g-line and i-line exposures, though with higher rates around 9 × 10⁻⁶/°C compared to fused silica. In (EUV) photomasks, low-thermal-expansion glasses like Corning's ULE 7973 titania-silicate are used, achieving coefficients below 0.03 × 10⁻⁶/°C to maintain overlay accuracy in multilayer reflective stacks. Absorber materials are critical for defining opaque patterns that block selectively, with properties optimized for near-total absorption and minimal at specific wavelengths. In binary DUV photomasks, serves as the standard absorber, providing 100% opacity at 248 nm (KrF) wavelengths through its high extinction coefficient, which effectively attenuates without residual transmission in patterned areas. For EUV applications at 13.5 nm, tantalum-based compounds such as (TaN) and tantalum (TaBO) are preferred, offering high contrast ratios greater than 30:1 due to their strong absorption in the EUV while maintaining compatibility with multilayer reflectors. These materials are deposited in thin films (typically 50-70 nm) to minimize phase errors and shadowing effects in high-numerical-aperture systems. Key optical properties of these materials ensure precise pattern transfer. For DUV absorbers like , reflectivity is controlled below 5% across 193-248 nm to suppress unwanted reflections that could degrade . In EUV photomasks, the reflective multilayer consists of 40-50 alternating pairs of (Mo) and (Si) layers, each pair approximately 6.9 nm thick, achieving peak reflectivity of about 70% at 13.5 nm through constructive interference tailored to the . To mitigate ghosting and effects in DUV systems, anti-reflective coatings such as chrome oxynitride (CrON) are applied atop the absorber, reducing surface reflectivity to under 20% and enhancing pattern clarity by minimizing light bounce-back. As of 2025, advancements in photomask fabrication emphasize defect-free EUV blanks to support high-numerical-aperture (high-NA) , targeting particle densities below 0.01 per cm² on substrates to enable sub-2 nm node production without yield losses from contamination. These ultra-clean blanks, often produced via improved and cleaning protocols, address the heightened sensitivity of high-NA EUV systems to even nanoscale defects.

Manufacturing Process

The manufacturing process of photomasks commences with blank preparation, where a fused silica substrate is meticulously cleaned using chemical and ultrasonic methods to eliminate contaminants and ensure surface flatness within nanometer tolerances. An opaque absorber layer, typically chrome, is then deposited onto the cleaned substrate via using , achieving a uniform thickness of 80-100 nm to provide the required optical density for light blocking. Pattern writing follows, employing (e-beam) systems capable of address grids finer than 4 nm to define intricate features with sub-10 nm precision. These systems utilize either raster scanning, which systematically sweeps the beam across the entire field in a pixelated grid, or vector scanning, which directs the beam along vector-defined shapes to optimize exposure efficiency for complex geometries. For leading-edge masks supporting nodes below 7 nm, the writing process demands 10-20 hours per mask, reflecting the high data volumes and proximity effect corrections needed to mitigate . Subsequently, the exposed is developed to expose the underlying pattern, followed by to transfer it into the absorber. Chrome is predominantly performed via dry plasma processes using with chlorine-based chemistries, enabling anisotropic profiles and control under 5 nm. For phase-shift masks (PSM), an additional step is integrated, employing HF-based wet to achieve precise phase depths of approximately 180 degrees at the operating , often in a two-step process combining dry and wet methods for sidewall control. Post-etching, the mask undergoes with megasonic agitation in ozonated or alkaline solutions to dislodge particles and residues while minimizing feature , typically achieving particle removal efficiencies above 90% for sub-50 nm defects. is then conducted using scanning electron microscopy (CD-SEM) to verify feature dimensions, with tolerances held below 5 nm across the mask plate to meet specifications. Yields for advanced EUV photomasks are often around 50%, limited by defect densities and process variability in e-beam writing and etching. As of 2025, integration of AI-driven optimization in pattern fracturing and dose correction has improved manufacturing reliability for sub-3 nm nodes.

Operational Principles

Photolithography Integration

In photolithography, the photomask acts as the primary template for transferring intricate circuit patterns onto a silicon wafer coated with photoresist. For deep ultraviolet (DUV) systems operating at a 193 nm wavelength, illumination passes through the transmissive mask, where transparent regions allow light to reach the wafer while opaque areas block it, and projection optics reduce the pattern size typically by a factor of 4x before focusing it onto the wafer surface. In extreme ultraviolet (EUV) lithography at 13.5 nm, the process differs as the mask is reflective: EUV light incidents on the multilayer mirror structure, reflects selectively from patterned areas, and is then demagnified by similar reduction optics to expose the wafer, enabling finer features due to the shorter wavelength. Photolithography tools, such as steppers and scanners, integrate the through precise stage movements: the mask () stage and stage synchronize to scan or step across the field, ensuring uniform exposure of the entire in a single pass or multiple steps, with typical throughputs ranging from 100 to 200 per hour depending on the node and system configuration. The resolution of features transferred from the mask is fundamentally limited by the Rayleigh criterion, expressed as: CD=k1λNA\text{CD} = k_1 \frac{\lambda}{\text{NA}} where CD is the critical dimension (minimum feature size), k1k_1 is a process-dependent factor typically between 0.25 and 0.6, λ\lambda is the illumination wavelength, and NA is the numerical aperture of the projection system; photomasks contribute by supporting resolution enhancement techniques that reduce k1k_1, such as phase-shift masks briefly referenced here for contrast with binary types. Precise alignment between the photomask and is essential for multilayer patterning, achieved via fiducials on the mask and corresponding alignment marks etched into the wafer, which scanners detect optically to position layers accurately; for advanced 5 nm nodes, overlay tolerances must be maintained below 3 nm to prevent yield loss from misalignment. By 2025, integration advances focus on high-NA EUV scanners with NA = 0.55, which amplify mask 3D effects like shadowing and phase shifts, requiring computational compensation models during mask and exposure to preserve integrity at sub-2 nm scales.

Mask Error Enhancement Factor (MEEF)

The Mask Error Enhancement Factor (MEEF) quantifies the amplification of critical dimension (CD) errors from the photomask to the printed wafer pattern in photolithography processes. It is defined as the ratio of the change in wafer CD to the change in mask CD, normalized by the system's demagnification factor MM (typically 4 for modern steppers and scanners): MEEF=ΔCDwaferΔCDmask×M.\text{MEEF} = \frac{\Delta \text{CD}_\text{wafer}}{\Delta \text{CD}_\text{mask}} \times M. An ideal linear imaging process yields MEEF = 1, meaning wafer errors scale directly with mask errors adjusted for demagnification. In practice, non-linear effects cause MEEF > 1, particularly in advanced nodes. MEEF increases with shrinking feature sizes, aggressive lithography (low k1k_1 factor, where k1<0.3k_1 < 0.3), and phase errors in advanced mask types, as these conditions reduce image contrast and amplify error transfer. For sub-10 nm nodes, MEEF values typically range from 2 to 5 for dense patterns, demanding tighter mask CD tolerances (e.g., <1 nm 3σ) to maintain wafer fidelity. An approximate relation capturing blur effects is MEEF≈1+σpitch,\text{MEEF} \approx 1 + \frac{\sigma}{\text{pitch}}, where σ\sigma represents optical or resist blur and pitch is the feature spacing; higher blur relative to pitch exacerbates error enhancement. Measurement of MEEF relies on tools like the Aerial Image Measurement System (AIMS), which simulates wafer-plane aerial images from the mask under process conditions (e.g., specific illuminator shape and NA) to derive CD variations from intentional mask biases. This is critical for nodes at 7 nm and below, where simulations correlate AIMS data with wafer prints to predict error propagation without full wafer exposure. Mitigation strategies include sub-resolution assist features (SRAFs), which improve image contrast and process windows, thereby reducing MEEF in dense arrays by balancing intensity around main features. Additionally, 2025-era optical proximity correction (OPC) models incorporate stochastic effects from photon shot noise and resist fluctuations, enabling more robust error compensation in model-based OPC flows. High MEEF (>3) significantly impacts yield by magnifying CD errors >2 nm into wafer-scale deviations that exceed tolerances, potentially halving yields in critical layers through increased across-chip linewidth variation (ACLV) and defect printability. This amplification underscores the need for precise fabrication to sustain economic viability in sub-10 nm production.

Advanced Features and Challenges

Pellicles

Pellicles serve as essential protective covers for photomasks in , consisting of a thin stretched taut across an aluminum or similar frame and mounted approximately 5-10 mm above the mask surface to create a . This design allows airborne particles to impact the membrane rather than the delicate mask patterns below, thereby preventing defects during exposure without introducing optical distortions. The , typically fluoropolymer-based for deep ultraviolet (DUV) applications, has a thickness of around 0.8-1 μm to balance mechanical stability and light transmission. The primary function of a pellicle is to trap particles larger than 0.1 μm on its surface, where they remain out of the focal plane of the scanner, avoiding any shadowing or printing of contaminants onto the . By maintaining a sealed, clean within the scanner, pellicles extend photomask usability and reduce associated with or defect mitigation. In operation, the pellicle's positioning ensures that any trapped particles do not interfere with the projected image, preserving pattern fidelity across high-volume . For DUV lithography at wavelengths like 193 nm, pellicles employ amorphous fluoropolymers such as Teflon AF, developed by in the 1980s, which offer exceptional optical clarity with transmission exceeding 99%. These materials provide low absorption and high resistance to chemical degradation, enabling reliable performance in aggressive lithographic environments. In contrast, (EUV) pellicles utilize thinner membranes, 10-50 nm thick, made from materials like or carbon nanotubes (CNTs) to accommodate the vacuum conditions and intense heat loads exceeding 600°C, up to over 1000°C, with CNT-based membranes providing enhanced thermal management. Pellicles were first introduced in the by for DUV applications, revolutionizing contamination control in manufacturing. EUV pellicles, critical for advanced nodes, saw initial around 2019 alongside high-volume EUV tool deployment, with ongoing advancements by 2025 focusing on improved EUV transmission nearing 90% to minimize absorption impacts. As of 2025, companies like Chemicals are preparing for of CNT pellicles to support high-power EUV systems. These developments have been driven by collaborations between equipment makers like ASML and material suppliers to meet the demands of sub-7 nm processes. Key challenges for pellicles, particularly in EUV systems, include in environments, which can introduce molecular contaminants and degrade performance over time. Additionally, ensuring a lifetime of over 1000 exposures per pellicle remains a focus, as from EUV irradiation can lead to membrane deformation or failure, necessitating robust designs to support sustained high-throughput production.

EUV Photomasks

EUV photomasks represent a fundamental shift in mask technology for (EUV) , operating at a of 13.5 nm to enable patterning of features below 7 nm. Unlike traditional transmissive masks, EUV photomasks are reflective, consisting of a substrate coated with a multilayer stack of approximately 40 pairs of (Mo) and (Si) layers, each with a period of 13.5 nm, designed to achieve over 70% reflectivity at the EUV . This multilayer is topped by a (Ta)-based absorber layer, typically 50-70 nm thick, which patterns the desired features by blocking EUV light reflection. The structure ensures high contrast while minimizing absorption losses in the reflective system. Key differences from deep ultraviolet (DUV) photomasks include their non-transmissive nature, relying on reflection rather than transmission, which necessitates operation in a environment to prevent EUV light absorption by air. Additionally, EUV masks exhibit a higher mask error enhancement factor (MEEF) of 4-6, compared to 1-3 in DUV, primarily due to shadowing effects from the oblique illumination angles (around 6 degrees) in EUV scanners, which amplify pattern errors on the . These attributes demand specialized handling and alignment to mitigate asymmetry in printed features. Fabrication of EUV photomasks begins with ion-beam deposition of the Mo/Si multilayer onto a low-thermal-expansion substrate, achieving interface roughness below 0.2 nm RMS to preserve reflectivity and minimize . The absorber is then patterned using electron-beam (e-beam) , with a thin Ru capping layer (typically 2-5 nm) on the multilayer, and sometimes a buffer layer of materials like SiO2 (20-50 nm) to protect the delicate multilayer during and ensure precise feature definition at sub-50 nm scales. This process requires ultra-clean environments to avoid defects that could propagate through the stack. Significant challenges in EUV photomasks arise from three-dimensional (3D) effects, including topographic that causes non-uniform illumination and horizontal-vertical feature biases, exacerbated by the mask's . Stochastic from and defect-induced phase shifts further complicates yield at advanced nodes. By , the transition to high-numerical-aperture (high-NA) EUV systems necessitates thinner absorbers (below 50 nm) to reduce shadowing and improve resolution for 2 nm nodes, while maintaining optical performance. Since their introduction in production for 5 nm nodes in , EUV photomasks have become standard for critical layers in 5 nm to 2 nm processes, enabling complex logic and devices. By 2025, refinements in defect mitigation and process control have supported the scaling of chips for AI and .

Inspection and

Defect Types and Detection

Photomask defects are broadly classified into hard, soft, and phase defects, each with distinct characteristics and implications for lithographic performance. Hard defects are permanent structural anomalies in the mask pattern, such as chrome extensions, missing absorber regions, or unintended bridges between features, which arise from errors in the patterning process and cannot be easily removed. Soft defects, in contrast, are transient and removable contaminants, primarily particles or residues that adhere to the mask surface, often capable of light and altering transmission. Phase defects involve subtle variations in the phase of transmitted or reflected , typically due to etch depth errors in phase-shift masks, leading to constructive or destructive interference that distorts the aerial on the . In (EUV) photomasks, an additional category of multilayer buried defects predominates, where pits, bumps, or particles embedded within the Mo/Si multilayer stack induce phase shifts without surface visibility, complicating detection and potentially printing as defects even at sub-20 nm scales. These defects originate primarily from contamination during fabrication processes and writing errors during , with EUV-specific buried defects often introduced during multilayer deposition on the substrate. Contamination sources include airborne particles in cleanrooms or residues from handling, while writing errors stem from beam instabilities or dosage inaccuracies in mask patterning. Detection of these defects relies on advanced inspection techniques tailored to mask complexity. Die-to-die optical , operating at 193 nm wavelengths, compares adjacent dies on the for discrepancies, achieving sensitivities down to 20 nm for hard and soft defects through brightfield and darkfield modes. For EUV masks, actinic tools, which use EUV wavelengths to mimic lithographic conditions, provide superior detection of phase and buried defects; as of 2025, systems like the ACTIS series offer resolutions to 15 nm with throughputs exceeding 100 masks per hour, enabling high-volume screening without compromising accuracy. As of late 2025, the ACTIS A200HiT series from Lasertec offers enhanced throughput for high-volume EUV screening. These methods incorporate for reference image generation to reduce false positives, maintaining false defect rates below 10% in production environments. Achieving low defect densities is critical for advanced nodes, with industry standards targeting below 0.01 defects per cm² for sub-7 nm EUV masks to ensure reliable performance. A single critical defect, particularly in high-density patterns, can propagate to the , significantly reducing yield across a production lot (potentially by tens of percent) due to replicated patterning errors across multiple dies. This underscores the need for rigorous to mitigate yield impacts, as even non-printing defects detected early prevent downstream losses in fabrication.

Repair Techniques

Photomask repair techniques are essential for correcting defects identified during , ensuring masks remain viable for production without necessitating costly replacement. These methods primarily target opaque, transparent, and phase defects in the absorber layers, using precision tools to remove or deposit material at the nanoscale. (FIB) systems, employing ions (Ga⁺), enable chrome removal and deposition with a beam resolution below 5 nm, allowing for accurate milling of unwanted absorber material or addition of carbon-based deposits to fill missing features. Laser ablation serves as a complementary approach for addressing soft defects, such as particulate or minor , by vaporizing the material without significantly affecting surrounding structures. or pulsed lasers heat and ablate excess absorber or particles, achieving clean removal on both DUV and EUV while minimizing thermal damage to the substrate. Phase defects, which alter the phase of transmitted light due to topography variations, require specialized restoration of layer depth. Nano-etching techniques, often using e-beam induced processes, selectively remove or deposit material to correct height discrepancies, while e-beam induced repair achieves precision for features below 10 nm by enabling gas-assisted or deposition directly at the defect site. For EUV photomasks, repair must preserve the integrity of the underlying multilayer reflector to avoid reflectivity loss. Electron beam tools perform actinic-compatible repairs at low voltages (e.g., 400 V) to minimize penetration and to the multilayer stack, targeting absorber defects without compromising EUV performance. In 2025, AI-guided repair systems enhance precision by automating defect localization and process optimization, achieving high success rates for first-pass corrections on advanced nodes. The repair workflow begins with post-inspection localization of defects using high-resolution , followed by targeted application of the chosen technique. Verification occurs via scanning electron microscopy (CD-SEM) for dimensional accuracy and aerial image measurement systems (AIMS) to confirm lithographic printability, ensuring the repaired meets specifications. Despite advancements, repair capabilities have inherent limitations; typically, only a few defects per can be addressed effectively due to risks of introducing new artifacts or cumulative processing effects. Each repair incurs significant costs (often tens of thousands of dollars), driven by specialized equipment and the high value of photomask sets (up to $50 million or more for advanced nodes as of 2025), making multiple fixes uneconomical compared to mask rejection.

Industry Landscape

Leading Manufacturers

Photronics Inc., headquartered , leads the advanced photomask segment with a focus on (EUV) for nodes at 7nm, 5nm, and 3nm, enabling high-resolution patterning for leading-edge integrated circuits. The company has expanded its production capabilities through investments in multi-beam mask writers, including the first U.S. installation of such a system in 2025 to support domestic chipmaking and EUV mask fabrication. Photronics maintains partnerships with major foundries to deliver specialized masks for advanced processes. Toppan Photomasks (rebranded as Tekscend Photomask Corp. in late 2024), based in , excels in phase-shift masks (PSM) for flat-panel displays and EUV photomasks tailored for 2nm and 3nm logic semiconductors, incorporating collaborations with entities like for . Its strengths lie in high-precision manufacturing that enhances resolution and in display applications. Dai Nippon Printing Co. Ltd. (DNP), another Japanese powerhouse, commands a substantial share in logic photomask production, with expertise in EUV masks for beyond-2nm generations and the integration of multi-beam writing tools to accelerate development for 2nm processes. DNP partners with initiatives like to advance high-volume manufacturing for next-generation logic chips. Together, Photronics, , and DNP collectively hold an estimated 40-50% of the global photomask market share as of 2025, dominating advanced semiconductor applications. Supporting these leaders are suppliers of foundational components: , also from , specializes in photomask blanks critical for EUV , providing low-defect substrates with multilayer reflective coatings. , likewise Japanese, focuses on EUV photomask substrates and blanks, featuring low-thermal-expansion glass with advanced optical films to ensure pattern fidelity in sub-5nm fabrication. Mitsui Chemicals, also Japanese, is a leading producer of pellicles for photomasks, serving as thin dust-proof membranes to protect against contamination during semiconductor lithography processes, with a long-standing role since 1984 and advancements in materials like carbon nanotubes for EUV applications. Emerging Chinese manufacturers, such as Shenzhen Qingyi Photomask Limited, are gaining traction in niche and cost-sensitive segments, contributing to Asia's expanding role in the . Overall, the industry's geographic distribution centers on , which dominates production due to semiconductor hubs in , , , and , accounting for over 36% of the market in recent years while and handle significant advanced R&D and capacity. The global photomask market is estimated at approximately USD 5.6 billion in 2025, driven by increasing demand for advanced nodes, with an expected (CAGR) of around 4.7% leading to a market size of USD 7.0 billion by 2030. The (EUV) segment is a key growth area, anticipated to represent about 25-30% of total revenue by 2025 and expanding rapidly due to its role in sub-5nm fabrication, with the EUV photomask market alone valued at USD 1.25 billion in 2024 and forecasted to grow at a CAGR of 11.8% through 2033. Key drivers include the surging demand for complex photomasks in AI accelerators and chips at 2nm and below, where advanced nodes require intricate patterns to enable higher transistor densities and performance gains essential for AI applications. Additionally, geopolitical tensions and policy initiatives like the U.S. CHIPS Act and equivalent European measures are accelerating supply chain diversification, prompting investments in domestic photomask production in and to reduce reliance on Asia-Pacific manufacturing. Challenges persist, particularly with EUV photomasks, where lead times have extended to 20-30 weeks due to capacity constraints and the need for defect-free multilayer blanks, exacerbating delays in chip production schedules. High-end EUV masks also command costs exceeding USD 100,000 per unit, often reaching USD 350,000 for blanks alone, driven by stringent precision requirements and limited supplier infrastructure. In 2025, emerging trends include the integration of (AI) in photomask design and inspection processes, which is expected to reduce overall costs by 15-20% through automated defect detection and optimized layout generation, improving yield rates in high-volume . Sustainability efforts are also gaining traction, with initiatives exploring eco-friendly substrates such as recycled silica-based materials to minimize environmental impact while maintaining optical performance standards. Looking ahead, high-numerical-aperture (high-NA) EUV technology is poised for dominance by 2027, enabling sub-2nm nodes with enhanced resolution and supporting the next wave of AI and chips, though it will further elevate mask complexity and costs. Meanwhile, emerges as a potential disruptor, offering a lower-cost alternative to traditional photomasks by directly imprinting patterns without light sources, potentially challenging EUV adoption in cost-sensitive applications if scalability improves.

References

  1. https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/
  2. https://heidelberg-instruments.com/applications/photomasks/
  3. https://www.appliedmaterials.com/il/en/semiconductor/products/processes/photomask.html
  4. https://www.lasertec.co.jp/en/products/glossary/3597.html
  5. https://www.hamamatsu.com/jp/en/applications/semiconductor/photomask_manufacturing.html
  6. https://www.laits.utexas.edu/~anorman/long.extra/Projects.F97/DAVID/paper.html
  7. https://www.osha.gov/semiconductors/definitions
  8. https://semiengineering.com/disruptive-changes-ahead-for-photomasks/
  9. https://semiengineering.com/metrology-advances-step-up-to-sub-2nm-device-node-needs/
  10. https://www.global.dnp/development/basic-technology/micro-processing/index.html
  11. https://www.lithoguru.com/scientist/lithobasics.html
  12. https://www.toppan.com/en/electronics/photo_mask/semicon/specification/pdf/photo_mask_e.pdf
  13. https://www.photomaskportal.com/terminology.html
  14. https://www.computerhistory.org/siliconengine/invention-of-the-planar-manufacturing-process/
  15. https://spectrum.ieee.org/the-silicon-dioxide-solution
  16. https://www.asianometry.com/p/the-history-of-the-semiconductor
  17. https://www.computerhistory.org/siliconengine/first-planar-integrated-circuit-is-fabricated/
  18. https://spie.org/news/photonics-focus/marchapril-2025/aiding-the-march-of-moores-law
  19. https://www.lithoguru.com/scientist/CHE323/Lecture58.pdf
  20. https://www2.eecs.berkeley.edu/Pubs/TechRpts/1994/ERL-94-34.pdf
  21. https://signoffsemiconductors.com/optical-proximity-correction-opc/
  22. https://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/ispd03/pdffiles/07_1.pdf
  23. https://pubs.aip.org/avs/jvb/article/22/6/3543/898301/Writing-strategy-and-electron-beam-system-with-an
  24. https://www.hitachihyoron.com/rev/pdf/2000/r2000_04_202.pdf
  25. https://www.researchgate.net/publication/234146446_Immersion_Lithography_Photomask_and_Wafer-Level_Materials
  26. https://www.cerc.utexas.edu/utda/publications/C157.pdf
  27. https://pr.tsmc.com/english/news/2010
  28. https://semiengineering.com/photomask-changes-and-challenges-at-mature-and-advanced-nodes/
  29. https://spie.org/documents/Membership/BacusNewsletters/BACUS_Newsletter_September_2023.pdf
  30. https://viewmm.com/en/what-are-photomasks-types-applications-inspection/
  31. https://www.photronics.com/integrated-circuits-ic/leading-edge-advanced-photomasks/
  32. https://semiengineering.com/photomask-shortages-grow-at-mature-nodes/
  33. https://www.deanfrancispress.com/index.php/te/article/download/1791/1663/6921
  34. https://optics.ansys.com/hc/en-us/articles/360042256473-Lithography-using-binary-mask
  35. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/7488/748801/Front-Matter-Volume-7488/10.1117/12.848146.pdf
  36. http://lithoguru.com/scientist/litho_tutor/TUTOR41%20%28May%2003%29.pdf
  37. https://pubs.aip.org/avs/jvb/article/23/2/417/896033/Edge-effects-characterization-of-phase-shift-mask
  38. https://eureka.patsnap.com/article/binary-mask-vs-phase-shift-mask-whats-the-difference
  39. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/3873/0000/Properties-of-fused-silica-for-157-nm-photomasks/10.1117/12.373334.full
  40. https://valleydesign.com/corning-7980/
  41. https://www.archivemarketresearch.com/reports/photomask-for-semiconductor-devices-355472
  42. https://patents.google.com/patent/US20230205072A1/en
  43. https://www.sciencedirect.com/science/article/pii/S2590007223000539
  44. https://spie.org/documents/Membership/BacusNewsletters/BACUS-Newsletter-October-2016.pdf
  45. https://euvlsymposium.lbl.gov/pdf/2007/MA-P06-Choi.pdf
  46. https://patents.google.com/patent/CN101424873A/en
  47. https://www.gminsights.com/industry-analysis/laser-photomask-market
  48. https://www.researchgate.net/publication/253053306_Recent_progress_in_the_fabrication_of_low_defect_density_mask_blanks
  49. https://spie.org/Publications/Proceedings/Volume/6283
  50. https://www.ims.co.at/wp-content/uploads/2019/01/2013-08-22_JM3_Vol-12-3_031108.pdf
  51. https://semiengineering.com/inside-photomask-writing/
  52. https://patents.google.com/patent/US7790334B2/en
  53. https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/cd-sem/
  54. https://www.intelmarketresearch.com/semiconductor-ic-photomask-2025-2032-114-1147
  55. https://www.newport.com/n/deep-uv-photolithography
  56. https://www.asml.com/technology/lithography-principles/light-and-lasers
  57. http://optoelectronics.eecs.berkeley.edu/ThesisJaione.pdf
  58. https://eureka.patsnap.com/article/euv-mask-vs-duv-mask-materials-challenges-and-inspection-methods
  59. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/6283/62830G/EUV-mask-process-development-and-integration/10.1117/12.681839.full
  60. https://www.asml.com/technology/lithography-principles/mechanics-and-mechatronics
  61. https://www.spiedigitallibrary.org/ebook/Download?urlid=10.1117%252F3.769214.ch10&isFullBook=False
  62. https://www.asml.com/technology/lithography-principles/rayleigh-criterion
  63. https://semiengineering.com/knowledge_centers/manufacturing/lithography/lithography-k1-coefficient/
  64. https://semiengineering.com/how-overlay-keeps-pace-with-euv-patterning/
  65. https://www.imec-int.com/en/articles/high-na-euvl-next-major-step-lithography
  66. https://www.spiedigitallibrary.org/journals/journal-of-micro-nanopatterning-materials-and-metrology/volume-24/issue-01/011002/Resolution-enhancement-for-high-numerical-aperture-extreme-ultraviolet-lithography-by/10.1117/1.JMM.24.1.011002.full
  67. https://eureka.patsnap.com/report-high-na-0-55-euv-imaging-resist-requirements-dof-and-mask-3d-effects
  68. https://www.lithoguru.com/scientist/litho_papers/1999_91_MEEF%20in%20Theory%20and%20Practice.pdf
  69. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/5377/0000/Impact-of-resist-blur-on-MEF-OPC-and-CD-control/10.1117/12.537472.pdf
  70. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/7122/71221D/AIMS-and-resist-simulation/10.1117/12.801226.full
  71. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13655/1365507/Stochastic-aware-compact-OPC-model-validation-for-reducing-failure-probability/10.1117/12.3072074.short
  72. https://spie.org/publications/spie-publication-resources/optipedia-free-optics-information/pm146_78_pellicles
  73. https://semiengineering.com/knowledge_centers/manufacturing/lithography/pellicle/
  74. https://www.fast-micro.com/blog/news-1/fastmicro-launches-the-fm-pds-particle-defect-inspection-system-1
  75. https://www.biogeneral.com/pdfs/Teflon-AF-Amorphous-Fluoropolymers.pdf
  76. https://www.mliusa.com/pdf/MLIintroduction.pdf
  77. https://spie.org/photomask-technology/presentation/Characterization-of-CNT-Pellicles-in-an-EUV-Scanner-Environment-and/13686-106
  78. https://www.asml.com/en/news/stories/2022/the-euv-pellicle-indistinguishable-from-magic
  79. https://semiengineering.com/euvs-future-looks-even-brighter/
  80. https://jp.mitsuichemicals.com/en/release/2024/2024_0528_1/index.htm
  81. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13655/136550K/Development-status-and-future-prospects-of-CNT-pellicle/10.1117/12.3072193.full
  82. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13215/132151C/Relative-lifetime-estimation-of-EUV-pellicle-by-normalized-thermal-stress/10.1117/12.3038648.full
  83. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13424/1342407/Imaging-characteristics-of-reflective-EUV-masks/10.1117/12.3051480.full
  84. https://www.sciencedirect.com/science/article/abs/pii/S0167931710000286
  85. https://www.euvlitho.com/2021/SS21.pdf
  86. https://www.researchgate.net/publication/256911830_MoSi_multilayers_for_EUV_lithography_by_ion_beam_sputter_deposition
  87. https://semiengineering.com/next-euv-issue-mask-3d-effects/
  88. https://euvlitho.com/2023/P61.pdf
  89. https://www.linkedin.com/pulse/euv-photomasks-market-demand-forecast-20252033-5k3wf/
  90. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2005/EECS-2005-28.pdf
  91. https://semiconductor.alfachemic.com/services/photomask-inspection.html
  92. https://www.lasertec.co.jp/en/news/20251031_%2520ACTIS%2520A200HiT%2520Series.pdf
  93. https://www.kla.com/products/reticle-manufacturing
  94. https://eureka.patsnap.com/article/what-is-a-mask-defect-and-how-does-it-affect-semiconductor-yield
  95. https://www.researchgate.net/publication/258718043_Photomask_Repair_Technology_by_using_Gas_Field_Ion_Source
  96. https://pubs.aip.org/avs/jvb/article/31/4/041602/467141/Focused-ion-beam-induced-Ga-contamination-An
  97. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13655/1365508/Efficient-defect-repair-methodology-for-N2-EUV-masks-by-using/10.1117/12.3069289.short
  98. https://pubs.aip.org/avs/jvb/article-pdf/17/6/3137/11139680/3137_1_online.pdf
  99. https://www.spiedigitallibrary.org/journals/Pushing-the-limits-of-EUV-mask-repair--addressing-sub/volume-20/issue-03/031013/Pushing-the-limits-of-EUV-mask-repair--addressing-sub/10.1117/1.JMM.20.3.031013.full
  100. https://goldberg.lbl.gov/papers/Qi_JM3_15_2_023502_2016.pdf
  101. https://asset-downloads.zeiss.com/catalogs/download/smt/8b4159f5-427f-40ec-8fbd-c356caceb57b/pushing-the-limits-of-euv-mask-repair_addressing-sub-10nm-defects-with-the-next-generation-e-beam-based-mask-repair-tool.pdf
  102. https://dacemirror.sci-hub.st/journal-article/040fe26e181f19549a4f4207462d4fdd/liang2000.pdf
  103. https://spie.org/news/4159-improving-extreme-uv-lithography-mask-repair
  104. https://www.zeiss.com/semiconductor-manufacturing-technology/products/photomask-solutions/mask-qualification.html
  105. https://pubs.aip.org/avs/jvb/article/22/6/2902/896894/Electron-beam-based-photomask-repair
  106. https://patentpc.com/blog/chip-manufacturing-costs-in-2025-2030-how-much-does-it-cost-to-make-a-3nm-chip
  107. https://semiengineering.com/mask-complexity-cost-and-change/
  108. https://www.imarcgroup.com/photomask-market
  109. https://photronicsinc.gcs-web.com/news-releases/news-release-details/photronics-extends-capability-first-installation-merchant-multi
  110. https://www.photomask.com/en/product/photomask/
  111. https://www.global.dnp/news/detail/20176139_4126.html
  112. https://www.hoya.com/en/business/informationtechnology/
  113. https://agcem.com/products/euv-mask-blanks/
  114. https://us.mitsuichemicals.com/service/product/pellicle/index.htm
  115. https://www.marketresearchfuture.com/reports/photomask-market-34231
  116. https://www.globenewswire.com/news-release/2025/08/18/3134697/0/en/Photomask-Market-Size-to-Surpass-USD-7-22-Billion-by-2032-at-a-CAGR-of-4-31-Research-by-SNS-Insider.html
  117. https://www.grandviewresearch.com/industry-analysis/photomask-market-report
  118. https://www.wiseguyreports.com/reports/euv-photomasks-market
  119. https://www.mordorintelligence.com/industry-reports/photomask-market
  120. https://www.ainvest.com/news/photronics-strategic-based-advanced-photomask-manufacturing-2508/
  121. https://www.techinsights.com/blog/ebeam-initiative-survey-reports-euv-fueling-photomask-industry-growth
  122. https://averroes.ai/whitepaper/the-future-of-photomask-technology-and-ai-driven-inspection
  123. https://www.linkedin.com/pulse/silicon-stencil-mask-market-overview-investor-guide-fougf/
  124. https://markets.financialcontent.com/wral/article/marketminute-2025-9-30-asmls-high-na-euv-tools-powering-the-sub-2nm-era-and-reshaping-the-semiconductor-landscape
  125. https://semiengineering.com/nanoimprint-finds-its-footing-in-photonics/
  126. https://www.the-waves.org/2023/11/10/nanoimprint-lithography-disruption-canon-vs-asml-rivalry-unfolds/
Add your contribution
Related Hubs
User Avatar
No comments yet.