Hubbry Logo
NXP LPCNXP LPCMain
Open search
NXP LPC
Community hub
NXP LPC
logo
8 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
NXP LPC
NXP LPC
from Wikipedia

LPC (Low Pin Count) is a family of 32-bit microcontroller integrated circuits by NXP Semiconductors (formerly Philips Semiconductors).[1] The LPC chips are grouped into related series that are based around the same 32-bit ARM processor core, such as the Cortex-M4F, Cortex-M3, Cortex-M0+, or Cortex-M0. Internally, each microcontroller consists of the processor core, static RAM memory, flash memory, debugging interface, and various peripherals. The earliest LPC series were based on the Intel 8-bit 80C51 core.[2] As of February 2011, NXP had shipped over one billion ARM processor-based chips.[3]

NXP LPC1114 in 33-pin HVQFN package and LPC1343 in 48-pin LQFP package.

Overview

[edit]

All recent LPC families are based on ARM cores, which NXP Semiconductors licenses from ARM Holdings, then adds their own peripherals before converting the design into a silicon die. NXP is the only vendor shipping an ARM Cortex-M core in a dual in-line package: LPC810 in DIP8 (0.3-inch width) and LPC1114 in DIP28 (0.6-inch width). The following tables summarize the NXP LPC microcontroller families.

History

[edit]
  • In 1982, Philips Semiconductors invented the I²C-bus, and is currently the top supplier of I²C solutions in the world.[11]
  • In January 2005, Philips Semiconductors launched the PNX4008 'Nexperia™ Mobile Multimedia Processor', featuring an ARM9 processor and including PowerVR MBX graphics IP from Imagination Technologies.
  • In February 2005, Philips Semiconductors announces the LPC3000 ARM9 series, based on the Nexperia platform.[12]
  • In September 2006, Philips Semiconductors was spun off to a consortium of private equity investors and changed its name to NXP.[1] As part of this spin off, NXP acquired the older Philips LPC microcontroller families.
  • In September 2006, NXP announced the LPC2300 and LPC2400 ARM7 series.[13]
  • In September 2007, NXP announced the LPC2900 series.[14]
  • In February 2008, NXP announced the licensing of the ARM Cortex-M3 core from ARM Holdings.[15]
  • In March 2008, NXP announced the LPC3200 ARM9 series.[16]
  • In October 2008, NXP announced the LPC1700 series.[17]
  • In February 2009, NXP announced the licensing of the ARM Cortex-M0 core from ARM Holdings.[18]
  • In May 2009, NXP announced the LPC1300 series.[19]
  • In January 2010, NXP launched the LPCXpresso Toolchain for NXP ARM processors.[20]
  • In February 2010, NXP announced the licensing of the ARM Cortex-M4F core from ARM Holdings.[21]
  • In April 2010, NXP announced the LPC1102, the world’s smallest ARM microcontroller at 2.17 mm x 2.32 mm size.[22]
  • In September 2010, NXP announced the LPC1800 series.[23]
  • In February 2011, NXP announced the LPC1200 series.[24]
  • In April 2011, NXP announced the LPC11U00 series with USB.[25]
  • In September 2011, NXP announced the LPC11D00 series with a LCD controller.[26]
  • In December 2011, NXP announced the LPC4300 series, the first dual-core chip with an ARM Cortex-M4F and ARM Cortex-M0.[27]
  • In February 2012, NXP announced the LPC1100LV series with dual supply voltage to allow interfacing to both 1.8 V and 3.3 V peripherals.[28]
  • In March 2012, NXP announced the LPC1100XL series for extra low-power and LPC11E00 series with EEPROM.[29]
  • In March 2012, NXP announced the licensing of the ARM Cortex-M0+ core from ARM Holdings.[30]
  • In March 2012, NXP introduced a "longevity program" to promise availability of IC chips from select ARM families for 10 or more years.[31]
  • In March 2012, NXP announced the LPC11A00 series with flexible analog subsystem.[32]
  • In April 2012, NXP announced the LPC11C00 series with a CAN bus controller.[33]
  • In September 2012, NXP announced the LPC4000 series based on ARM Cortex-M4F.[34]
  • In November 2012, NXP announced the LPC800 series based on the ARM Cortex-M0+ core, and the first ARM Cortex-M in a DIP8 package.[35]
  • In April 2013, NXP announced the LPC-Link 2 JTAG / SWD debug adapter. Multiple firmware versions are available to emulate popular debug adapters.[36][37]
  • In May 2013, NXP announced that it acquired Code Red Technologies, an embedded software development tools provider, such as the LPCXpresso IDE and Red Suite.[38][39]
  • In October 2013, NXP announced the LPC4370 microcontroller.[40]
  • In December 2013, NXP announced the LPC11E37H and the LPC11U37H microcontrollers.[41]
  • In January 2017, NXP announced LPC54000 MCU series along with a refresh of the LPC800 series.[42]

LPC4000 series

[edit]
LPC4000 Family[43]
General information
LaunchedCurrent
Performance
Max. CPU clock rate120  to 204 MHz
Architecture and classification
MicroarchitectureARM Cortex-M4F[4]
ARM Cortex-M0[6]
Instruction setThumb, Thumb-2,
Sat Math, DSP, FPU
LPC 4330-based development board from German manufacturer Hitex

The LPC4xxx series are based on the ARM Cortex-M4F core.

LPC4300

[edit]

The LPC4300 series have two or three ARM cores, one ARM Cortex-M4F and one or two ARM Cortex-M0. The LPC4350 chips are pin-compatible with the LPC1850 chips. The LPC4330-Xplorer development board is available from NXP. The summary for this series is:[27][44][45]

  • Core:
    • ARM Cortex-M4F and one or two ARM Cortex-M0 core at a maximum clock rate of 204 MHz.
    • Debug interface is JTAG or SWD with SWO "Serial Trace", eight breakpoints and four watch points. JTAG supports both cores, but SWD only supports Cortex-M4F core.
  • Memory:
    • Static RAM sizes of 104 / 136 / 168 / 200 / 264 KB.
    • Flash sizes of 0 / 512 / 768 / 1024 KB.
    • EEPROM size of 16 KB.
    • ROM size of 64 KB, which contains a boot loader with optional booting from USART0 / USART3, USB0 / USB1, SPI Flash, Quad SPI Flash, external 8 / 16/ 32-bit NOR flash. The ROM also contains an API for in-system programming, in-application programming, OTP programming, USB device stack for HID / MSC / DFU.
    • OTP size of 64 bits.
    • Each chip has a factory-programmed 128-bit unique device identifier number.
  • Peripherals:
    • four UART, two I²C, one SPI, two CAN, none / one / two high-speed USB 2.0 Host/Device controller (one is OTG capable), none or one Ethernet controller, none or one LCD controller, interface for SDRAM, and more.
  • Oscillators consists of optional external 1 to 25 MHz crystal or oscillator, external 32.768 kHz crystal for RTC, internal 12 MHz oscillator, and three internal PLLs for CPU / USB / Audio.
  • IC packages: LQFP100, TFBGA100, LQFP144, TFBGA180, LQFP208, LBGA256.
  • Operating voltage range is 2.2 to 3.6 volt.

LPC4000

[edit]

The LPC4000 series are based on the single ARM Cortex-M4F processor core. The LPC408x chips are pin-compatible with the LPC178x chips. The summary for this series is:[34][46]

  • Core:
    • ARM Cortex-M4F core at a maximum clock rate of 120 MHz.
    • Debug interface is JTAG or SWD with SWO "Serial Trace", eight breakpoints and four watch points.
  • Memory:
    • Static RAM sizes of 24 / 40 / 80 / 96 KB.
    • Flash sizes of 64 / 128 / 256 / 512 KB.
    • EEPROM sizes of 2 / 4 KB.
    • ROM boot loader.
    • Each chip has a factory-programmed 128-bit unique device identifier number.
  • Peripherals:
    • four or five UART, three I²C, one high-speed USB 2.0 Device controller or Host / Device / OTG controller, none or one Ethernet controller, none or one LCD controller, and more.
  • Oscillators consists of optional external 1 to 25 MHz crystal or oscillator, external 32.768 kHz crystal for RTC, internal 12 MHz oscillator, and two internal PLLs for CPU and USB.
  • IC packages: LQFP80, LQFP144, TFBGA180, LQFP208, TFBGA208.
  • Operating voltage range is 2.4 to 3.6 volt.

LPC3000 series

[edit]
LPC3000 Family[47]
General information
LaunchedCurrent
Max. CPU clock rateto 266 MHz
Architecture and classification
MicroarchitectureARM9
Instruction setThumb, ARM

The LPC3xxx series use the ARM926EJ-S core, and were based on the Nexperia SoC platform. Was the first 90 nm ARM9 MCU processor family.[48]

LPC3200

[edit]

The LPC3200 series are based on the ARM926EJ-S processor core.[16][49]

LPC3100

[edit]

The LPC3100 series are based on the ARM926EJ-S processor core.[50] The LPC3154 is used by NXP to implement the LPC-Link debugger on all LPCXpresso boards.[51][52] The LPC3180 core operates up to 208 MHz, and features interfaces for SDRAM, USB 2.0 full-speed, NAND flash, Secure Digital (SD) and I²C.[citation needed]

LPC2000 series

[edit]
LPC2000 Family[47][53]
General information
LaunchedCurrent
Max. CPU clock rateto 72 MHz
Architecture and classification
MicroarchitectureARM7, ARM9
Instruction setThumb, ARM

LPC2000 is a series based on a 1.8-volt ARM7TDMI-S core operating at up to 80 MHz together with a variety of peripherals including serial interfaces, 10-bit ADC/DAC, timers, capture compare, PWM, USB interface, and external bus options. Flash memory ranges from 32 kB to 512 kB; RAM ranges from 4 kB to 96 kB.[citation needed]

NXP has two related series without the LPC name, the LH7 series are based on the ARM7TDMI-S and ARM720T cores,[54] and the LH7A series are based on the ARM9TDMI core.[55]

LPC2900

[edit]

The LPC2900 series are based on the ARM968E-S processor core.[14][56]

LPC2400

[edit]

The LPC2400 series are based on the ARM7TDMI-S processor core.[13][57]

LPC2300

[edit]

The LPC2300 series are based on the ARM7TDMI-S processor core.[13][58] The LPC2364/66/68 and the LPC2378 are full-speed USB 2.0 devices with 2 CAN interfaces and 10/100 Ethernet MAC in LQFP100 and LQFP144 packages. Multiple peripherals are supported including a 10-bit 8-channel ADC and a 10-bit DAC.[citation needed]

LPC2200

[edit]

The LPC2200 series are based on the ARM7TDMI-S processor core.[59]

LPC2100

[edit]

The LPC2100 series are based on the ARM7TDMI-S processor core.[60] The LPC2141, LPC2142, LPC2144, LPC2146, and LPC2148 are full-speed USB 2.0 devices in LQFP64 packages. Multiple peripherals are supported including one or two 10-bit ADCs and an optional 10-bit DAC.[citation needed]

LPC1000 series

[edit]
LPC1000 Family[61][62]
General information
LaunchedCurrent
Performance
Max. CPU clock rate30  to 180 MHz
Architecture and classification
MicroarchitectureARM Cortex-M3[5]
ARM Cortex-M0[6]
Instruction setThumb, Thumb-2
mbed with NXP LPC1768

The NXP LPC1000 family consists of six series of microcontrollers: LPC1800, LPC1700, LPC1500, LPC1300, LPC1200, LPC1100. The LPC1800, LPC1700, LPC1500, LPC1300 series are based on the Cortex-M3 ARM processor core.[61] The LPC1200 and LPC1100 are based on the Cortex-M0 ARM processor core.[62]

LPC1800

[edit]

The NXP LPC1800-series are based on the ARM Cortex-M3 core.[23][63] The LPC1850 is pin-compatible with the LPC4350 parts. The available packages are TBGA100, LQFP144, BGA180, LQFP208, BGA256. The LPC4330-Xplorer development board is available from NXP.

The Apple M7 and M8 motion co-processor chips are most likely based on the LPC1800 series, as LPC18A1 and LPC18B1.

LPC1700

[edit]

The NXP LPC1700-series are based on the ARM Cortex-M3 core.[17][64] The LPC178x is pin-compatible with the LPC408x parts. The available packages are LQFP80, LQFP100, TFBGA100, LQFP144, TFBGA180, LQFP208, TFBGA208. The LPC1769-LPCXpresso development board is available from NXP. The mbed LPC1768 board is also available. With EmCrafts LPC-LNX-EVB a LPC1788 based board with μClinux is available.[65]

LPC1500

[edit]

The NXP LPC1500-series are based on the ARM Cortex-M3 core.[66] The available packages are LQFP48, LQFP64, LQFP100. The LPC1549-LPCXpresso development board is available from NXP along with a motor control kit.

LPC1300

[edit]

The NXP LPC1300-series are based on the ARM Cortex-M3 core.[19][67] The available packages are HVQFN33, LQFP48, LQFP64. The LPC1343-LPCXpresso and LPC1347-LPCXpresso development board are available from NXP.

LPC1200

[edit]

The NXP LPC1200-family are based on the ARM Cortex-M0 core. It consists of 2 series: LPC1200, LPC12D00.[24][68][69] The available packages are LQFP48, LQFP64, LQFP100. The LPC1227-LPCXpresso development board is available from NXP.

LPC1100

[edit]

The NXP LPC1100-family are based on the ARM Cortex-M0 core. It consists of 8 series: LPC1100 Miniature, LPC1100(X)L, LPC1100LV, LPC11A00, LPC11C00, LPC11D00, LPC11E00, LPC11U00.

LPC1100 Miniature

[edit]

The LPC1100 series primarily targets an ultra tiny footprint. The available package is WLCSP16 (2.17 mm x 2.32 mm).[22][70] The LPC1104-LPCXpresso development board is available from NXP.

LPC1100(X)L

[edit]

The LPC1100(X)L-series consists of three subseries: LPC111x, LPC111xL, and LPC111xXL. The LPC111xL and LPC111xXL include the power profiles, a windowed watchdog timer, and a configurable open-drain mode. The LPC1110XL adds a Non-Maskable Interrupt (NMI) and 256-byte page flash erase function. The LPC1114-LPCXpresso and LPC1115-LPCXpresso development board are available from NXP. The summary for these series are:[29][71]

  • Core:
    • ARM Cortex-M0 core at a maximum clock rate of 50 MHz.
    • Includes 24-bit SysTick Timer.
    • Debug interface is SWD with four breakpoints and two watchpoints. JTAG debugging is not supported.
  • Memory:
    • Static RAM sizes of 1 / 2 / 4 / 8 KB general purpose.
    • Flash sizes of 4 / 8 / 16 / 24 / 32 / 64 KB general purpose.
    • ROM boot loader.
    • Each chip has a factory-programmed 128-bit unique device identifier number.
  • Peripherals:
    • LPC111x has one UART, one I²C, one or two SPI, two 16-bit timers, two 32-bit timers, watch dog timer, five to eight multiplexed 10-bit ADC, 14 to 42 GPIO.
      • I²C supports standard mode (100 kHz) / fast-mode (400 kHz) / fast-mode Plus (1 MHz) speeds, master / slave / snooping modes, multiple slave addresses.
    • LPC111xL consists of LPC111x features, plus low power profile in active and sleep modes, internal pull-up resistors to pull-up pins to full VDD level, programmable pseudo open-drain mode for GPIO pins, upgraded to windowed watch dog timer with clock source lock capability.
    • LPC111xXL consists of LPC1110L features, plus flash page erase In-Application Programming (IAP) function, timers / UART / SSP peripherals available on more pins, one capture feature added to each timer, capture-clear feature on 16-bit and 32-bit timers for pulse-width measurements.
  • Oscillators consists of optional external 1 to 25 MHz crystal or oscillator, internal 12 MHz oscillator, internal programmable 9.3 kHz to 2.3 MHz watchdog oscillator, and one internal PLL for CPU.
  • IC packages:
  • Operating voltage range is 1.8 to 3.6 volt.

LPC1100LV

[edit]

The LPC1100LV series primarily targets a low operating voltage range of 1.65 to 1.95 volt power. Its I²C is limited to 400 kHz. It is available in two power supply options: A 1.8 volt single power supply (WLCSP25 and HVQFN24 packages), or 1.8 volt (core) / 3.3 volt (IO/analog) dual power supply with 5 volt tolerant I/O (HVQFN33 package). The available packages are WLCSP25 (2.17 mm × 2.32 mm), HVQFN24 and HVQFN33.[28][72]

LPC11A00

[edit]

The LPC11A00 series primarily targets analog features, such as: 10-bit ADC, 10-bit DAC, analog comparators, analog voltage reference, temperature sensor, EEPROM memory. The available packages are WLCSP20 (2.5 mm x 2.5 mm), HVQFN33 (5 mm x 5 mm), HVQFN33 (7 mm x 7 mm), LQFP48.[32][73]

LPC11C00

[edit]

The LPC11C00 series primarily targets CAN bus features, such as: one MCAN controller, and the LPC11C22 and LPC11C24 parts include an on-chip high-speed CAN transceiver. The available package is LQFP48.[33][74] The LPC11C24-LPCXpresso development board is available from NXP.

LPC11D00

[edit]

The LPC11D00 series primarily targets LCD display features, such as: 4 x 40 segment LCD driver. The available package is LQFP100.[26][75]

LPC11E00

[edit]

The LPC11E00 series primarily targets EEPROM memory and Smart Card features.[29][76]

LPC11U00

[edit]

The LPC11U00 series primarily targets USB features, such as: USB 2.0 full-speed controller. It's the first Cortex-M0 with integrated drivers in ROM. This series is pin-compatible with the LPC134x series.[25][77] The LPC11U14-LPCXpresso development board is available from NXP. The mbed LPC11U24 board is also available.

LPC800 series

[edit]
LPC800 Family [78]
General information
Launched2012
DiscontinuedCurrent
Performance
Max. CPU clock rate30 MHz
Architecture and classification
MicroarchitectureARM Cortex-M0+[7]
Instruction setThumb subset,
Thumb-2 subset

LPC800

[edit]

The NXP LPC800 microcontroller family are based on the Cortex-M0+ ARM processor core. Unique features include a pin switch matrix, state configurable timer, clockless wake-up controller, single-cycle GPIO, DIP8 package. The LPC812-LPCXpresso development board is available from NXP. The summary for this series is:[35][79][80]

  • Core:
    • ARM Cortex-M0+ core at a maximum clock rate of 30 MHz.
    • Includes a single-cycle 32x32 bit multiplier, 24-bit SysTick Timer, Vector Table Relocation, full NVIC with 32 interrupts and four levels of priorities, single-cycle GPIO.
    • Doesn't include a memory protection unit (MPU), nor a wake-up interrupt controller (WIC). Instead NXP added their own clockless wake-up controller to lower power usage.
    • The debug interface is SWD with four breakpoints, two watchpoints, 1 KB Micro Trace Buffer (MTB). JTAG debugging is not supported.
  • Memory:
    • Static RAM sizes of 1 / 2 / 4 KB general purpose.
    • Flash sizes of 4 / 8 / 16 KB general purpose, zero wait-state up to 20 MHz, one wait-state up to 30 MHz.
    • ROM size of 8 KB, which contains a boot loader with optional booting from USART. The ROM also contains an API for USART communication, I²C communication, flash programming, in-system programming, and power profile.
    • Each chip has a factory-programmed 128-bit unique device identifier number.
  • Peripherals:
    • One to three USARTs, one I²C, one or two SPI, one analog comparator, four interrupt timers, state configurable timer, wake-up timer, windowed watchdog timer, 6 to 18 single-cycle GPIOs, cyclic redundancy check (CRC) engine, pin switch matrix, four low-power modes, brownout detect.
    • I²C supports standard mode (100 kHz) / fast-mode (400 kHz) / fast-mode Plus (1 MHz) speeds, master / slave / snooping modes, multiple slave addresses.
  • Oscillators consists of optional external 1 to 25 MHz crystal or oscillator, internal 12 MHz oscillator, internal programmable 9.3 kHz to 2.3 MHz watchdog oscillator, and one internal PLL for CPU.
  • IC packages are DIP8 (0.3-inch width), TSSOP16, TSSOP20, SO20. NXP is the only vendor shipping ARM Cortex-M cores in DIP packages.
  • Operating voltage range is 1.8 to 3.6 volt.

Legacy series

[edit]

LPC900

[edit]

The LPC900 series are legacy devices based on the 8-bit 80C51 processor core.[81]

LPC700

[edit]

The LPC700 series are legacy devices based on the 8-bit 80C51 processor core.[82]

Development boards

[edit]

LPCXpresso boards

[edit]
LPC1343 LPCXpresso development board. LPC-LINK SWD debugger on left of J4 and target LPC1343 on right of J4

LPCXpresso boards are sold by NXP to provide a quick and easy way for engineers to evaluate their microcontroller chips.[83][84] The LPCXpresso boards are jointly developed by NXP, Code Red Technologies,[38] and Embedded Artists.[20]

Each LPCXpresso board has the following common features:

  • On-board LPC-LINK for programming and debugging via a MiniUSB connector.
  • Board can be cut into two separate boards: LPC-LINK board and target microcontroller board.
  • Power input from 5 V via the USB cable or 5 V external power. If boards are separated, then 3.3 V external power is required for the target microcontroller board.
  • Target microcontroller side:
    • User LED.
    • 12 MHz crystal.
    • Prototype area.
    • Holes for JTAG/SWD debugger connection.
    • DIP footprint compatible with mbed boards.

Development tools

[edit]

Cortex-M

[edit]

LPC

[edit]
Flash programming via UART

All LPC microcontrollers have a ROM'ed bootloader that supports loading a binary image into its flash memory using one or more peripherals (varies by family). Since all LPC bootloaders support loading from the UART peripheral and most boards connect a UART to RS-232 or a USB-to-UART adapter IC, thus it's a universal method to program the LPC microcontrollers. Some microcontrollers requires the target board to have a way to enable/disable booting from the ROM'ed bootloader (i.e. jumper / switch / button).

  • lpc21isp A multi-platform open-source tool to flash LPC microcontrollers over the UART.
  • Flash Magic, a commercial program for Windows and macOS to perform in-system programming of the LPC flash via its UART.
  • nxp_isp_loader, an open-source tool to flash LPC microcontrollers over the UART.
Debugging tools (JTAG / SWD)
  • OpenOCD, an open source software package for JTAG access using a wide variety of hardware adapters.
  • LPC-Link 2, by NXP, a JTAG / SWD debug adapter that has multiple firmware releases available to emulate popular debug adapter protocols, such as: J-Link by Segger, CMSIS-DAP by ARM, Redlink by Code Red Technologies. All connectors are 1.27 mm (0.05-inch) pitch.[36][37]

Documentation

[edit]

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer (NXP Semiconductors) and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).

NXP documentation tree (top to bottom)
  1. NXP website.
  2. NXP marketing slides.
  3. NXP datasheet.
  4. NXP reference manual.
  5. ARM core website.
  6. ARM core generic user guide.
  7. ARM core technical reference manual.
  8. ARM architecture reference manual.

NXP has additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official NXP and ARM documents.

See also

[edit]

References

[edit]

Further reading

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia
from Grokipedia
The LPC (Low Pin Count) is a family of 32-bit integrated circuits developed by , featuring processor cores and targeted at embedded applications from low-power sensors to high-performance industrial systems. Originally introduced by Semiconductors in the early as one of the first integrated flash-based microcontrollers, the LPC line transitioned to NXP following the spin-off of Philips Semiconductors into an independent company. By 2018, the portfolio had grown to over 400 devices, building on more than 11 years of innovation to support diverse markets including IoT, automotive, and . Key defining characteristics include scalable performance with clock speeds up to 204 MHz, memory options reaching 1 MB of flash and 282 KB of SRAM, and integrated peripherals such as USB, CAN, Ethernet, and LCD controllers for enhanced connectivity and efficiency. The LPC family encompasses multiple series tailored to specific needs, including the entry-level LPC800 with Cortex-M0+ cores for cost-sensitive designs, the LPC1100 for ultra-low power applications, the performance-oriented LPC4000 and LPC4300 series with Cortex-M4 and dual-core options, and advanced lines like LPC54000 and LPC5500 for IoT and secure processing using Cortex-M33 cores. Supported by NXP's MCUXpresso software ecosystem and a 10-year product longevity program, the LPC microcontrollers emphasize ease of development, reliability, and long-term availability for engineers.

Overview

The LPC family originated with Semiconductors in the early 2000s, with the LPC2000 series introduced in 2004 as one of the first integrated flash-based microcontrollers using the ARM7TDMI core. In 2006, Philips Semiconductors was spun off to form , which continued expanding the line. Key milestones include the 2010 launch of the dual-core LPC4300 series, the 2011 introduction of the Cortex-M4-based LPC4000 series, and the 2012 debut of the low-cost LPC800 series with Cortex-M0+ cores. The portfolio grew further with the LPC54000 series in 2017 for high-performance IoT applications and the LPC5500 series in 2018, featuring secure Cortex-M33 cores. By 2018, the family encompassed over 400 devices, supported by a 10-year program.

LPC5500 Series

Architecture and Core

The LPC5500 series utilizes the Arm Cortex-M33 core, operating at up to 150 MHz, based on the Armv8-M architecture with integrated TrustZone for secure processing. Some variants, such as the LPC55S6x family, feature an optional second Cortex-M33 core for enhanced performance and power efficiency in multi-tasking scenarios. The core includes a single-precision (FPU), (DSP) extensions, and a (MPU) for reliable operation in embedded systems. In high-end models like the LPC55S6x, a dedicated DSP accelerator (PowerQuad) provides up to 10x improvement in tasks. Memory options scale across families, with up to 640 KB of on-chip flash (supporting PRINCE encryption for secure code execution) and 320 KB of SRAM, including dedicated banks for code, system, and USB operations. Error correction and secure partitioning are enabled via TrustZone and MPU, allowing flexible allocation while preventing unauthorized access. The system employs a multi-layer AHB matrix bus for high-bandwidth concurrent access by the core(s) and peripherals, supported by two DMA controllers offering up to 32 channels for efficient data transfers and offloading CPU tasks. Clocking is managed through independent PLLs (PLL0 and PLL1), sourcing from an internal free-running oscillator (FRO) at 96 MHz (or 12 MHz/1 MHz variants) or external crystals up to 25 MHz, enabling core frequencies up to 150 MHz. Low-power modes include sleep (with RTC active at ~1 µA), deep-sleep (~100 nA), power-down, and deep power-down (~475 nA without RTC), facilitated by an integrated (PMU) with DC-DC converter support for single-supply operation at 1.8-3.6 V. Wake-up sources such as the 32 kHz RTC ensure always-on functionality for battery-powered applications.

Features and Applications

The LPC5500 series integrates peripherals optimized for secure, connected embedded systems. Connectivity includes full-speed (FS) and high-speed (HS) USB 2.0 interfaces with on-chip PHY (crystal-less FS option), supporting host/device modes up to 480 Mbps; up to nine FlexComm interfaces configurable as UART, SPI (up to 50 MHz HS SPI), I²C, or I²S; and SDIO for dual-card support. Analog features comprise a 16-bit ADC (up to 2 MSPS, 10 channels) with threshold comparison, alongside comparators and DACs in select models. Timers include five 32-bit counter/timers (CTIMER), a state-configurable timer/PWM (SCTimer), RTC, watchdog (WWDT), and multi-rate timer (MRT) for precise control. Security is a core strength, with hardware accelerators for AES-256, , PRINCE, true generator (TRNG), and SRAM physically unclonable function (PUF) for root-of-trust generation, enabling secure boot, debug authentication, and real-time decryption. The series encompasses scalable families: the baseline LPC551x/S1x with up to 256 KB flash and 96 KB SRAM for cost-sensitive designs; LPC552x/S2x with enhanced connectivity; and performance-oriented LPC55S6x with dual cores, up to 640 KB flash/320 KB SRAM, and DSP for compute-intensive tasks. Automotive-grade variants in some families meet AEC-Q100 standards. Packages range from compact VFBGA59 (5x5 mm) to HLQFP100 (14x14 mm), including HTQFP64 and VFBGA98 for space-constrained integrations. Applications target secure IoT gateways, industrial control, , , diagnostic equipment, and edge nodes, leveraging the series' balance of performance, security, and low power. The Cortex-M33 delivers up to 1.5 DMIPS/MHz, supporting responsive real-time operation while enabling energy-efficient designs for always-connected devices.

LPC54000 Series

Architecture and Core

The LPC54000 Series utilizes an Arm Cortex-M4 main processor operating at up to 180 MHz, with an optional Arm Cortex-M0+ in select variants to support asynchronous operation and independent task execution via a multi-layer AHB matrix interconnect. The Cortex-M4 core incorporates a single-precision (FPU) compliant with IEEE 754-2008, enabling efficient handling of floating-point computations for performance-critical applications, while the M0+ core manages lower-power, real-time tasks at comparable frequencies in dual-core variants like select LPC541xx models. This setup allows the M4 core to be powered down while the M0+ maintains essential functions, optimizing energy use in tiered processing scenarios. The memory system provides scalable storage with up to 512 KB of on-chip flash in standard models or up to 4 MB of integrated Quad SPI serial flash in variants like the LPC54S018, and 360 KB of SRAM configured as 160 KB contiguous main SRAM plus 192 KB on instruction and data buses, plus an 8 KB USB-dedicated bank. (ECC) is supported on SRAM for enhanced , and memory allocation is flexible between cores where applicable, managed through the Cortex-M4's (MPU) to enable secure partitioning and efficient sharing without contention. This configuration supports high-throughput access via separate bus masters for each core, with individual power domains for granular control. The system bus employs a multi-layer AHB matrix with an integrated crossbar switch to facilitate concurrent access by multiple masters, delivering high bandwidth for core-to-memory and core-to-peripheral transfers. Dual DMA controllers, providing up to 32 channels total, enable efficient inter-core communication through memory-to-memory transfers and peripheral offloading, reducing CPU overhead in data-intensive operations. Clocking flexibility is achieved via independent phase-locked loops (PLLs), including a system PLL (PLL0) that generates core clocks up to 180 MHz from sources like the 12/48/96 MHz free-running oscillator (FRO) or external crystals, with separate configurations possible for each core in dual-core models. Low-power states include deep-sleep mode at ~54 µA (SRAM retained, 25°C) and deep power-down at ~1 µA (RTC enabled, 25°C), supporting always-on functionality through wake-up sources like the 32 kHz RTC. The integrated (PMU) oversees these modes, with programmable scaling of core and peripheral voltages to minimize consumption during idle or reduced-frequency operation, making the architecture suitable for battery-powered, always-on IoT devices.

Features and Applications

The LPC54000 series microcontrollers integrate a range of peripherals tailored for embedded applications requiring efficient processing and interface capabilities. Key among these is the LCD controller, which supports high-resolution on STN and TFT displays up to 1024x768 pixels in 24-bit , augmented by SmartDMA for offloading data transfers to LCD/TFT panels and enabling hardware cursor functionality. Advanced audio features include the Inter-IC Sound () interface for stereo or mono audio with (TDM) support, SPDIF for digital audio transmission, and a digital microphone (DMIC) subsystem for PDM inputs. Connectivity options encompass a Quad SPI Flash Interface (SPIFI) enabling execute-in-place (XIP) operation from external flash at speeds up to 52 MB/s, as well as a 10/100 Mbps Ethernet MAC with DMA and (AVB) support for networked applications. Analog peripherals feature two 12-bit ADCs, one offering up to 5 MSamples/sec across 12 channels with threshold comparison and integrated temperature sensor, suitable for precise signal acquisition. The series comprises several model variants optimized for different performance and environmental needs. The LPC541xx models include single- and dual-core configurations with up to 512 KB on-chip flash and 192 KB SRAM (including 160 KB main and 32 KB on instruction/data buses), providing cost-effective options for general-purpose use. The flagship LPC546xx models feature a single-core with up to 512 KB flash and 200 KB SRAM (160 KB main plus additional banks), supporting partitioned processing for complex tasks. For automotive applications, the LPC54S0xx variants are qualified to AEC-Q100 standards with ASIL-B compliance, incorporating enhanced features like AES-256 and SHA acceleration while featuring up to 360 KB SRAM, with flash via external SPIFI or integrated up to 4 MB QSPI serial flash in select configurations. These microcontrollers are available in compact packages ranging from 100 to 208 pins, including TFBGA (100, 144, 180 pins) and LQFP (100, 208 pins) types, which facilitate integration into space-constrained designs such as portable devices and control modules. Primary applications leverage the series' real-time capabilities and peripheral richness for human-machine interfaces (HMIs) in industrial panels, multimedia devices like audio players and displays, systems in appliances, and connected gateways for IoT edge processing. The hardware provided by SmartDMA and cryptographic engines enhances efficiency in rendering and signal processing tasks. Performance is characterized by up to 1.25 DMIPS/MHz on the Cortex-M4 core, enabling responsive operation at clock speeds to 180 MHz while maintaining low power consumption for battery-operated or always-on scenarios.

LPC4000 Series

LPC43xx

The LPC43xx series represents a pivotal advancement in the LPC4000 family, introducing a dual-core that combines an ARM Cortex-M4 processor with a Cortex-M0 to enable efficient multitasking in embedded systems. This design allows the Cortex-M4, operating at up to 204 MHz with a (FPU), to manage computationally intensive tasks such as and control algorithms, while the Cortex-M0, also capable of up to 204 MHz, handles real-time operations and peripheral management to ensure low-latency responses. The series supports inter-core communication through shared SRAM acting as a mailbox mechanism and an event router for interrupt-based signaling, facilitating seamless code partitioning where complex application logic runs on the M4 and deterministic tasks on the M0. Memory resources in the LPC43xx are optimized for dual-core operation, featuring up to 1 MB of dual-bank that permits simultaneous read/write operations across banks, alongside up to 264 kB of SRAM distributed in multiple power-domain blocks for flexible allocation between cores. An external (EMC) further extends capabilities by interfacing with SDRAM, NAND flash, NOR flash, and static RAM, supporting bus widths up to 32 bits depending on the package. This configuration bridges legacy systems requiring robust I/O handling with modern demands for higher performance, as evidenced by the series' integration of connectivity features like a high-speed USB 2.0 interface (480 Mbps) supporting host, device, and OTG modes with DMA, a 10/100 Mbps Ethernet MAC compliant with IEEE 1588 for precise timing, and up to two CAN 2.0B controllers for automotive and industrial networking. Clocking in the LPC43xx is managed by an advanced (PLL) system, including PLL0 for USB (14 kHz to 25 MHz input), PLL1 for main system clocks (up to 320 MHz internally before division to 204 MHz), and an audio-dedicated PLL, all fed by a 1-25 MHz or a 12 MHz internal RC oscillator. This multi-domain clocking architecture allows independent for peripherals and cores, enhancing power efficiency in applications like , industrial automation, and . Introduced in 2011, the LPC43xx targeted scenarios needing partitioned code execution to optimize resource use without compromising real-time performance.

LPC40xx

The LPC40xx family consists of single-core Cortex-M4-based microcontrollers developed by for embedded applications emphasizing high integration, capabilities, and efficient power usage. These devices target general-purpose control, human-machine interfaces, and industrial automation, offering a and peripheral support without the complexity of dual-core architectures. Introduced in 2012, the LPC40xx series provides scalable options for developers, with ranging from 64 KB to 512 KB and SRAM from 16 KB to 96 KB, enabling flexible code and data storage for real-time systems. At the heart of the LPC40xx is a 32-bit Arm Cortex-M4 processor core operating at up to 120 MHz, incorporating instructions and, on select models, a single-precision (FPU) compliant with IEEE 754-2008 for accelerated mathematical operations in applications like and sensor processing. Memory configuration supports (ISP) and in-application programming (IAP) through UART0 or SPIFI interfaces, allowing field updates without specialized hardware. The family distinguishes itself through integrated peripherals tailored for display and analog interfacing, including a PWM unit capable of generating precise waveforms for three-phase motor drives and a 12-bit successive approximation ADC with 8 multiplexed channels, achieving conversion rates up to 400 kSamples/s at full resolution. Higher-end variants also feature an LCD controller supporting STN and TFT panels up to 1024 × 768 resolution with 24-bit . Power efficiency is achieved via dynamic scaling across multiple modes—active, , deep-sleep, power-down, and deep power-down—operating on a single 3.3 V supply (2.4 V to 3.6 V range). Typical active-mode current draw is approximately 56 mA at 120 MHz with peripherals enabled, equating to about 467 µA/MHz, while power-down mode reduces consumption to 280–600 µA, supporting battery-powered or energy-constrained designs. The LPC407x variants serve general-purpose needs with USB device/host support and up to 512 KB flash but lack Ethernet and LCD on lower models, whereas the LPC408x extends functionality with an integrated Ethernet MAC for networked applications, (EMC), and FPU across the lineup, making it suitable for connectivity-focused prototyping and development.

LPC3000 Series

LPC32xx

The LPC32xx series, specifically the LPC32x0 family, represents ' early ARM9-based microcontrollers designed for embedded applications requiring a balance of high performance and low power consumption. These devices feature the ARM926EJ-S core, a 16/32-bit RISC processor with a 5-stage pipeline, , Memory Management Unit (MMU), and DSP extensions for enhanced tasks. The core supports operation at frequencies up to 266 MHz, delivering approximately 220 MIPS of performance, and includes hardware-based Jazelle technology for direct execution of Java byte-code, enabling efficient Java applications without interpretation overhead. Additionally, an integrated Vector Floating Point (VFP) accelerates floating-point computations, making it suitable for and workloads. Memory architecture in the LPC32xx emphasizes flexibility for and storage-intensive uses, with 32 kB of instruction cache and 32 kB of cache to optimize core by reducing external access latency. The series provides a dedicated interface for SDR or , supporting 16- or 32-bit wide buses and capacities up to 512 Mbit (64 MB) per bank at speeds up to 133 MHz, allowing seamless integration of large dynamic pools. For non-volatile storage, dual NAND flash controllers—one for single-level cell (SLC) and one for multi-level cell (MLC) devices—enable direct connection to various flash sizes and configurations, with built-in error correction via Reed-Solomon encoding/decoding and DMA support to minimize CPU intervention during transfers. On-chip SRAM ranges from 128 kB to 256 kB across variants, providing fast access for code and . Peripherals in the LPC32xx are oriented toward and connectivity, including a versatile LCD controller that drives STN or TFT panels with resolutions up to × 768 pixels, palette or direct color modes (up to 24-bit), and dedicated DMA for efficient frame buffer handling, ideal for display-intensive applications. A USB 2.0 full-speed OTG interface supports host, device, or OTG modes with an integrated OHCI-compliant host controller and dedicated PLL for 48 MHz operation, facilitating peripherals like storage devices or human-interface inputs. Other notable integrations include a 10/100 Ethernet MAC with DMA and for checksums and frame filtering on select models (LPC3240/3250), multiple , SPI, and UART interfaces, as well as a 10-bit ADC with support. These features position the LPC32xx for , industrial controls, and medical devices requiring graphical interfaces and networked connectivity. Clocking and power management employ a multi-PLL , including a 397x PLL for precise RTC derivation, a USB PLL for stable 48 MHz, and an HCLK PLL for scalable peripheral clocks, allowing independent domain control to optimize power in dynamic workloads. The core operates at a supply voltage of 0.9 V to 1.39 V (typically 1.35 V for full speed), while I/O pads support 1.8 V, 3.0 V, or 3.3 V levels for broad compatibility, and EMC interfaces (for memory) range from 1.7 V to 3.6 V. Released around 2008, the LPC32xx series has become a legacy platform but remains relevant in legacy for its robust capabilities and support via provided board support packages. As of 2025, the series is discontinued with limited availability under NXP's product longevity program.

LPC31xx

The LPC31xx series, part of NXP's LPC3000 family, consists of low-cost, power-efficient ARM9-based microcontrollers optimized for applications needing high-speed USB connectivity, external memory support, and battery-powered operation. Introduced in 2009 as a more energy-efficient alternative to the higher-performance LPC32xx series, these devices target industrial, consumer, and portable systems where compact design and low power are critical. At the heart of the LPC31xx is the ARM926EJ-S processor core, operating at clock speeds of 180 MHz in base models like the LPC3130/3131 and up to 270 MHz in variants such as the LPC3141/3143, with support for dynamic voltage and to balance performance and energy use. The core includes a (MMU) for multitasking, along with separate 16 kB instruction and 16 kB data caches featuring 8-word line lengths to enhance execution efficiency from external memory. Memory architecture emphasizes flexibility for storage-intensive tasks, with up to 192 kB of on-chip SRAM and a multi-port (MPMC) supporting up to 128 MB of external SDRAM or SRAM via an 8/16-bit interface. A dedicated NAND flash controller handles 8/16-bit devices with hardware 8-bit ECC for reliable data storage, commonly used in industrial applications. Key integrated peripherals include a secure digital host controller compatible with SD/MMC, SDHC, SDIO, and CE-ATA cards for removable storage, alongside two interfaces for audio codec connectivity in portable devices. A battery-backed (RTC) ensures timekeeping in low-power states, supporting applications like data logging. Power management is a standout feature, with a 1.2 V core supply enabling ultra-low consumption: typical standby mode draws 1.75 mW, while can reach as low as 50 µA, making the LPC31xx suitable for battery-operated industrial controls and gadgets. Variants like the LPC313x focus on general industrial use, the LPC314x adds AES decryption and one-time programmable (OTP) memory for security, and the LPC315x incorporates a stereo with headphone for peripherals. As of 2025, the series is discontinued with limited availability under NXP's product longevity program.

LPC2000 Series

The LPC2000 series, introduced in the mid-2000s, is now considered legacy by NXP as of 2025, with varying availability across devices.

LPC24xx and LPC23xx

The LPC24xx and LPC23xx series represent higher-end models within the LPC2000 family of microcontrollers, designed for demanding embedded applications requiring advanced connectivity and integration. These devices are built around the ARM7TDMI-S 16-bit/32-bit RISC processor core, which operates at speeds up to 72 MHz, providing efficient performance for real-time tasks while maintaining low power consumption. The architecture supports real-time emulation and debugging interfaces, such as EmbeddedICE, enabling seamless development for complex systems. Memory configurations in the LPC23xx series typically include 128 kB to 512 kB of on-chip flash memory for program storage, paired with 16 kB to 64 kB of SRAM for data handling, including dedicated portions for peripherals like Ethernet and USB. The LPC24xx series extends this with 256 kB to 512 kB flash and up to 96 kB total SRAM, incorporating additional general-purpose and DMA-accessible RAM blocks to support more intensive multitasking. Both series feature In-System Programming (ISP) and In-Application Programming (IAP) capabilities for the flash, allowing field updates without specialized hardware. Key peripherals emphasize connectivity and interface versatility. Select models in the LPC23xx series integrate a 10/100 Ethernet MAC with DMA support for networked applications, two CAN 2.0B controllers for robust industrial communication, and a full-speed USB 2.0 device controller with 4 kB of dedicated endpoint RAM. Building on this, the LPC24xx adds an LCD controller capable of driving STN and TFT panels up to 1024 × 768 resolution, an external for interfacing with SDRAM or other devices, and enhanced timers with up to 10 compare outputs for PWM generation in automation tasks. Both series include four 32-bit timers with capture/compare functions, multiple UARTs, SSP/SPI, , and interfaces, along with a 10-bit ADC and DAC for . Clocking is managed via an on-chip PLL that multiplies the input oscillator frequency (from 32 kHz to 25 MHz) to achieve the full 72 MHz CPU speed, with options for USB and Ethernet clocking derived from the same source. Brown-out detection circuitry monitors supply voltage with configurable thresholds—typically 2.95 V for and 2.65 V for reset—ensuring reliable operation in power-unstable environments. Introduced in 2006–2007, these series gained popularity in USB-intensive applications such as printers, point-of-sale terminals, and industrial controllers due to their balanced integration of host/device USB functionality with networking capabilities.

LPC21xx and LPC22xx

The LPC21xx and LPC22xx series represent early members of NXP's LPC2000 family of ARM-based microcontrollers, designed for cost-effective embedded applications requiring moderate processing power. These devices are built around the ARM7TDMI-S core, a 16/32-bit RISC processor operating at up to 60 MHz for flash-based variants or 75 MHz for flashless models. The LPC21xx subfamily targets simpler designs with on-chip flash memory ranging from 32 kB to 256 kB and SRAM from 8 kB to 32 kB, while the LPC22xx extends this with support for external memory interfaces, offering up to 256 kB flash or flashless configurations paired with 16 kB to 64 kB SRAM. Both support (ISP) and In-Application Programming (IAP) via a built-in , enabling field updates without specialized hardware. Key integrated peripherals emphasize versatile I/O for control tasks, including two UARTs for , one I²C interface operating up to 400 kbit/s in modes, and two SPI ports for 8- to 16-bit data transfers. A 10-bit ADC with up to 8 channels (depending on package) handles analog inputs, complemented by a PWM unit providing six outputs suitable for and timing applications. These features make the series ideal for foundational embedded systems without needing external components for basic interfacing. Power management is optimized for low-energy operation at 3.3 V nominal supply (3.0 V to 3.6 V for I/O, 1.8 V core), with active-mode consumption around 40 mA at 60 MHz—equating to less than 1 mA/MHz—and power-down mode drawing under 10 µA at . Reliability is enhanced by an integrated for system monitoring and brown-out detection to prevent operation during voltage dips. Introduced between 2004 and 2005, the LPC21xx and LPC22xx series gained popularity in educational settings, such as with the LPC2103-based development boards for teaching architecture and peripherals, and in simple control applications like industrial sensors and consumer devices.

LPC1000 Series

LPC18xx and LPC17xx

The LPC17xx series represents NXP's high-performance ARM Cortex-M3-based microcontrollers designed for embedded applications requiring robust connectivity and processing capabilities. These devices feature a 32-bit ARM Cortex-M3 core operating at up to 100 MHz for most variants (LPC176x) or 120 MHz for the LPC1769, enabling efficient execution of complex control algorithms. Memory configurations include 128 KB to 512 KB of on-chip flash and 32 KB to 64 KB of SRAM, with some models supporting an external memory bus for additional expansion. Key integrated peripherals emphasize industrial and networking demands, such as two CAN 2.0B controllers for automotive and control networks, USB 2.0 OTG/full-speed host/device interfaces for connectivity, and Ethernet MAC (10/100 Mbps) on select models like the LPC1768 for networked applications. Clocking is managed via a high-frequency PLL supporting up to 120 MHz from a 1-25 MHz crystal oscillator or 4 MHz internal RC, ensuring stable operation in demanding environments. Introduced in 2008, the LPC17xx series targets applications like motor control, eMetering, and industrial networking. These devices are included in NXP's 15-year product longevity program, ensuring availability until at least 2038. Building on the LPC17xx foundation, the LPC18xx series advances performance with enhanced speed and for more intensive tasks such as and advanced networking. The Cortex-M3 core runs at up to 180 MHz, providing superior computational throughput compared to earlier models. options scale to 256 KB–1 MB of dual-bank flash, 64–136 KB of SRAM, and 16 KB of , complemented by an external bus interface () supporting up to 1 GB of external for flexible expansion. Peripherals are optimized for high-speed integration, including 10/100 Ethernet MAC with IEEE 1588 timing support, two high-speed USB 2.0 interfaces (one OTG), two CAN 2.0B controllers, and a Quad SPI Flash Interface (SPIFI) enabling up to 52 MB/s data rates for rapid code execution from external storage. Clock generation utilizes three PLLs and a 1–25 MHz to achieve the 180 MHz clock, with a 12 MHz internal RC for initialization. Announced in , the LPC18xx series suits high-demand control in industrial automation, RFID readers, and networked devices. These devices are included in NXP's product longevity program.
FeatureLPC17xxLPC18xx
Core ClockUp to 120 MHzUp to 180 MHz
128–512 KB256 KB–1 MB
SRAM32–64 KB64–136 KB
Key Peripherals2x CAN, USB OTG, Ethernet (select)2x CAN, 2x HS USB, Ethernet, Quad SPI
External BusLimited (select models) up to 1 GB
Target Applications, eMetering, advanced networking

LPC15xx to LPC11xx

The LPC15xx to LPC11xx devices form the entry-level segment of NXP's LPC1000 series, emphasizing ultra-low-power operation and cost-effective 32-bit processing for embedded systems such as sensors, gadgets, and industrial controls. These microcontrollers, introduced progressively from 2010 to 2013, build on the LPC1000 by prioritizing in core performance, memory, and peripherals to suit battery-constrained and space-limited applications. The LPC11xx subfamily debuted in late 2009 with the broader LPC1100 launch, followed by USB-enhanced variants in 2011 and the LPC15xx in 2013, enabling widespread adoption in low-end designs requiring deterministic real-time response without the overhead of higher-end M4 cores. At the core, the LPC11xx, LPC12xx, and LPC13xx integrate the ARM Cortex-M0 processor running at up to 50 MHz, delivering efficient instruction execution for tasks like and basic control loops while minimizing code size compared to legacy 8/16-bit architectures. The LPC15xx upgrades to the Cortex-M3 core at up to 72 MHz, incorporating features like hardware multiply and nested vectored interrupts for more demanding algorithms, such as or data encryption, without exceeding low-power envelopes. The LPC11Uxx extension adds a full-speed USB 2.0 device controller with on-chip PHY, facilitating plug-and-play connectivity in human-interface devices and data loggers. Memory provisions scale from 8 KB flash and 4 KB SRAM in base LPC11xx models to 256 KB flash, 36 KB SRAM, and 4 EEPROM in the LPC15xx, supporting firmware storage, runtime variables, and persistent configuration data respectively. The LPC11Axx variant enhances analog integration with up to 4 EEPROM and an 8-channel 10-bit ADC for applications like . Similarly, the LPC11Cxx includes a (CRC) engine supporting polynomials like CRC-16 and CRC-32 to verify in serial transmissions. The LPC11E subfamily embeds EEPROM directly for simplified non-volatile storage in cost-sensitive nodes. Peripheral integration tailors these devices for diverse interfaces: the LPC13xx supports Fast-mode Plus I²C at 1 Mbit/s with multiple address recognition for rapid networks, while the LPC12xx features two analog comparators with programmable thresholds and output feedback for voltage detection in circuits. LPC11xx options include miniature packages like 20-pin SOIC and TSSOP for compact assemblies in wearables or IoT modules. Power profiles underscore their suitability for battery operation, with the Cortex-M0 drawing under 0.5 mA/MHz in active mode at 3.3 V and dropping to below 1 µA in deep-sleep or deep power-down modes via integrated (PMU). This efficiency propelled the LPC11xx, particularly the LPC11U24, into popular use for USB-enabled, low-power wearables and portable prototypes during the early .

LPC800 Series

LPC80x

The LPC80x family comprises the entry-level, ultra-compact variants of the LPC800 series, optimized for minimal size, low cost, and battery-powered applications such as nodes and simple IoT edge devices. These microcontrollers emphasize power efficiency and integration in constrained environments, distinguishing them from larger siblings by limiting peripherals to essentials while supporting for flexible deployment. Introduced around 2013, the LPC80x targets designs requiring basic processing without excess resources, enabling migration from 8-bit MCUs to 32-bit architectures at comparable cost. At the heart of the LPC80x is the Arm Cortex-M0+ processor core (revision r0p1), clocked at up to 15 MHz, which delivers efficient performance for lightweight tasks through features like low-latency handling and sleep modes that reduce dynamic power draw. The core's design prioritizes energy savings, making it suitable for always-on sensing applications. Memory options include 16 KB or 32 KB of on-chip flash for program storage, which is reprogrammable in-system via the built-in , paired with 2 KB or 4 KB of SRAM for data handling; for instance, the LPC802 offers the smaller 16 KB flash and 2 KB SRAM configuration, while the LPC804 provides the larger 32 KB flash and 4 KB SRAM. Peripheral integration focuses on fundamental connectivity and monitoring, including up to two USART interfaces for asynchronous serial communication, up to two I²C-bus interfaces operating at speeds to 400 kbit/s, and one SPI controller for synchronous data exchange. Analog capabilities are provided by a single 12-bit ADC with up to 12 channels and sample rates of 480 KS/s, enabling precise signal acquisition, alongside a windowed for reliable system monitoring and reset. These features support direct interfacing with sensors and actuators without external components, streamlining development for low-complexity systems. Packaging emphasizes compactness, with options in 16- to 33-pin formats such as WLCSP (wafer-level chip-scale package) for the tiniest footprints (e.g., 1.9 mm × 1.6 mm) and TSSOP for easier handling, alongside HVQFN for balanced thermal performance. includes multiple modes—sleep, , power-down, and —with the latter achieving typical consumption of 0.15 µA at 25 °C and 3.3 V supply, allowing extended battery life in dormant states while enabling fast wake-up (around 300 µs) via pin activity or timers. Operating from 1.71 V to 3.6 V, the LPC80x suits single- or dual-supply designs in portable and embedded contexts.

LPC81x

The LPC81x family represents a feature-rich subset of NXP's LPC800 series, designed for general-purpose applications requiring enhanced peripheral integration and low-cost 32-bit processing. These microcontrollers are based on the Arm Cortex-M0+ core, operating at up to 30 MHz, which provides efficient performance for embedded tasks while supporting enhanced debug capabilities such as Serial Wire Debug (SWD) and JTAG boundary scan, along with multiple low-power sleep modes including sleep, deep-sleep, power-down, and deep power-down to optimize energy consumption. Introduced in 2014 as part of NXP's push toward accessible Cortex-M0+ solutions, the LPC81x series saw updates like the LPC82x by around 2014-2020 for greater peripheral density and memory, targeting applications in simple control systems, LED lighting, energy metering, and sensor interfaces. Memory configurations in the LPC81x family vary by variant, with the base LPC81x models offering up to 16 KB of on-chip and 4 KB of SRAM, while the higher-integration LPC82x extension doubles these to 32 KB flash and 8 KB SRAM, enabling more complex without external components. A key feature is the support for flash read-while-write operations through In-Application Programming (IAP) and (ISP), allowing code updates without halting execution. The family emphasizes versatile integration, including an analog comparator for , multiple s such as the multi-rate timer (MRT), state-configurable /PWM (SCTimer), windowed (WWDT), and self-wake-up (WKT), as well as flexible GPIO with up to 29 pins supporting configurable pull-up/pull-down resistors, open-drain modes, interrupts, and high-current drive (up to 20 mA on certain pins). Packages range from compact TSSOP20 and HVQFN33 options, ensuring pin compatibility across variants for scalable designs.

Legacy Series

LPC900 Series

The LPC900 series comprises a family of low-cost, 8-bit microcontrollers from (formerly Semiconductors), built around an accelerated two-clock 80C51-compatible core that executes instructions in reduced clock cycles for improved performance over traditional 80C51 devices. The core operates at up to 18 MHz using an external , enabling efficient handling of basic embedded tasks while maintaining compatibility with legacy 80C51 software and tools. Some variants support an internal RC oscillator for simpler designs, though external clocks provide the highest speeds. Memory configurations in the LPC900 series emphasize flexibility for small-scale applications, with on-chip ranging from 1 kB to 16 kB that is byte-erasable and supports (ISP) and in-application programming (IAP) for field updates without specialized hardware. Data RAM is typically 128 to 256 bytes, sufficient for stack and variable storage, while higher-end models like the P89LPC935 and P89LPC936 include an additional 512 bytes of auxiliary RAM. options up to 512 bytes are available in select devices for non-volatile data storage, such as serialization codes, with endurance ratings of 100,000 erase/write cycles. In-circuit programming is facilitated through a serial interface, allowing reprogramming via standard connectors without removing the device from the board. Key integrated peripherals simplify system design by reducing external components, including an enhanced UART with fractional baud rate generation and break detection for , a 400 kHz interface for peripheral connectivity, and two 16-bit timers/counters that support PWM, functions, and capture/compare modes. Brown-out detection circuitry monitors supply voltage (2.4 V to 3.6 V range) and can trigger a reset or to protect against power glitches, enhancing reliability in unstable environments. Additional features like and a with oscillator fail detection further support robust operation. The series is housed in compact, cost-effective packages such as 8-pin to 44-pin DIP, PLCC, TSSOP, and LQFP, with pin counts scaling from basic 20-pin DIP/PLCC for minimal I/O to 44-pin options for more GPIO and peripherals, making it suitable for legacy upgrades in space-constrained designs. Introduced in the early , the LPC900 series found use in simple appliances like vacuum cleaners and handheld devices, as well as early PC interfaces requiring low-power, high-integration control.

LPC700 Series

The LPC700 series represents Philips Semiconductors' (now NXP) early entry into 8-bit microcontrollers, based on an accelerated version of the 80C51 core. These devices were designed for cost-sensitive, high-volume applications requiring minimal external components, with the core executing instructions at twice the speed of a standard 80C51, achieving cycle times of 300–600 ns. Introduced in the late , the series emphasized one-time programmable (OTP) variants alongside mask-programmed options to enable flexible production without the need for full mask ROM customization. Memory configurations in the LPC700 series typically include 1–4 KB of mask ROM or OTP for program storage, paired with 128–256 bytes of on-chip RAM for data and stack operations. For example, the P87LPC762 model provides 2 KB OTP and 128 bytes RAM, while higher-end variants like the P87LPC764 offer 4 KB OTP with the same RAM size, sufficient for simple control tasks without external . The OTP mechanism allows end-users to program the device once during , bridging the gap between fixed mask ROM and more advanced reprogrammable technologies. Peripherals are kept minimal to maintain low cost and pin efficiency, featuring a full-duplex UART for , basic quasi-bidirectional I/O ports, two 16-bit timers/counters, and an interface for peripheral connectivity. Additional elements include two analog comparators for simple , a for reliability, and up to eight keypad interrupt inputs, tailored for direct interfacing with low-pin-count systems like PC add-ons. The core supports operation at 12 MHz in standard configurations, scalable to 20 MHz at higher voltages (4.5–6.0 V), with low-power modes (idle and power-down) to extend battery life in portable devices. Packaging options focus on compact, cost-effective formats such as 14-pin and 20-pin PDIP and SOIC, to suit low I/O needs while targeting a bill-of-materials cost under $1 in volume. This design philosophy prioritized integration for peripherals and embedded controls, making the LPC700 series a foundational legacy line before the shift to flash-based and architectures in later families.

Development Resources

Software Tools

The MCUXpresso IDE is an Eclipse-based provided free of charge by NXP for developing applications on LPC microcontrollers and other Cortex-M-based devices. It includes built-in code generation capabilities through integrated configuration tools for peripherals, pins, clocks, and , streamlining and initialization. The IDE supports debugging features such as breakpoints, watchpoints, and real-time variable monitoring, with seamless integration for real-time operating systems including and Zephyr. The MCUXpresso SDK serves as a comprehensive software enablement package for LPC series, offering a collection of open-source peripheral drivers, middleware stacks for protocols like USB and Ethernet, and over 300 example applications tailored to various LPC families such as LPC55xx and LPC18xx. Developers can customize the SDK using the online SDK Builder tool to select specific components, ensuring compatibility across series while reducing development time through pre-integrated and board support packages. The SDK is available for download and hosted on for community contributions and . Supported compilers in the MCUXpresso ecosystem include the GNU GCC toolchain integrated directly into the IDE, as well as compatibility with IAR Embedded Workbench and Keil MDK for professional development. For advanced LPC series like the LPC5500, which support TrustZone for secure/non-secure execution, the tools provide specialized linker scripts and build configurations to manage partitioned memory and secure boot processes. These compilers enable optimized code generation for Cortex-M4 and M33 cores common in LPC devices. Debugging for LPC microcontrollers is facilitated through and SWD interfaces using NXP's LPC-Link or MCU-Link probes, alongside third-party options like P&E Micro Multilink and SEGGER . The IDE supports trace capabilities for instruction and data profiling on Cortex-M4 and M33 cores, allowing for performance analysis and optimization without halting execution. These tools integrate with the SDK for on-target of drivers and applications. Following NXP's 2015 merger with Freescale Semiconductor, the LPCXpresso IDE was unified and rebranded as MCUXpresso in 2017, consolidating tools across LPC and other MCU portfolios into a single ecosystem for enhanced interoperability. As of November 2025, updates to MCUXpresso include integration with NXP's eIQ AI software toolkit, enabling edge AI development on LPC devices through neural network compilers, inference engines, and generative AI flows for applications like time-series machine learning. The latest IDE version, 25.09, incorporates improved configuration tools and open-source CMSIS packs for broader compatibility.

Evaluation Boards

NXP offers a range of low-cost LPCXpresso development boards designed for and evaluation of its LPC series, featuring integrated debug probes and compatibility with expansion options. These boards typically include onboard CMSIS-DAP debug interfaces for seamless integration with tools like MCUXpresso IDE, enabling quick code deployment and testing without external hardware. Series-specific examples include the LPCXpresso55S69-EVK, which supports secure evaluation of the LPC55S6x family with Cortex-M33 cores and enhanced security features like secure boot and crypto acceleration. Similarly, the LPCXpresso54628 board targets applications in the LPC546xx series with a Cortex-M4 processor for high-performance tasks such as and connectivity. For versatile prototyping across older series, LPCXpresso base boards from partners like Embedded Artists allow compatibility with multiple target modules, such as those for LPC17xx and LPC40xx families, and include Rev3 shield connectors for easy peripheral expansion. Specialized boards cater to IoT applications, exemplified by the LPCXpresso55S28-EVK, which integrates audio subsystems, accelerometers, and connectivity options for and sensor-based designs in the LPC55S2x series. The LPC54018 IoT module, developed in partnership with Embedded Artists, provides a compact, self-contained solution with built-in and (BLE) support based on the LPC54018 MCU, suitable for standalone or baseboard-mounted prototyping. Common features across these boards include expansion headers for GPIO, I2C, SPI, and UART access, as well as preloaded sensors and peripherals to facilitate immediate development of applications like or human-machine interfaces. Integrated debug probes, such as Link2 on newer models, support high-speed USB communication, serial wire output (SWO) for tracing, and virtual COM ports for data logging. In the community ecosystem, third-party boards like mbed-enabled platforms for the LPC1768 continue to be popular for legacy projects.

References

Add your contribution
Related Hubs
User Avatar
No comments yet.