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3 nm process
3 nm process
3 nm process
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In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5 nm MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its 3 nm gate all around (GAA) process, named 3GAA, in mid-2022.[1][2] On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node (N3) was underway with good yields.[3] An enhanced 3 nm chip process called "N3E" may have started production in 2023.[4] American manufacturer Intel planned to start 3 nm production in 2023.[5][6][7]

Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3 nm process still uses FinFET (fin field-effect transistor) technology,[8] despite TSMC developing GAAFET transistors.[9] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[10] Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.[11]

Projected node properties according to International Roadmap for Devices and Systems (2021)[12]
Node
name		 Gate
pitch		 Metal
pitch		 Year
5 nm 51 nm 30 nm 2020
3 nm 48 nm 24 nm 2022
2 nm 45 nm 20 nm 2025
1 nm 40 nm 16 nm 2027

The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.[12]

However, in real world commercial practice, 3 nm is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[13][14] There is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node.[15] Typically the chip manufacturer refers to its own previous process node (in this case the 5 nm node) for comparison. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips.[16][17] On the other hand, Samsung has stated that its 3 nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process.[18] EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.[19]

History

[edit]

Research and technology demos

[edit]

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes.[20][21] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.[22][23]

Commercialization history

[edit]

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.[24]

In 2017, TSMC announced it was to begin construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan.[25] TSMC plans to start volume production of the 3 nm process node in 2023.[26][27][28][29][30]

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.[31]

In early 2019, Samsung presented plans to manufacture 3 nm GAAFET (gate-all-around field-effect transistors) at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7 nm.[32][33][34] Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm nodes.[35][36]

In December 2019, Intel announced plans for 3 nm production in 2025.[37]

In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.[38]

In August 2020, TSMC announced details of its "N3" process, which is new rather than being an improvement over its N5 process.[39] Compared with the N5 process, the N3 process should offer a 10–15% increase in performance, or a 25–35% decrease in power consumption, with a 70% increase in logic density, a 20% increase in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC was planning volume production in the second half of 2022.[40][needs update]

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process (previously named Intel 7+), the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.[5][needs update]

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers' first 3 nm-based chip designs in the first half of 2022, while its second generation of 3 nm is expected in 2023.[41][needs update]

In June 2022, at TSMC Technology Symposium, the company shared details of its N3E process technology scheduled for volume production in 2023 H2: 1.6× higher logic transistor density, 1.3× higher chip transistor density, 10–15% higher performance at iso power or 30–35% lower power at ISO performance compared to TSMC N5 v1.0 process technology, FinFLEX technology, allowing to intermix libraries with different track heights within a block etc. TSMC also introduced new members of 3 nm process family: high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications.[42][43][44]

In June 2022, Samsung started "initial" production of a low-power, high-performance chip using 3 nm process technology with GAA architecture.[1][45] According to industry sources, Qualcomm has reserved some of 3 nm production capacity from Samsung.[46]

On 25 July 2022, Samsung celebrated the first shipment of 3 nm Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi.[47][48][49][50] It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density,[51] 23% higher performance or 45% lower power draw compared to an unspecified 5 nm process technology.[52] Goals for the second-generation 3 nm process technology include up to 35% higher transistor density,[51] further reduction of power draw by up to 50% or higher performance by 30%.[52][53][51]

On 29 December 2022, TSMC announced that volume production using its 3 nm process technology N3 is underway with good yields.[3] The company plans to start volume manufacturing using refined 3 nm process technology called N3E in the second half of 2023.[54]

In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their 3 nm process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm2 for N3 and 0.021 μm2 for N3E (same as in N5). For N3E process, depending on the number of fins in cells used for design, area scaling compared to N5 2–2 fin cells ranges from 0.64x to 0.85x, performance gains range from 11% to 32% and energy savings range from 12% to 30% (the numbers refer to Cortex-A72 core). TSMC's FinFlex technology allows to intermix cells with different number of fins in a single chip.[55][56][57][58]

Reporting from IEDM 2022, semiconductor industry expert Dick James stated that TSMC's 3 nm processes offered only incremental improvements, because limits have been reached for fin height, gate length, and number of fins per transistor (single fin). After implementation of features such as single diffusion break, contact over active gate and FinFlex, there will be no more room left for improvement of FinFET-based process technologies.[59]

In April 2023, at its Technology Symposium, TSMC revealed some details about their N3P and N3X processes the company had introduced earlier: N3P will offer 5% higher speed or 5–10% lower power and 1.04× higher "chip density" compared to N3E, while N3X will offer 5% speed gain at the cost of ~3.5× higher leakage and the same density compared to N3P. N3P is scheduled to enter volume production in the second half of 2024, and N3X will follow in 2025.[60]

In July 2023, semiconductor industry research firm TechInsights said it has found that Samsung's 3 nm GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT.[61]

On 7 September 2023, MediaTek and TSMC announced that MediaTek have developed their first 3 nm chip, volume production is expected to commence in 2024.[62]

On 22 May 2025, Xiaomi announced its first 3 nm chip XRING O1, volume production under TSMC N3E process, equipped on its Xiaomi 15S Pro phone and Xiaomi Pad 7 Ultra.[63][64]

3 nm process nodes

[edit]
Samsung[41][65][66][67] TSMC[68] Intel[5]
Process name 3GAE
SF3E 		3GAP
SF3 		N3
(a.k.a. N3B)[69] 		N3E N3P N3X N3C 3
Transistor type MBCFET FinFET
Transistor density (MTr/mm2) 150[66] 190[70] 197[44] 216[71] 224[72] Unknown 143.37[73]
SRAM bit-cell size (μm2) Unknown Unknown 0.0199[57] 0.021[57] Unknown Unknown Unknown 0.024[74]
Transistor gate pitch (nm) 40 Unknown 45[57] 48[71] Unknown Unknown Unknown 50[73]
Interconnect pitch (nm) 32 Unknown Unknown 23[57] Unknown Unknown Unknown 30[73]
Release status 2022 risk production[41]
2022 production[1]
2022 shipping[2] 		2024 Q1 risk production[75]
2024 H2 production[70] 		2021 risk production
2022 Q4 volume production[68][3][76]
2023 H1 shipping for revenue[77] 		2023 Q4 production[68][76] 2024 H2 production[60] 2025 H2 production[60] 2026 production [78] 2024 H1 product manufacturing[79]
2024 H2 shipping for revenue[80]

References

[edit]

Further reading

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

3 nm process

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from Grokipedia
The 3 nm process is a semiconductor manufacturing technology node that represents a major advancement in integrated circuit fabrication, enabling transistors with critical dimensions scaled to around 3 nanometers for higher density, enhanced performance, and reduced power consumption compared to the preceding 5 nm node. This node, while not literally measuring all features at 3 nm, serves as a generational marker for process improvements in logic scaling, typically achieving 25-35% lower power usage or 10-15% higher performance at the same power, alongside up to 1.7 times greater transistor density. Leading foundries like TSMC, Samsung, and Intel have commercialized variants of the 3 nm process, with TSMC's 3nm contributing about 23% of its revenue by Q3 2025, powering high-end applications in mobile devices, servers, and AI accelerators. TSMC's N3 family, including enhancements like N3E and N3P, utilizes (FinFET) architecture as its last major iteration before transitioning to gate-all-around (GAA) at smaller nodes, with beginning in late 2022 and high-volume yields nearly 90% by mid-2025. 's 3 nm process, branded as SF3, employs multi-bridge-channel FET (MBCFET) GAA nanosheet transistors for superior channel control and scaling, entering production in June 2022 with reported improvements of 45% reduced power, 23% higher performance, and 16% smaller area over its 5 nm node, though yields have lagged at around 50-60% as of mid-2025. 's Intel 3 process, also FinFET-based, delivers an 18% performance-per-watt gain over its Intel 4 node (equivalent to a 5 nm-class process) and entered high-volume in 2024, targeting datacenter and with support for 1.2V operations and denser libraries. These processes mark a critical tipping point for evolution, as FinFETs approach physical limits in controlling short-channel effects and leakage, prompting the shift to GAA structures for future nodes while enabling denser interconnects at pitches like 48 nm contacted poly and 22 nm metal. Notable implementations include Apple's A17 Pro, M4, and A18 chips on TSMC's N3, Samsung's 2500 processor on SF3, and Intel's 6 server CPUs on Intel 3, underscoring the node's role in driving efficiency for energy-intensive AI and mobile workloads.

History

Early research and development

The progression toward the 3 nm process was foreshadowed by the International Technology Roadmap for Semiconductors (ITRS) editions from 2011 to 2015, which outlined escalating challenges in scaling CMOS transistors from 5 nm and larger nodes. These roadmaps predicted that sub-5 nm dimensions would encounter severe short-channel effects, increased leakage currents, and limitations in classical planar and early FinFET architectures, necessitating innovations in device structures and materials to sustain performance gains. By 2015, the ITRS emphasized the urgency of transitioning to multi-gate devices like gate-all-around (GAA) transistors to improve electrostatic control and enable continued density scaling beyond 5 nm. Research milestones in the mid-2010s focused on evolving FinFETs toward GAAFET concepts, particularly through lab demonstrations of nanowire and nanosheet architectures. researchers first introduced the stacked nanosheet GAAFET in 2015 as a viable path for sub-5 nm scaling, offering superior gate control over FinFETs by fully surrounding the channel with the gate dielectric. Building on this, advanced the technology with 2016 demonstrations of lateral nanowire GAA MOSFETs at scaled dimensions below 20 nm, highlighting their potential for ultimate scaling with reduced variability and enhanced drive currents. By 2018, reported further refinements in stacked nanowire GAA transistors, achieving improved Ion/Ioff ratios and suppression suitable for 3 nm nodes and beyond. Early material innovations in the laid groundwork for 3 nm viability by addressing gate stack and patterning limitations inherited from larger nodes. High-k metal gate (HKMG) stacks, initially commercialized at 45 nm, underwent extensive refinement during this decade for FinFET integration and GAA compatibility, enabling equivalent oxide thicknesses below 1 nm while minimizing quantum tunneling and threshold voltage variability at sub-5 nm scales. Concurrently, precursors to (EUV) were tested in research settings, with developments in 13.5 nm wavelength sources and photoresists demonstrating sub-20 nm resolution and overlay precision under 5 nm, critical for single-exposure patterning in dense 3 nm layouts. Specific lab prototypes underscored these advancements' feasibility. In 2016, showcased 3 nm-class GAA prototypes using channels, validating multi-gate control for high-mobility channels at aggressive pitches. Complementing this, TSMC's 2018 research on EUV integration confirmed its viability for 3 nm processes, with demonstrations of enhanced light-source power and multi-layer patterning that supported faster development cycles and reduced multi-patterning complexity compared to 5 nm approaches.

Technology demonstrations and announcements

In December 2019, presented a short course at the International Electron Devices Meeting (IEDM) outlining device technologies for 3 nm and beyond, including EUV lithography integration for enhanced scaling and initial test chip concepts demonstrating feasibility for high-density logic and SRAM structures. Building on this, advanced its 3 nm development in 2020 with EUV-based test chips entering risk production, validating key process modules like multi-patterning and contact gate pitch scaling to achieve up to 1.7x density over the 5 nm node while maintaining yield targets. In January 2020, Samsung announced the fabrication of the world's first 3 nm gate-all-around FET (GAAFET) prototype using its multi-bridge-channel FET (MBCFET) architecture, which demonstrated a 30% transistor density improvement over its 5 nm process through better channel control and reduced short-channel effects. In July 2021, Intel revealed RibbonFET, its implementation of gate-all-around transistor technology, as part of the Intel 20A process node—equivalent to a 3 nm class—aimed at delivering superior drive current and electrostatic integrity compared to FinFETs, with initial prototypes showing enhanced performance-per-watt metrics. Concurrently, TSMC and Arm collaborated on 3 nm test vehicles, culminating in a successful tape-out of a test chip validating Armv9 physical IP, which included silicon results confirming robust power delivery networks with low IR drop and up to 10-15% efficiency gains in high-performance computing blocks. At IEDM 2022, showcased a 3 nm-class nanosheet FET device, highlighting the architecture's potential for low-power applications through precise nanosheet width control and inner-spacer optimization. During the 2022 TSMC Technology Symposium, demonstrated the N3E process variant with FINFLEX for flexible cell architectures while preserving compatibility with existing FinFET flows.

Commercialization timeline

TSMC initiated risk production of its 3 nm N3 process in 2021, marking the early stages of ahead of high-volume . This was followed by the start of high-volume for N3 in the second half of 2022, with the process entering production for Apple's A17 Pro chip in and applications by late 2023. began high-volume of its first-generation 3 nm gate-all-around (GAA) process in mid-2022, initially targeting the series, though persistent yield challenges limited its adoption. In 2023, ramped up its enhanced N3E variant, which saw its first with for a Dimensity , enabling broader integration by 2024. encountered significant yield issues with its 3 nm process during 2022-2023, reportedly below 20% initially, prompting major customers like to shift orders to 's more reliable N3 platform. Intel's equivalent 20A process, planned as a 2 nm-class node, faced delays and was ultimately canceled for consumer production in 2024, with manufacturing shifted to external foundries like . By 2024, advanced to trial production of its second-generation 3 nm SF3 process, aiming for in the second half of the year to address prior yield shortcomings. In May 2025, announced its in-house XRING O1 chipset, fabricated on 's N3E node, representing a key milestone in diversified 3 nm adoption for mobile processors. Market events included Technologies' of a 3D IC test chip integrating 3 nm and 5 nm dies in September 2025, validating ecosystem readiness for advanced packaging. further expanded 3 nm capacity in 2025, driven by AI chip demand from , increasing monthly wafer output to support growth. In early 2025, 's Intel 3 process entered high-volume manufacturing, targeting datacenter applications with 6 processors.

Technology

Key innovations in transistor design

The 3 nm process involves advancements in architecture, with some implementations shifting from fin field-effect (FinFETs) to gate-all-around (GAA) nanosheet field-effect (FETs) to enable continued scaling beyond the limitations of FinFETs at sub-5 nm nodes. Other implementations, such as TSMC's N3 family and 's Intel 3, refine FinFET designs through optimizations like narrower pitches (around 24-26 nm) and higher aspect ratios to enhance electrostatic control and reduce short-channel effects without transitioning to GAA. In GAA nanosheet FETs, the channel is formed by multiple horizontally stacked silicon nanosheets, typically 3 to 5 layers thick, with the gate material fully encircling each nanosheet on all four sides. This all-around gate configuration provides enhanced electrostatic control over the channel, significantly reducing short-channel effects such as drain-induced barrier lowering and leakage currents compared to the partial gate wrapping in FinFETs. The stacked nanosheet design also allows for tunable device characteristics by varying the number and dimensions of the sheets, optimizing drive strength while maintaining compact footprints suitable for 3 nm densities. Key implementations of GAA technology at 3 nm include Samsung's multi-bridge-channel FET (MBCFET), which employs stacked horizontal nanosheets as the conductive channels, enabling precise adjustment of channel width for balanced power, performance, and area (PPA) metrics. In MBCFET, the nanosheet structure facilitates higher through parallel conduction paths across the bridges, with demonstrated improvements of 23% in performance and 45% in power efficiency over preceding 5 nm FinFET-based processes. TSMC's N3X variant incorporates a backside power delivery network (BSPDN), relocating power rails to the wafer's underside to minimize IR drop and improve in high-performance applications, thereby supporting higher operating voltages up to 1.2 V without compromising frontside routing density. Interconnect innovations at 3 nm address rising resistance in narrow lines by adopting ruthenium-cobalt (Ru/Co) bilayer liners, which reduce liner thickness by up to 33% while enhancing wettability and void-free filling. These liners lower overall interconnect resistance by approximately 14% at pitches below 20 nm, mitigating RC delay increases that plague traditional tantalum-based barriers. To achieve such tight interconnect dimensions, (EUV) lithography with multi-patterning techniques, such as self-aligned litho-etch processes, enables metal pitches as low as 24 nm, ensuring precise patterning of backend-of-line (BEOL) layers without excessive overlay errors. The scaling benefits of GAA nanosheet FETs are quantified through the effective channel width, defined as
Weff=2×(W+H)×NW_{\text{eff}} = 2 \times (W + H) \times N
where WW is the nanosheet width, HH is the nanosheet thickness (or height), and NN is the number of stacked nanosheets. This formulation allows designers to boost drive current by increasing NN or sheet dimensions, yielding up to a 30% improvement in on-state current over equivalent FinFET structures at iso-area conditions, primarily due to enhanced gate-to-channel coupling and reduced source/drain resistance.

Manufacturing processes and equipment

The manufacturing processes for the 3 nm semiconductor node involve a complex sequence of fabrication steps tailored to achieve atomic-scale precision in transistor structures, particularly for FinFET or gate-all-around (GAA) architectures. The process flow begins with wafer preparation, followed by critical patterning, deposition, , and planarization stages. Key among these is the use of (EUV) with double-patterning techniques to define fine features such as fins and gates. In EUV double-patterning, two sequential exposures and etches are employed to resolve pitches below 30 nm, enabling the formation of multi-fin structures essential for 3 nm density. This approach is necessary because single-exposure EUV at 0.33 (NA) reaches its resolution limits around 28-30 nm pitches, requiring multi-patterning for tighter dimensions in logic devices. Deposition processes play a pivotal role in building the gate stack and source/drain regions. Atomic layer deposition (ALD) is widely used to apply high-k dielectrics, such as hafnium oxide (HfO₂), which provide superior while minimizing leakage currents compared to traditional SiO₂. ALD enables conformal, sub-nanometer-thick layers by sequentially introducing precursors and reactants in a self-limiting manner, ensuring uniform coverage on high-aspect-ratio features like fins. Following deposition, selective removes excess material to shape the structures, often using plasma-based dry etch techniques for anisotropic profiles. (CMP) then achieves global planarization, smoothing the wafer surface after metal or dielectric fills to prepare for subsequent layers; this step is repeated multiple times in the back-end-of-line (BEOL) interconnect formation to maintain topography control within nanometers. Specialized equipment underpins these processes, with dominated by ASML's TWINSCAN NXE:3600D EUV systems, which support high-volume production at the 3 nm node through enhanced source power (up to 250 W) and overlay accuracy below 1.3 nm. These low-NA (0.33) scanners, introduced in the early 2020s, enable over 20 EUV layers in 3 nm flows, balancing resolution and throughput at around 185 wafers per hour. For deposition and etch, provides integrated tools like the Endura platform for ALD and the Centura for plasma etch, optimized for sub-3 nm scaling with features such as in-situ cleaning to prevent in high-k/ modules. These systems facilitate atomic-precision control, supporting the "angstrom-era" transitions beyond 3 nm. To enhance yields, advanced integrates e-beam tools that detect defects down to 1-3 nm, such as those from EUV effects or residue in fins. Systems like KLA's eSL10 or ASML's HMI eScan 1000 use multi-beam sources for high-throughput scanning, identifying killer defects that optical tools overlook and enabling process corrections in real-time. Thermal budget management is equally critical, involving low-temperature anneals (below 800°C) and millisecond spiking to activate dopants without excessive , which could degrade short-channel control in 3 nm FinFETs. This constrains overall process temperatures to preserve junction abruptness and minimize variability. Addressing mask fabrication challenges, multi-beam e-beam (MBM) writers, such as IMS Nanofabrication's MBMW-101 or JEOL's systems, reduce cycle times for complex EUV to approximately 10-20 hours per write, compared to over 30 hours with single-beam tools. This improvement supports the high pattern fidelity required for 3 nm, where must resolve features with sub-1 nm uniformity to avoid overlay errors in double-patterning.

Process variants

TSMC N3 family

The TSMC N3 family comprises a series of 3 nm-class process nodes based on FinFET , designed to optimize power, , and area (PPA) for diverse applications ranging from mobile devices to (HPC). The baseline N3 process, also known as N3B, entered high-volume production in late , delivering approximately 10-15% higher and 25-30% lower power consumption compared to the preceding N5 node, with a logic around 290 MTr/mm². The N3E variant, an enhanced iteration, began volume production in late 2023 and focuses on improved manufacturability through reduced EUV layers and greater design flexibility, achieving yields comparable to mature nodes while maintaining strong PPA metrics; it supports a height of 6 tracks and a logic density of approximately 300 MTr/mm². Subsequent enhancements include N3P, an optical shrink of N3E that entered production in late 2024, providing a 5% performance uplift at the same power level and enhanced transistor density while preserving IP compatibility. N3X, targeted for HPC applications with risk production starting in 2024, emphasizes high-voltage operation and performance optimization, enabling up to 4% speed gains or 7% power reduction relative to N3E under specific conditions. A key architectural feature across the N3 family is FinFlex technology, which enables mixing of standard cells with varying fin configurations (such as 1-fin, 2-fin, or 3-fin layouts) within the same design, offering GAA-like versatility for balancing performance and power without requiring a complete redesign. This approach supports alternating row heights, typically 6-7 tracks, to optimize density and efficiency. In 2025, the N3 family, particularly N3E, saw expanded adoption, including volume production for Xiaomi's XRING O1 chipset, a 3 nm mobile SoC with 19 billion transistors. Overall, 3 nm processes contributed about 23-24% of TSMC's total wafer revenue in 2025, reflecting full driven by demand for advanced nodes.

Samsung 3 nm process

's 3 nm process represents a significant advancement in manufacturing, leveraging gate-all-around (GAA) technology through its proprietary Multi-Bridge Channel FET (MBCFET) , which enables superior channel control and electrostatic integrity compared to FinFET designs. This approach stacks multiple nanosheet channels vertically around the gate, mimicking 3D density benefits to enhance drive current while mitigating short-channel effects at advanced nodes. of the initial 3 nm variant, designated as 3GAE, commenced in mid-2022, delivering up to 45% lower power consumption, 23% higher performance, and 16% reduced die area relative to the preceding 5 nm low-power plus (LPP) process. The process lineup has evolved with second-generation offerings to address performance and efficiency demands. SF3 (also known as 3GAP), entering trial production in early 2024 and volume ramp in the second half of 2024, incorporates design optimizations for improved density and power delivery, achieving approximately 190 million s per square millimeter. This variant provides a 10-15% area reduction over 5 nm LPP implementations through refined layout rules and GAA scaling. Building on this, SF3P (3GAP+), introduced in 2024, offers a 22% performance uplift at iso-power compared to 4 nm-class nodes, while maintaining power consumption levels akin to 5 nm processes, making it suitable for high-efficiency mobile applications. Looking ahead, is preparing its SF2 process, a 2 nm-class node slated for starting in 2025, which promises further refinements in GAA architecture for mobile and . Early production of the 3 nm family faced challenges, including initial yield rates below 20% due to complexities in GAA fabrication and multi-patterning . However, by late 2025, yield improvements—reaching around 50%—have enabled stable output for key designs, such as the 2500 application processor, set for integration into 2025 mobile devices. By October 2025, further yield gains allowed securing foundry orders for Tesla's AI5 chip. These advancements are supported by a $17 billion in advanced node facilities through 2025, including expansions in to bolster capacity. To enhance reliability, incorporates advanced interconnect materials like cobalt liners in select layers, improving resistance in high-current paths.

Intel and other implementations

Intel's implementation of 3 nm-class process technology centers on its Intel 18A node, following the cancellation of the Intel 20A node in 2024 for consumer products such as Arrow Lake processors, which shifted to external foundries like . Intel 18A adopts angstrom-era nomenclature and integrates RibbonFET gate-all-around (GAA) s alongside PowerVia backside power delivery (BSPDN) to enhance performance, power efficiency, and density. The Intel 18A node achieves densities roughly 2.4 times greater than Intel 7 (approximately 100 MTr/mm² to around 240 MTr/mm²), establishing approximate equivalence to contemporary 3 nm processes. Intel 18A supports versatile standard cell architectures, such as 4-track configurations optimized for mobile density and 8-track variants suited for server performance requirements. Test chip tape-outs for 20A commenced in 2023 as part of earlier development, while Intel 18A achieved initial silicon validation in 2024, paving the way for volume production in 2025. By 2025, Intel deployed Intel 18A for Panther Lake mobile processors, succeeding the generation and representing the node's debut in consumer silicon. To bolster capacity during internal ramps, Intel Foundry Services forged partnerships, including with , to offer external manufacturing options for select designs. Other 3 nm implementations remain niche, with conducting only exploratory work before pivoting to specialty and mature nodes beyond 12 nm in 2018, citing market focus over leading-edge scaling. Imec provides an open pathfinding process design kit (PDK) for sub-3 nm nodes, facilitating academic research into advanced designs and bridging educational efforts with industrial innovation. In , Corporation initiated pilot production of its 2 nm-class process in 2025 at a facility, aiming for mass production by 2027 as part of a government-backed initiative to reestablish domestic advanced manufacturing.

Performance and economics

Transistor density and scaling benefits

The 3 nm process achieves transistor densities ranging from approximately 190 to 225 million transistors per square millimeter across major implementations, marking a significant advancement in integration over preceding nodes. For TSMC's N3 family, the baseline N3 process delivers up to a 1.6× logic density improvement compared to the 5 nm (N5) node, while the enhanced N3E variant provides a 1.3× density scaling for mixed-signal chips comprising 50% logic, 30% SRAM, and 20% analog content. Samsung's SF3 (3 nm GAA) process, in contrast, offers about a 1.15× density gain relative to its 5 nm FinFET, achieved through a 16% area reduction for equivalent functionality. These density gains extend by enabling continued scaling, primarily through architectural advancements that mitigate short-channel effects such as drain-induced barrier lowering. Samsung's adoption of gate-all-around (GAA) s at the 3 nm node fully encircles the channel, providing superior electrostatic control compared to FinFETs and allowing for tighter pitches without exacerbating leakage or variability. TSMC's N3, using enhanced FinFET, employs a contacted pitch of 45 nm, a reduction from 51 nm in N5, contributing to the observed scaling. Evaluations of nanosheet-based GAA demonstrate reduction in short-channel effects by up to 8% in effective drive current degradation during the transition from 5 nm to 3 nm. The scaling benefits can be conceptually modeled using the density scaling factor, approximated as (λoldλnew)2\left( \frac{\lambda_\text{old}}{\lambda_\text{new}} \right)^2, where λ\lambda represents the minimum half-pitch (e.g., for interconnects or gates). For the 3 nm node, λ\lambda is roughly 12 nm compared to about 20 nm for 5 nm, yielding a theoretical 2.78× density increase from pitch scaling alone, though practical factors like design rules temper this to 1.3–1.6× overall. This translates to a 25–30% area reduction for equivalent logic functionality versus 5 nm, allowing system-on-chips (SoCs) to integrate 15–20 billion transistors on feasible die sizes. Tighter pitches in 3 nm processes also enable reductions of 20–25% through innovations like self-aligned contacts and optimized nanosheet stacking, further supporting higher integration without proportional increases in interconnect delay. These improvements collectively sustain performance scaling, with GAA designs demonstrating enhanced channel control that preserves drive currents at scaled dimensions.

Power efficiency and yield considerations

The 3 nm process achieves significant power efficiency improvements over the preceding 5 nm node, primarily through architectural advancements and process optimizations, which enable better electrostatic control and reduced leakage. At iso-performance, these nodes deliver 25-30% lower power consumption compared to 5 nm equivalents, as reported by for its N3 family. Samsung's SF3 process similarly claims up to 45% power reduction versus its 5 nm baseline, though real-world implementations often align closer to the 25-35% range due to design optimizations and workload variations. A key contributor to these gains is the reduction in parasitic capacitance enabled by advanced structures; for GAA in Samsung's process, this surrounds the channel on all sides for superior gate control. Dynamic power dissipation in CMOS circuits follows the equation P=αCV2fP = \alpha C V^2 f, where α\alpha is the activity factor, CC is the total capacitance, VV is the supply voltage, and ff is the frequency; GAA designs lower CC by approximately 15% relative to FinFETs at 5 nm through minimized fringe and overlap effects. This capacitance scaling directly cuts power at constant voltage and frequency, amplifying overall efficiency in high-density logic. Yield considerations at 3 nm are critical for economic viability, with mature processes targeting defect densities of 0.1-0.3 defects per cm² to support high-volume production. TSMC's N3E variant has achieved yields exceeding 90% for high-volume chips as of mid-2025, reflecting optimizations in and process control. Samsung's SF3 process reports yields around 50% as of mid-2025. These metrics stem from managing EUV 's noise, where random and chemical variations can induce defects; mitigation strategies include precise dose control to boost uniformity and reduce line-edge roughness by up to 20%. Additional challenges in 3 nm designs include thermal throttling in densely packed layouts, where elevated power densities—up to 150 W/cm² in logic blocks—necessitate to prevent overheating, potentially curtailing performance by 10-20% under sustained loads. Backside power delivery emerges as a promising solution, relocating power rails to the wafer's rear to shorten distribution paths and cut IR voltage drop by 10-15%, thereby enhancing stability without increasing frontside routing congestion. These factors underscore the balance required between efficiency targets and fabrication reliability at this scale.

Cost structure and market economics

The cost structure of 3 nm semiconductor production is dominated by the expenses associated with advanced and fabrication equipment, particularly (EUV) technology. A single 300 mm processed at the 3 nm node by costs approximately $20,000 in 2025, reflecting a significant escalation from prior generations due to the complexity of multi-patterning and high-precision required. This price incorporates the elevated costs of EUV photomasks, where individual blanks and patterning can exceed $100,000 each, contributing to overall mask set expenses that reach tens of millions of dollars for a full production run. Additionally, the per-unit chip fabrication cost at 3 nm stands around $0.25 per square millimeter, driven by depreciation of specialized tools like EUV scanners, which alone can cost over $200 million per unit. Economically, the 3 nm process represents a 25% increase in pricing compared to the 5 nm node, where wafers cost about $16,000–$17,000, yet this premium is partially mitigated by the ability to yield 20–30% more functional dies per wafer through improved layout . TSMC's emphasizes scaling production to amortize these costs, with the company reporting sustained that supports stable pricing amid capacity expansions. Samsung, facing competitive pressures, has invested heavily in its 3 nm gate-all-around (GAA) process, committing over $10 billion in to enhance yields and capture , though its capex for advanced nodes in 2025 has been adjusted downward to around half of prior levels to align with utilization rates. The global market for 3 nm semiconductor production is projected to generate approximately $30 billion in revenue in 2025, fueled by demand for AI accelerators and high-end mobile processors, with an expected compound annual growth rate (CAGR) of 18.3% through 2032. Foundry market dynamics show TSMC commanding a dominant 70% share of overall advanced node production in mid-2025, while Samsung holds about 11%, reflecting TSMC's lead in yield maturity and customer adoption. Capacity constraints at leading foundries have driven wafer price hikes of 8–10% for sub-5 nm nodes into 2026, exacerbating supply tightness for premium clients. TSMC has indicated that demand for advanced-node processes, including 3 nm, exceeds available capacity by about three times, primarily driven by requirements for AI chips, resulting in persistent shortages. Geopolitical factors further influence 3 nm economics, including U.S. government subsidies under the , which allocated up to $7.86 billion in direct funding to in 2024 to bolster domestic 3 nm-equivalent fabrication capabilities and mitigate reliance on Asian supply chains. These incentives, combined with export controls on advanced equipment, heighten risks for non-U.S. players like and , potentially reshaping investment priorities and pricing strategies in the sector.

Adoption and applications

Mobile and consumer devices

The 3 nm process has significantly influenced the design and performance of mobile and consumer devices, particularly in smartphones and tablets, by enabling more efficient system-on-chips (SoCs) that balance high computational demands with power constraints. One of the earliest adoptions came with Apple's A17 Pro SoC, fabricated using TSMC's N3 process and integrated into the series launched in 2023, which delivered enhanced graphics capabilities and sustained performance for gaming and applications. followed with its Dimensity 9400 SoC on TSMC's improved N3E process in late 2024, powering premium Android devices with an all-big-core CPU architecture that supports advanced on-device AI processing for features like real-time image enhancement. In 2025, adoption accelerated among Android manufacturers, with introducing the XRING O1 SoC on TSMC N3E for the 15S Pro , featuring a ten-core CPU and 16-core GPU that achieved benchmark scores competitive with leading rivals while emphasizing AI-driven tasks such as voice recognition and photo editing. also shifted its flagship lineup to 3 nm with the 2500 SoC using its SF3 process for the S25 series, incorporating gate-all-around (GAA) transistors to improve thermal management in high-resolution displays and multitasking scenarios. These implementations reflect a broader trend where approximately 50% of advanced node (3 nm and below) SoC shipments occurred in mobile devices by 2025, driving 's wafer production allocation toward consumer applications. The efficiency gains from 3 nm technology have directly benefited battery life in these devices, with reports indicating up to 20% extensions in usage time under mixed workloads compared to prior 4 nm nodes, allowing for longer video streaming and navigation without frequent recharging. This power reduction stems from denser packing and lower leakage currents, enabling manufacturers to maintain slim profiles while supporting demanding features like always-on AI assistants. In foldable smartphones, such as the Find N5, the compact die size of 3 nm SoCs facilitates ultra-thin designs—measuring just 8.93 mm when folded—without compromising on battery capacity or durability for repeated folding cycles. By mid-2025, over 70% of flagship Android smartphones had transitioned to 3 nm processes, up from less than 20% in 2024, fueled by competitive pressures to match iOS performance in AI and multimedia while extending device longevity through better thermal efficiency. Wearables, including advanced smartwatches, have also begun incorporating 3 nm variants for low-power always-connected features, though smartphones remain the primary driver, accounting for nearly 50% of global 3 nm wafer demand that year.

High-performance computing and AI

The 3 nm process has become pivotal in (HPC) and (AI) applications, particularly for data center accelerators that demand massive parallel processing and energy efficiency. AMD's Instinct MI350 series accelerators, built on TSMC's 3 nm process, deliver up to 185 billion and support generative AI tasks with enhanced CDNA 4 architecture, targeting deployment in 2025 for supercomputing environments. These implementations leverage the node's dense transistor integration to handle exascale simulations and models that previous nodes could not scale efficiently. A primary advantage of the 3 nm process in HPC and AI is its improved floating-point operations per second (FLOPS) per watt, offering up to a 30% reduction in power consumption compared to 5 nm predecessors while maintaining or boosting computational throughput. This efficiency enables larger AI models to run on sustainable power budgets, facilitating scalability toward where systems exceed 10^18 FLOPS without prohibitive energy costs. For instance, TSMC's N3X variant, designed specifically for HPC, enhances clock speeds by 5% over standard 3 nm at the same voltage, allowing custom chips to achieve higher performance densities for AI supercomputers. In 2025, the sector experienced a significant boom driven by AI demands, with advanced nodes like 3 nm contributing substantially to expanded HPC capacity amid projections of 15% annual global growth in data center infrastructure. This trend supports the training of generative AI models beyond , such as larger multimodal systems requiring trillions of parameters, by providing the dense, low-latency compute resources essential for iterative fine-tuning and deployment at scale. TSMC's N3X further accelerates custom HPC designs, enabling hyperscalers to integrate 3 nm accelerators into next-generation AI fabrics for real-time inference in enterprise environments.

Notable chips and production milestones

The 3 nm process marked a significant advancement in semiconductor manufacturing, with Samsung initiating mass production of its gate-all-around (GAA) 3 nm chips in June 2022, achieving up to 45% reduced power consumption, 23% improved performance, and 16% smaller area compared to its 5 nm process. TSMC followed by entering high-volume production of its N3 FinFET-based 3 nm technology later in December 2022, enabling the delivery of the industry's first commercial 3 nm chips in 2023. Intel began risk production of its Intel 3 process in 2023, with high-volume manufacturing ramping up in 2024 for server applications and shifting to European facilities like Fab 34 in Ireland by late 2025 to expand capacity. Key production milestones included TSMC's achievement of approximately 55% yields on its N3 node by mid-2023, supporting the rollout of enhanced like N3E for broader . By 2024, demand from AI and led to full booking of TSMC's 3 nm capacity through 2026, with Apple, , , and securing the majority of allocations. Samsung improved yields on its SF3 (3 nm GAA) process to support flagship mobile chips in 2025, while targeted process leadership with Intel 3, offering 18% performance gains over its Intel 4 node at iso power. Notable chips fabricated on 3 nm processes highlight the technology's impact on , and AI applications. Apple's A17 Pro, introduced in September 2023 for the series, was the first consumer-facing 3 nm SoC on TSMC's N3B variant, featuring 19 billion transistors and enabling console-quality gaming with a 6-core CPU and 6-core GPU. The family, unveiled in October 2023 for and , utilized TSMC's 3 nm process to deliver up to 65% faster ray tracing and a 16-core Neural Engine for AI tasks, powering the transition to unified memory architectures in personal computers. In mobile processors, Qualcomm's Snapdragon 8 Elite (also known as Gen 4), launched in October 2024 for 2025 flagship smartphones, marked the company's shift to 's 3 nm N3E process, providing a 45% increase in NPU performance for on-device AI compared to its 4 nm predecessor. 's Dimensity 9400, announced in October 2024, became the company's first 3 nm chip on TSMC N3E, featuring an all-big-core CPU design with Cortex-X925 for up to 35% better power efficiency in AI-accelerated tasks. Samsung's 2500, revealed in June 2025 for the Galaxy S25 series, was the firm's inaugural 3 nm GAA mobile SoC on its SF3 node, integrating a 10-core CPU and Xclipse 960 GPU with 39% NPU uplift for generative AI, achieving 15% overall performance gains over the prior 4 nm 2400. For , Intel's Granite Rapids Xeon 6 processors, entering production in 2024 on the Intel 3 node, supported up to 128 E-cores for AI workloads, delivering 2.4x performance per watt over prior generations. By mid-2025, Intel expanded 3 nm to consumer PCs with chips like Lunar Lake, emphasizing low-power efficiency for laptops. These implementations underscore the 3 nm process's role in enabling denser integration and energy-efficient scaling amid surging AI demand.

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