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5 nm process
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5 nm process
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MOSFET scaling
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In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the "5 nm" process as the MOSFET technology node following the "7 nm" node. In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Huawei, Mediatek, Qualcomm and Marvell.[1][2]

The term "5 nm" does not indicate that any physical feature (such as gate length, metal pitch or gate pitch) of the transistors is five nanometers in size. Historically, the number used in the name of a technology node represented the gate length, but it started deviating from the actual length to smaller numbers (by Intel) around 2011.[3] According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, the 5 nm node is expected to have a gate length of 18 nm, a contacted gate pitch of 51 nm, and a tightest metal pitch of 30 nm.[4] In real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.[5][6]

History

[edit]

Background

[edit]

Quantum tunnelling effects through the gate oxide layer on "7 nm" and "5 nm" transistors became increasingly difficult to manage using existing semiconductor processes.[7] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[8][9]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[10][11]

In 2015, IMEC and Cadence fabricated 5 nm test chips. The fabricated test chips were not fully functional devices, but rather are to evaluate patterning of interconnect layers.[12][13]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the "5 nm" node.[14]

In 2017, IBM revealed that it had created "5 nm" silicon chips,[15] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2, for a total of 30 billion transistors (1667 nm2 per transistor or 41 nm actual transistor spacing).[16][17]

Commercialization

[edit]

In April 2019, Samsung Electronics announced they had been offering their "5 nm" process (5LPE) tools to their customers since 2018 Q4.[18] In April 2019, TSMC announced that their "5 nm" process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[19] For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.[20]

For their "5 nm" process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.[21]

In October 2019, TSMC reportedly started sampling 5 nm A14 processors for Apple.[22] At the 2020 IEEE IEDM conference, TSMC reported their 5 nm process had 1.84x higher density than their 7nm process.[23] At IEDM 2019, TSMC revealed two versions of 5 nm, a DUV version with a 5.5-track cell, and an (official) EUV version with a 6-track cell.[24][25]

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their "5 nm" test chips with a die size of 17.92 mm2.[26] In mid 2020 TSMC claimed its (N5) "5 nm" process offered 1.8x the density of its "7 nm" N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.[27]

On 13 October 2020, Apple announced a new iPhone 12 lineup using the A14. Together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's "5 nm" node. Later, on 10 November 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.[28]

In October 2021, TSMC introduced a new member of its "5 nm" process family: N4P. Compared to N5, the node offered 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expected first tapeouts by the second half of 2022.[29][30][needs update]

In December 2021, TSMC announced a new member of its "5 nm" process family designed for HPC applications: N4X. The process featured optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process was expected at that time to[needs update] offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2 V and supply voltage in excess of 1.2 V. TSMC, at that time, said that they expected[needs update] N4X to enter risk production by the first half of 2023.[31][32][33]

In June 2022, Intel presented some details about the Intel 4 process (known as "7 nm" before renaming in 2021): the company's first process to use EUV, 2x higher transistor density compared to Intel 7 (known as "10 nm" ESF (Enhanced Super Fin) before the renaming), use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 was Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.[34] Intel 4 has contacted gate pitch of 50 nm, both fin and minimum metal pitch of 30 nm, and library height of 240 nm. Metal-insulator-metal capacitance was increased to 376 fF/μm², roughly 2x compared to Intel 7.[35] The process was optimized for HPC applications and supported voltage from <0.65 V to >1.3 V. WikiChip's transistor density estimate for Intel 4 was 123.4 Mtr./mm², 2.04x from 60.5 Mtr./mm² for Intel 7. However, high-density SRAM cell had scaled only by 0.77x (from 0.0312 to 0.024 μm²) and high-performance cell by 0.68x (from 0.0441 to 0.03 μm²) compared to Intel 7.[36][needs update]

On 27 September 2022, AMD officially launched their Ryzen 7000 series of central processing units, based on the TSMC N5 process and Zen 4 microarchitecture.[37] Zen 4 marked the first utilization of the 5 nm process for x86-based desktop processors. In December 2022 AMD also launched the Radeon RX 7000 series of graphics processing units based on RDNA 3, which also used the TSMC N5 process.[38]

On 26 August 2024 IBM introduced their Telum II processor, based on Samsung's 5 nm process.

Nodes

[edit]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[39][40]

5 nm
IRDS roadmap 2017[41] Samsung[42][43][44][45][46] TSMC[42]
Process name 7 nm 5 nm 5LPE 5LPP N5 N5P
Transistor density (MTr/mm2) Unknown Unknown 126.9[46] Unknown 138.2[47][48]
SRAM bit-cell size (μm2) 0.027[49] 0.020[49] 0.0262[50] 0.021[50]
Transistor gate pitch (nm) 48 42 57 51
Interconnect pitch (nm) 28 24 36 Unknown 28[51]
Release status 2019 2021 2018 risk production[18]
2020 production 		2022 production 2019 risk production[19]
2020 production 		2020 risk production
2021 production

4 nm

[edit]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[39][40]

4 nm
Samsung[42][44][45][46][52] TSMC Intel[53][34]
Process name 4LPE
SF4E		 4LPP
SF4		 4LPP+
SF4P		 4HPC
SF4X		 4LPA
SF4U 		N4 N4P 4N[54] N4X[31][32][33] N4C[55] 4[56][57]
Transistor density (MTr/mm2) 137[46] Unknown Unknown Unknown 143.7[58] Unknown Unknown Unknown 123.4–129.82[59][36][60]
SRAM bit-cell size (μm2) 0.0262[50] Unknown Unknown Unknown Unknown Unknown Unknown Unknown 0.024[50]
Transistor gate pitch (nm) 57 Unknown Unknown Unknown 51 Unknown Unknown Unknown 50[60]
Interconnect pitch (nm) 32 Unknown Unknown Unknown 28 Unknown Unknown Unknown 30[60]
Release status 2020 risk production
2021 production		 2022 production 2023 production 2025 Q1 production[61] 2025 production 2021 risk production
2022 production		 2022 risk production
2022 production		 2022 production Risk production by H1 2023
2024 production		 2025 production 2022 risk production[62]
2023 production[63]

Beyond 4 nm

[edit]
Main article: 3 nm process

"3 nm" is the usual term for the next node after "5 nm". As of 2023, TSMC has started producing chips for select customers, while Samsung and Intel have plans for 2024.[53][64][65][66][needs update]

"3.5 nm" has also been given as a name for the first node beyond "5 nm".[67]

References

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5 nm process

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The 5 nm process is an advanced node in semiconductor manufacturing that scales transistor features to approximately 5 nanometers using fin field-effect transistor (FinFET) architecture and extreme ultraviolet (EUV) lithography, achieving up to 1.8 times the logic density of the preceding 7 nm node while delivering 15% higher performance or 30% lower power consumption at the same speed. Developed primarily by leading foundries Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung Electronics, the 5 nm process entered volume production in 2020 with TSMC's N5 variant, marking the first widespread adoption of EUV for multiple layers to enable precise patterning at this scale. Samsung followed with mass production of its SF5 process in 2020, offering a 25% increase in logic density, 10% performance uplift, or 20% power reduction compared to its 7 nm technology. Both implementations incorporate high-mobility channel materials, such as silicon-germanium (SiGe) for p-type FinFETs in TSMC's case, to enhance carrier mobility and overall efficiency. Key variants of the process include TSMC's N5P, which provides an additional 5% performance improvement or 10% power savings over N5, and N4, a refined 5 nm-class node with further density gains for cost-sensitive applications. Samsung's SF5 is optimized for (HPC) and automotive-grade chips, featuring tight process controls to support standards like ISO 26262. These advancements have enabled transistor densities exceeding 170 million per square millimeter, facilitating the integration of over 100 million transistors in a typical smartphone system-on-chip (SoC). The 5 nm process powers a wide range of applications, including mobile devices for and AI processing, high-end servers for data centers, and automotive systems for advanced driver-assistance features. Notable deployments include mobile SoCs for smartphones and wearables, as well as solid-state drive controllers, underscoring its role in driving energy-efficient computing amid growing demands for AI and edge processing. By 2025, the node remains a cornerstone for performance-critical designs, bridging the transition to even smaller nodes like 3 nm while addressing challenges in yield and cost through ongoing optimizations.

Technology Fundamentals

Node Definition and Metrics

The 5 nm process node represents a generation of semiconductor manufacturing technology characterized primarily as a designation rather than a literal measurement of physical dimensions, such as gate length, which has long ceased to align directly with node names. Instead, it approximates advancements in density and key feature sizes, including a minimum metal pitch (MMP) of approximately 28-36 nm and a contacted poly pitch (CPP) of 48-60 nm, enabling tighter integration of logic elements while adhering to scaling rules defined by industry roadmaps like the International Roadmap for Devices and Systems (IRDS). Key performance metrics for the 5 nm node emphasize improvements in , power efficiency, and speed, with standard reaching up to 170 million per square millimeter (MTr/mm²), a metric that reflects optimized logic area scaling for high-volume production. Compared to the preceding 7 nm node, which achieves around 100 MTr/mm² in similar benchmarks, the 5 nm process delivers approximately 1.7-1.8× higher , allowing for more complex circuits within the same die area. This scaling is quantified through standard logic area metrics, where the 5 nm node reduces cell area by about 40-50% relative to 7 nm while maintaining functionality. In terms of power and performance, the 5 nm node provides 15-30% better power efficiency and 10-15% higher speed at iso-power compared to 7 nm, as measured in representative workloads, enabling applications like mobile SoCs and AI accelerators to balance constraints with computational demands. These gains stem from refinements in FinFET transistor architecture, which enhances electrostatic control and reduces leakage currents to sustain scaling at this node, serving as a critical precursor to gate-all-around FET (GAAFET) structures in subsequent generations. (EUV) plays an enabling role by patterning these finer features with higher precision.

Architectural Innovations

The adoption of (EUV) in the 5 nm process enabled single-patterning for critical layers, significantly reducing the multi-patterning complexity that was prevalent in the 7 nm node and simplifying fabrication steps while improving pattern fidelity. This shift allowed for tighter pitches without the overlay errors associated with multiple exposures, contributing to higher throughput and lower costs in production. Refinements in FinFET architecture at the 5 nm node focused on optimizing fin dimensions, including fin heights of approximately 50-60 nm, widths around 6-8 nm, and pitches scaled to 27 nm or below, to enhance electrostatic control and boost drive current by up to 15-20% compared to prior nodes. These adjustments minimized short-channel effects and improved gate-to-channel coupling, enabling better performance in high-density logic circuits while maintaining low leakage. Interconnect improvements in the 5 nm process incorporated liners for lines, which reduced resistance by mitigating in narrow features below 20 nm pitch, and advanced low-k dielectrics with effective values around 2.5-2.7 to lower inter-layer . These enhancements addressed RC delay challenges, improving and overall chip speed by 10-15% in dense metallization schemes. Power delivery network enhancements at the 5 nm node included denser local power routing and reduced via resistance through selective metallization, serving as precursors to full backside power delivery by minimizing IR drop and enabling more efficient voltage distribution in multi-core designs. For high-volume , the 5 nm process targeted defect densities below 0.1 defects/cm², achieving mature yields exceeding 90% through improved and controls.

Historical Development

Early Research and Announcements

Research into the 5 nm semiconductor process originated in the late as part of broader efforts to extend amid diminishing returns from prior nodes. In January 2016, outlined its , projecting the 5 nm process to enter production by 2020 as a full-node advancement over its 7 nm technology, with development already in the full stage by the end of that year. Similarly, in May 2017, announced its foundry roadmap, positioning 5 nm as a key node following 6 nm, with initial variants like 5LPE emphasizing low-power enhancements through EUV integration. Key collaborations accelerated feasibility studies, particularly through Imec's contributions to EUV lithography and gate-all-around (GAA) transistor development. Imec's work on EUV patterning and process co-optimization enabled early demonstrations of 5 nm scaling potential, including GAA prototypes that addressed FinFET limitations in channel control and leakage. By 2017, Imec introduced extensions to GAA architectures, such as forksheet transistors, validating their viability for sub-5 nm nodes through joint efforts with industry partners. Milestones in 2018-2019 highlighted competitive dynamics, influenced by Intel's repeated delays in 10 nm volume production, which extended into 2019 due to yield challenges and allowed foundries like and to advance their announcements without immediate pressure. In October 2018, TSMC taped out its first 7 nm EUV designs and scheduled 5 nm tape-outs for the first half of 2019, followed by risk production initiation in April 2019. Samsung completed 5 nm EUV development by April 2019, enabling customer tool access and underscoring rapid progress in low-power FinFET scaling. Academic contributions from IEEE conferences emphasized scaling limits, with the 2017 International Roadmap for Devices and Systems (IRDS) report detailing challenges in sub-5 nm feature control, such as quantum effects and interconnect variability. A 2017 IEEE paper on trends further analyzed innovations needed to sustain density gains at 5 nm, prioritizing high-mobility channels and 3D integration. These works, presented at events like IEDM, informed industry roadmaps by quantifying trade-offs in power, performance, and area.

Commercial Production Timeline

TSMC initiated risk production for its 5 nm N5 process in April 2019, achieving high-volume manufacturing ramp-up by the second quarter of 2020 and full qualification by the fourth quarter of the same year. Samsung began volume production of its 5LPE process in the second quarter of 2020, with shipments of initial 5 nm system-on-chips commencing in the third quarter. In 2021, introduced the N5P variant, an enhanced version of N5 offering approximately 5% higher performance or 10% lower power consumption at iso-speed, alongside density improvements to support expanding customer demands. Production ramps for 5 nm processes accelerated through 2021 and 2022 despite supply chain challenges from and material shortages, which temporarily constrained global output. Yield rates for TSMC's 5 nm improved rapidly from around 50% at the start of in early 2020 to over 80% within months, reaching mature levels above 80% by 2022 as optimizations took hold. By 2023, 5 nm approached full levels, with reporting 100% utilization for its 5 nm and advanced nodes in 2024 amid surging demand. By 2025, (SMIC) completed development of its 5 nm without extreme ultraviolet (EUV) , though with yields about one-third of 's equivalent and costs 40-50% higher. Bookings for 's 5 nm production extended into 2026, driven primarily by applications requiring chips.

Manufacturing Approaches

TSMC Processes

's N5 process represents a pivotal advancement in fabrication, employing () lithography for over 10 critical layers to enable precise patterning of features such as cuts, contacts, vias, and metal lines, thereby reducing the need for multiple exposures. This approach incorporates single-patterning EUV techniques for tight pitches in the backend-of-line (BEOL) interconnects, supplemented by where necessary to achieve the required resolution for high-density logic and structures. Additionally, the N5 flow integrates high-mobility channels using silicon-germanium (SiGe) as the p-type FinFET channel , enhancing carrier mobility and drive current for improved in mobile system-on-chips (SoCs) and () applications. The N5P variant builds on the N5 foundation with targeted enhancements, with comparable transistor density to N5 through layout optimizations that maximize EUV utilization in select layers while maintaining for (IP) reuse. These optimizations include refined design rules for standard cells and SRAM bit cells, allowing for more efficient packing without altering the core FinFET architecture or requiring extensive redesigns. Alongside gains, N5P offers approximately 5% higher or 10% lower power at iso-power compared to N5, further leveraging the high-mobility channel integration for balanced power and speed trade-offs. TSMC's fabrication infrastructure for the 5 nm family relies on 300 mm wafers processed in advanced environments across its Taiwan-based GigaFabs, such as Fab 18, which supports high-volume production of N5 and related nodes. Critical to maintaining yield and precision is advanced for overlay control, achieving accuracy below 2 nm to align multiple EUV-exposed layers and minimize defects in multi-patterned regions. This sub-2 nm overlay capability is enabled by high-resolution optical and e-beam tools integrated into the process flow, ensuring alignment tolerances meet the stringent requirements of FinFET scaling. The cost structure for N5 production reflects the increased complexity of EUV integration; as reported in 2020, wafer pricing was approximately 80% higher than for the 7 nm node (around $17,000 per 300 mm wafer versus $9,500), primarily due to EUV tool depreciation, higher consumables, and extended process times. By 2025, N5 prices have stabilized around $18,000–$20,000 per wafer, with per-transistor costs remaining competitive owing to the 1.8× density scaling over 7 nm, though overall fabrication expenses rose by 20-30% attributable to EUV-specific operations like source mask optimization and resist processing. Despite these elevations, TSMC anticipates 3-5% hikes for sub-5 nm nodes like N3 and N2 starting in 2026 to offset capacity expansions. In terms of production scale, TSMC's 5 nm capacity across facilities exceeded 100,000 wafers per month by 2025, concentrated in facilities like Fab 18 dedicated to advanced nodes, supporting the ramp-up for major clients in mobile and AI sectors. This expansion, part of a broader GigaFab network, has enabled over 200,000 wafers per month across 5 nm and finer nodes collectively, underscoring TSMC's dominance in EUV-enabled .

Samsung and Other Foundry Methods

Samsung's 5 nm process, designated as SF5, is a FinFET-based technology that entered in 2021 and utilizes () lithography for critical logic layers to achieve higher and efficiency. While EUV is employed for key patterning steps, deep ultraviolet (DUV) lithography is used for select non-critical layers to optimize cost and throughput. This approach enables up to a 25% increase in logic compared to Samsung's prior 7 nm node, with 10% higher performance or 20% lower power consumption. In parallel, Samsung developed the 5LPE (5 nm Low Power Early) variant, which builds on innovations from the 7LPP process to emphasize ultra-low power benefits and area scaling, supporting applications in mobile and . The SF5 node serves as a foundational platform, facilitating a smoother transition to gate-all-around (GAA) architectures in subsequent generations like Samsung's . Unlike some competitors, Samsung places greater emphasis on 3D stacking integration, such as its X-Cube , which enables silicon-proven 3D IC designs for 5 nm nodes to enhance heterogeneous integration and performance in multi-die systems. Semiconductor Manufacturing International Corporation (SMIC), China's leading foundry, has pursued a 5 nm process without access to EUV tools due to U.S. sanctions, relying instead on deep ultraviolet (DUV) combined with self-aligned quadruple patterning (SAQP) and multi-patterning techniques. This non-EUV approach aims to achieve comparable feature sizes through increased patterning complexity, with development targeted for completion and initial by 2025 to support domestic Chinese chip designs, particularly for Huawei's Kirin processors. Despite higher costs and potential yield challenges from the multi-patterning, this effort underscores SMIC's push for semiconductor self-sufficiency amid geopolitical restrictions. GlobalFoundries maintains limited involvement in 5 nm production, focusing instead on partnerships and mature nodes rather than standalone advanced manufacturing at this scale. Early collaborations, such as with and in 2017 for 5 nm , did not lead to commercial 5 nm fabs; by 2025, the company prioritizes specialty technologies like 12 nm and below for automotive and RF applications, securing orders through alliances with firms like for less advanced processes. Intel's role in 5 nm-equivalent processes is primarily internal, with its Intel 4 node—deployed starting in 2023 for products like —offering transistor densities and performance comparable to industry 5 nm standards, though it remains a FinFET-based without RibbonFET implementation. This node supports Intel's high-volume internal fabrication for CPUs and GPUs, with limited external offerings at this level to prioritize ecosystem development for future nodes.

Process Variants

5 nm Specific Nodes

The 5 nm process includes several specialized node variants from major foundries, each tailored to balance power, performance, and area (PPA) requirements for diverse applications such as mobile and . The following table summarizes key specifications for select 5 nm variants:
Foundry/NodeTransistor Density (MTr/mm²)Performance/Power vs Prior NodeKey Specs
TSMC N5~17115% perf or 30% power reduction vs N7Poly pitch ~48-51 nm, metal pitch ~30 nm
TSMC N5P~17110% perf or 22% power savings vs N5Backward compatible with N5
Samsung 5LPE~13510% perf or 20% power reduction vs 7 nmEnergy efficiency focus
Samsung 5LPP~135Similar to 5LPE, optimized for low powerMulti-patterning enhancements
SMIC N+3~125Comparable to 5 nm-class vs SMIC 7 nmDUV-based, lower density than peers
TSMC's N5 serves as the foundational 5 nm node, delivering 1.8 times the logic density relative to its , alongside a at equivalent power or 30% power reduction at matched performance. The subsequent N5P variant refines this baseline by providing an additional 10% or 22% power savings over N5, while preserving the same density to support seamless IP migration. Samsung's 5LPE (Low Power Early) variant emphasizes energy efficiency, achieving transistor densities of approximately 135 million s per mm² and enabling up to 10% higher or 20% lower power compared to its , making it suitable for power-sensitive designs like mobile processors. Complementing this, Samsung's SF5 node focuses on scaling for high-performance scenarios, incorporating ultra-high-density SRAM to improve overall logic efficiency over prior 5 nm iterations. These variants exhibit notable PPA trade-offs in density metrics; for instance, TSMC's N5 reaches about 171 million transistors per mm² in logic areas (including SRAM contributions in mixed designs), surpassing Samsung's 5LPE at roughly 135 million transistors per mm², which prioritizes power savings over maximum packing . Such differences highlight foundry-specific optimizations, where higher often correlates with enhanced but may increase . To promote , foundries have pursued in design rules and IP libraries for 5 nm nodes, enabling cross-variant compatibility and reducing redesign efforts for blocks.

Evolution to Sub-5 nm Nodes

The progression from the 5 nm process to sub-5 nm nodes represents a critical phase in scaling, where foundries like and introduced incremental enhancements at 4 nm before transitioning to more radical architectural shifts at 3 nm and beyond. 's N4 process and its variant N4P, optical shrinks backported from N5 technology, offer 4-6% improvements in over N5 while maintaining compatibility with existing 5 nm designs, enabling volume production starting in 2022. Similarly, 's 4LPP (4 nm Low Power Plus) node focused on multi-patterning EUV for improved scaling and power efficiency, entering around the same period to support mobile and high-performance applications. These 4 nm variants served as evolutionary steps, offering modest and performance gains—typically 4-6% over 5 nm—without requiring full redesigns, thus bridging the gap to more advanced nodes. A key architectural evolution in sub-5 nm scaling is the shift from FinFET transistors, which reached their scaling limits at 5 nm due to challenges in gate control and fin aspect ratios, to gate-all-around FET (GAAFET) structures for better and current drive. While retained refined FinFETs for its N3 (, which entered volume production in late with 10-15% performance uplift and 25-30% power reduction over N5, fully adopted GAAFETs in its 3 nm node during the same timeframe to overcome FinFET's short-channel effects. Following N3, introduced N3E and N3P variants in 2023-2024, offering 5-10% additional performance or power improvements over N3, with N3P entering volume production in 2024. This transition addressed the physical constraints of FinFETs, such as increased leakage and variability below 5 nm, paving the way for denser integration in logic circuits. Looking further ahead, TSMC's N2 (2 nm) process incorporates GAAFETs with backside power delivery network (BSPDN) technology, entering high-volume manufacturing in late 2025 (as of November 2025), promising 10-15% speed improvements or 25-30% power savings compared to N3. BSPDN decouples power routing from signal paths, reducing IR drop and enabling higher transistor densities, though initial yields and costs remain hurdles. Samsung is pursuing parallel advancements in its 2 nm roadmap, emphasizing similar nanosheet GAA implementations. As scaling pushes below 5 nm, fundamental challenges intensify, including quantum tunneling that causes leakage through thin barriers, degrading subthreshold swing and increasing , alongside thermal issues from self-heating in densely packed transistors that exacerbate variability and reliability. These effects, rooted in , limit classical scaling and necessitate innovations like new materials or 3D stacking to sustain . By late 2025, the 5 nm process continues to act as a vital bridge to 3 nm adoption, with reporting its 3 nm and 5 nm capacities fully booked through 2026 amid surging demand for AI, mobile, and chips.

Applications and Impact

Key Devices and Chips

The 5 nm process enabled the production of several landmark system-on-chips (SoCs) and processors, marking a significant advancement in mobile and computing performance. Apple's A14 Bionic, introduced in 2020 and fabricated on 's N5 node, was the first major commercial 5 nm chip, powering the series with 11.8 billion transistors across a die size of 88 mm². This SoC featured a 6-core CPU and 4-core GPU, delivering improved efficiency and graphics capabilities for mobile devices. Similarly, Apple's M1 SoC, also on N5 and released in late 2020 for Mac computers, integrated 16 billion transistors on a die of approximately 120 mm², combining an 8-core CPU, 7 or 8-core GPU, and unified to enable seamless transition from Intel-based systems. Qualcomm's Snapdragon 888, launched in December 2020 and produced on Samsung's 5LPE , served as the flagship Android SoC for 2021 smartphones like the and , featuring a 1+3+4 core CPU configuration and Adreno 660 GPU with around 10 billion transistors on a 112 mm² die. Despite its performance gains in AI and integration, the chip faced challenges from Samsung's 5 nm yield issues, resulting in higher power consumption and thermal throttling compared to TSMC-produced alternatives. Subsequent adoptions expanded 5 nm use to high-performance computing. AMD's Zen 4 architecture, debuting in 2022 with the Ryzen 7000 series desktop processors on TSMC's optimized N5 node, incorporated CCDs with up to 6.5 billion transistors per die, enabling clock speeds over 5 GHz and significant IPC improvements for gaming and productivity workloads. Huawei's Kirin X90 SoC in 2025 devices, fabricated on SMIC's 7nm N+2 process using modified techniques due to equipment limitations, achieving densities comparable to advanced nodes without full EUV adoption. From 2023 to 2025, 5 nm variants supported AI accelerators and enhanced mobile chips. Google's TPU v6 (), deployed in cloud infrastructure starting in 2024 on TSMC's 5 nm process, featured systolic arrays for inference, boosting efficiency for large models. Apple's SoC, released in 2022 on TSMC's enhanced N5P 5 nm node, packed 20 billion s on a larger die for and , offering up to 18% better CPU performance over the M1 while maintaining power efficiency. Other notable 5 nm chips include MediaTek's Dimensity 9200 series on TSMC N5 for mid-to-high-end Android devices. These devices highlighted 5 nm's role in scaling density for AI and without shifting to sub-5 nm nodes immediately.

Industry and Market Effects

The adoption of the 5 nm process has significantly contributed to the expansion of the global market, projected to reach approximately $697 billion in 2025, reflecting an 11% year-over-year increase primarily fueled by demand for AI accelerators and high-performance mobile devices. Advanced nodes like 5 nm have enabled the integration of more powerful AI chips and system-on-chips (SoCs) in smartphones and data centers, driving logic revenues to grow by 23.9% to $267.3 billion in 2025. This growth underscores the process's role in supporting generative AI applications and 5G-enabled mobile ecosystems, with semiconductors alone expected to reach $40.88 billion. Supply constraints during the 2021 semiconductor shortage severely impacted 5 nm production timelines, as operated its facilities at , leading to delays in flagship product launches such as Apple's series. The shortages, which persisted into early 2022, exacerbated global vulnerabilities and curtailed automotive and output by up to 20% in affected sectors. 's dominance in advanced nodes, holding over 90% for processes at 7 nm and below, intensified these bottlenecks, as competitors like and lagged in scaling 5 nm output. By 2025, 's has stabilized at around 70%, but its lead in 5 nm continues to centralize production risks. Geopolitical tensions between the and have hindered SMIC's progress toward commercial 5 nm production, with US export controls on (EUV) tools restricting access to essential equipment since 2019. These restrictions, aimed at limiting 's advancement in AI and , have forced SMIC to rely on domestic alternatives like deep ultraviolet (DUV) with self-aligned quadruple patterning, delaying viable 5 nm yields until potentially 2025 or later. As a result, 's semiconductor self-reliance efforts have accelerated, but at the cost of higher production inefficiencies and ongoing fragmentation. The high costs associated with 5 nm manufacturing, including wafer prices ranging from $15,000 to $20,000, have enabled for devices like high-end smartphones and AI servers while erecting significant barriers for smaller fabless firms entering the market. These elevated costs, driven by complex EUV processes and low initial yields, represent a 1.6x increase over 7 nm s and limit adoption primarily to major players such as Apple and . Despite planned 3-5% price hikes for sub-5 nm nodes in 2026, the favor established ecosystems, consolidating among leading foundries. By 2025, 5 nm processes are estimated to power 20-30% of high-end chips, particularly in mobile SoCs and AI accelerators, as production scales to meet demand from over 80% of smartphones transitioning from older nodes. This adoption rate reflects a broader shift where advanced nodes below 5 nm account for about 30% of global microchip output, prioritizing performance-critical applications over cost-sensitive legacy segments.

Challenges and Prospects

Technical and Yield Issues

One of the primary yield challenges in 5 nm process fabrication stems from (EUV) lithography, where noise introduces patterning defects such as microbridging and line breaks. These defects arise from photon shot noise and variations in chemistry, exacerbated by the limited number of photons available for exposure at this scale, leading to reduced pattern fidelity and lower overall yields. To mitigate these issues, dose optimization techniques adjust EUV exposure levels to minimize variations, while -aware (OPC) refines mask patterns to compensate for noise-induced edge roughness, achieving reductions in defect rates by orders of magnitude in experimental validations. Power leakage presents another critical hurdle in 5 nm FinFET devices, with scaling leading to elevated subthreshold leakage currents that degrade energy efficiency and increase consumption. High-k metal gate (HKMG) structures address this by replacing traditional with high-dielectric-constant materials like hafnium oxide, combined with s, to enhance gate control and suppress both gate and subthreshold leakage while maintaining performance. Thermal management becomes increasingly demanding at 5 nm due to higher transistor densities generating localized hotspots that can throttle performance and accelerate reliability failures. Advanced packaging solutions, such as integrated microchannels and diamond-based heat sinks, facilitate efficient heat dissipation by leveraging superior thermal conductivity materials, enabling sustained operation in stacked-die configurations common to this node. Defects in 5 nm manufacturing are categorized into random types, primarily caused by airborne particles or adhering to wafers, and systematic types, resulting from process variations like misalignment or inconsistencies. advancements, particularly electron-beam (e-beam) , provide high-resolution imaging down to sub-5 nm features, enabling precise detection and of these defects to support yield enhancement through targeted root-cause . As of late 2025, high demand has led to full booking of 5 nm capacity through 2026, exacerbating yield optimization efforts amid supply shortages. AI-assisted control has significantly resolved yield limitations in 5 nm production, with implementations at leading foundries like achieving yields around 80% through for defect prevention and real-time adjustments, further boosted by up to 20% via machine learning-driven optimizations in similar advanced nodes.

Future Scaling Directions

As scaling approaches physical limits beyond 5 nm, complementary field-effect transistors (CFETs) emerge as a key architectural shift for 1-2 nm nodes, stacking n-type and p-type FETs vertically to reduce footprint while maintaining performance. This configuration addresses short-channel effects and enables denser integration compared to traditional FinFETs or gate-all-around (GAA) structures, with simulations showing up to 20% area reduction and improved drive currents for sub-3 nm technologies. Challenges include thermal management during stacking and precise alignment, but CFETs are projected to support logic scaling toward the regime by enhancing electrostatic control. Two-dimensional (2D) materials, such as (MoS₂), offer promising channel alternatives for post-5 nm devices due to their atomic-scale thickness, which mitigates short-channel effects and enables gate lengths below 1 nm. transistors have demonstrated subthreshold swings near the Boltzmann limit and on/off ratios exceeding 10⁶ at scaled channels down to 30 nm, with potential for ballistic transport in ultra-thin layers. Integration of 2D channels with high-κ dielectrics and metallic contacts could extend by overcoming silicon's tunneling barriers, though challenges like and large-area synthesis persist. Advanced packaging techniques, including chiplets and 3D integration via TSMC's CoWoS (Chip on Wafer on Substrate), extend the utility of 5 nm processes by enabling heterogeneous assembly of multiple dies for higher bandwidth and efficiency without further transistor scaling. CoWoS supports over 9 high-bandwidth memory (HBM) stacks integrated with 5 nm logic, achieving inter-die bandwidths up to 1.5 TB/s and reducing latency in AI accelerators. Chiplet-based designs, combined with through-silicon vias (TSVs) and system-on-integrated-chips (SoIC), allow modular scaling, where 5 nm cores are paired with specialized I/O dies to boost overall system performance by 30-50%. Sustainability in scaling focuses on energy-efficient designs to accommodate AI's exponential compute demands, projected to drive data center electricity consumption to around 3% of global totals by 2030, with AI workloads contributing significantly to this growth, while reducing fab carbon footprints through optimized processes and materials. advancements like low-power GAA transistors and voltage scaling in 5 nm derivatives can cut AI inference energy by 40%, supporting greener data centers. Fab initiatives include integration and recovery, with industry targets to halve per-wafer emissions by 2030 via EUV efficiency gains and circular supply chains. Industry roadmaps project entry into the era by 2030, with targeting a 1 nm (10 ) node through nanosheet FETs and backside power delivery, following 2 nm in 2025 and 1.4 nm in 2028. Samsung originally aimed for similar milestones with 1.4 nm GAA processes by 2027 but has delayed to 2029, focusing on enhancements to its 2 nm node. SMIC pursues indigenous paths beyond 5 nm using deep-ultraviolet (DUV) lithography and self-aligned quadruple patterning, focusing on domestic R&D for 3-5 nm equivalents despite yield hurdles. Research frontiers explore integrating 5 nm logic with via cryogenic-compatible circuits, where FinFET-based systems-on-chip (SoCs) operate at 10 K to process data in real-time. These 5 nm designs enable low-power embedded controllers for , handling up to thousands of qubits within decoherence limits of 100 µs, though thermal noise and power constraints (<100 mW) require model calibration for reliable cryogenic performance.

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