Recent from talks
Camera Link
Knowledge base stats:
Talk channels stats:
Members stats:
Camera Link
Camera Link is a serial communication protocol standard designed for camera interface applications based on the National Semiconductor interface Channel-link. It was designed for the purpose of standardizing scientific and industrial video products including cameras, cables and frame grabbers. The standard is maintained and administered by the Automated Imaging Association or AIA, the global machine vision industry's trade group.
Camera Link uses one to three Channel-link transceiver chips with four links at 7 serial bits each. At a minimum, Camera Link uses 28 bits to represent up to 24 bits of pixel data and 3 bits for video sync signals, leaving one spare bit. The video sync bits are Data Valid, Frame Valid, and Line Valid. The data are serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The receiver accepts the four LVDS data streams and LVDS clock, and then drives the 28 bits and a clock to the board. The camera link standard calls for these 28 bits to be transmitted over 4 serialized differential pairs with a serialization factor of 7. The parallel data clock is transmitted with the data. Typically a 7× clock must be generated by a PLL or SERDES block in order to transmit or receive the serialized video. To deserialize the data, a shift register and counter may be employed. The shift register catches each of the serialized bits, one at a time, then registers the data out into the parallel clock domain - once the data counter has reached its terminal value.
Camera Link comes in several variants which differ in the amount of data that can be transferred. Some of them require two cables for transmission.
The "Base" Camera Link configuration carries signals over a single connector/cable. The cable used is a MDR ("Mini D Ribbon") 26-pin Male Plug Connector, optimized by 3M for the LVDS signal. In addition to the 5 LVDS pairs transmitting the serialized video data (24 bits of data and 4 framing/enable bits), the connector also carries 4 LVDS discrete control signals and 2 LVDS asynchronous serial communication channels for communicating with the camera. At the maximum chipset operating frequency (85 MHz), the base configuration yields a video data throughput of 2.04 Gbit/s (255 MB/s).
The Camera Link specification includes higher-bandwidth configurations that provide additional video data paths over a second connector/cable. The "Medium" configuration doubles the video bandwidth, adding 24 bits of data and the same 4 framing/enable bits present in the "Base" configuration. This yields a 48-bit wide video data path capable of throughput up to 4.08 Gbit/s (510 MB/s). The "Full" configuration adds another 16-bits to the data path, resulting in a 64-bit wide video path that can carry 5.44Gbit/s (680 MB/s).
Some camera and data acquisition hardware manufacturers have extended the bandwidth of the interface beyond the limits imposed by the Camera Link interface specification. These formats extend the width of the "Full" configuration by utilizing 8 unused bits and reassigning the 8 redundant framing/enable bits to produce a data path width of up to 80 bits over two connectors/cables, which further increases the video bandwidth. A consensus has emerged in the industry about the 80-bit variant, and compatible cameras and frame grabbers are marketed with the term "Camera Link Deca". However, some manufacturers use the term "Extended Full" to refer to Deca configuration, and still others retain use of the term Camera Link Full while referring to Full Deca. The 80-bit video path can carry 6.8 Gbit/s (850 MB/s).
The image below shows the relative signal timing of the clock and one data line of one of the Channel Link transceivers used for Camera Link transmissions. Data words start in the middle of the high phase of the clock, and the most significant bit is transmitted first.
The bits of pixel values are not assigned to serial transmitters in order, but are permutated in a complicated way, as shown in the following figure. The figure labels the Camera Link data bits consecutively and includes 8 additional bits not part of the Camera Link Full specification. (The Camera Link standard divides the data bits into eight 8-bit ports denoted by letter-number combinations, but uses the same letter-number combinations for color channels that do not always correspond one-to-one, making this notation ambiguous.)
Hub AI
Camera Link AI simulator
(@Camera Link_simulator)
Camera Link
Camera Link is a serial communication protocol standard designed for camera interface applications based on the National Semiconductor interface Channel-link. It was designed for the purpose of standardizing scientific and industrial video products including cameras, cables and frame grabbers. The standard is maintained and administered by the Automated Imaging Association or AIA, the global machine vision industry's trade group.
Camera Link uses one to three Channel-link transceiver chips with four links at 7 serial bits each. At a minimum, Camera Link uses 28 bits to represent up to 24 bits of pixel data and 3 bits for video sync signals, leaving one spare bit. The video sync bits are Data Valid, Frame Valid, and Line Valid. The data are serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The receiver accepts the four LVDS data streams and LVDS clock, and then drives the 28 bits and a clock to the board. The camera link standard calls for these 28 bits to be transmitted over 4 serialized differential pairs with a serialization factor of 7. The parallel data clock is transmitted with the data. Typically a 7× clock must be generated by a PLL or SERDES block in order to transmit or receive the serialized video. To deserialize the data, a shift register and counter may be employed. The shift register catches each of the serialized bits, one at a time, then registers the data out into the parallel clock domain - once the data counter has reached its terminal value.
Camera Link comes in several variants which differ in the amount of data that can be transferred. Some of them require two cables for transmission.
The "Base" Camera Link configuration carries signals over a single connector/cable. The cable used is a MDR ("Mini D Ribbon") 26-pin Male Plug Connector, optimized by 3M for the LVDS signal. In addition to the 5 LVDS pairs transmitting the serialized video data (24 bits of data and 4 framing/enable bits), the connector also carries 4 LVDS discrete control signals and 2 LVDS asynchronous serial communication channels for communicating with the camera. At the maximum chipset operating frequency (85 MHz), the base configuration yields a video data throughput of 2.04 Gbit/s (255 MB/s).
The Camera Link specification includes higher-bandwidth configurations that provide additional video data paths over a second connector/cable. The "Medium" configuration doubles the video bandwidth, adding 24 bits of data and the same 4 framing/enable bits present in the "Base" configuration. This yields a 48-bit wide video data path capable of throughput up to 4.08 Gbit/s (510 MB/s). The "Full" configuration adds another 16-bits to the data path, resulting in a 64-bit wide video path that can carry 5.44Gbit/s (680 MB/s).
Some camera and data acquisition hardware manufacturers have extended the bandwidth of the interface beyond the limits imposed by the Camera Link interface specification. These formats extend the width of the "Full" configuration by utilizing 8 unused bits and reassigning the 8 redundant framing/enable bits to produce a data path width of up to 80 bits over two connectors/cables, which further increases the video bandwidth. A consensus has emerged in the industry about the 80-bit variant, and compatible cameras and frame grabbers are marketed with the term "Camera Link Deca". However, some manufacturers use the term "Extended Full" to refer to Deca configuration, and still others retain use of the term Camera Link Full while referring to Full Deca. The 80-bit video path can carry 6.8 Gbit/s (850 MB/s).
The image below shows the relative signal timing of the clock and one data line of one of the Channel Link transceivers used for Camera Link transmissions. Data words start in the middle of the high phase of the clock, and the most significant bit is transmitted first.
The bits of pixel values are not assigned to serial transmitters in order, but are permutated in a complicated way, as shown in the following figure. The figure labels the Camera Link data bits consecutively and includes 8 additional bits not part of the Camera Link Full specification. (The Camera Link standard divides the data bits into eight 8-bit ports denoted by letter-number combinations, but uses the same letter-number combinations for color channels that do not always correspond one-to-one, making this notation ambiguous.)