Community Hub0 Subscribers
Community hub
Penryn (microprocessor)
View on Wikipediafrom Wikipedia
 Mobile Core 2 Duo T9550 with a 2.66 GHz clock speed, 6 MB of L2 cache, and a 1.07 GT/s FSB | |
| General information | |
|---|---|
| Launched | 2007 |
| Discontinued | 2011 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
|
| CPUID code | 1067x |
| Product code |
|
| Performance | |
| Max. CPU clock rate | 1.2 GHz to 3.06 GHz |
| FSB speeds | 800 MT/s to 1.07 GT/s |
| Physical specifications | |
| Cores |
|
| Package |
|
| Socket | |
| Cache | |
| L1 cache | 32 KB instruction, 32 KB data per core |
| L2 cache |
|
| Architecture and classification | |
| Application | Mobile |
| Technology node | 45 nm |
| Microarchitecture | Penryn |
| Instruction set | x86, x86-64 |
| Products, models, variants | |
| Brand names | |
| History | |
| Predecessor | Merom |
| Successors | Clarksfield (quad-core and extreme mobile) Arrandale (dual-core mobile) |
| Support status | |
| Unsupported | |
Penryn is the code name of a mobile processor from Intel that is sold in varying configurations such as Core 2 Solo, Core 2 Duo, Core 2 Quad, Pentium and Celeron.
During development, Penryn was the Intel code name for the 2007/2008 "Tick" of Intel's Tick-Tock cycle which shrunk Merom to 45 nanometers as CPUID model 23. The term "Penryn" is sometimes used to refer to all 45 nm chips with the Core architecture.
Chips with Penryn architecture come in two sizes, with 6 MB and 3 MB L2 cache.
Low power versions of Penryn are known as the Penryn-L; these are single-core processors.[1] The Penryn-QC quad-cores are made from two chips with two cores and 6 MB of cache per chip.
The desktop version of Penryn is Wolfdale and the dual-socket server version is Wolfdale-DP. Penryn-QC is related to Yorkfield on the desktop and Harpertown in servers. The MP server Dunnington chip is a more distant relative based on a different chip but using the same 45 nm Core microarchitecture.
Penryn was replaced by the Nehalem-based Arrandale (dual core) and Clarksfield (quad core).
Variants
[edit]| Processor | Brand name | Model (list) | Cores | L2 Cache | Socket | TDP |
|---|---|---|---|---|---|---|
| Penryn-L | Core 2 Solo | SU3xxx | 1 | 3 MB | BGA956 | 5.5 W |
| Penryn-3M | Core 2 Duo | SU7xxx | 2 | 3 MB | BGA956 | 10 W |
| SU9xxx | ||||||
| Penryn | SL9xxx | 6 MB | 17 W | |||
| SP9xxx | 25/28 W | |||||
| Penryn-3M | P7xxx | 3 MB | Socket P FCBGA6 |
25 W | ||
| P8xxx | ||||||
| Penryn | P9xxx | 6 MB | ||||
| Penryn-3M | T6xxx | 2 MB | 35 W | |||
| T8xxx | 3 MB | |||||
| Penryn | T9xxx | 6 MB | ||||
| E8x35 | 6 MB | Socket P | 35-55 W | |||
| Penryn-QC | Core 2 Quad | Q9xxx | 4 | 2x3-2x6 MB | Socket P | 45 W |
| Penryn XE | Core 2 Extreme | X9xxx | 2 | 6 MB | Socket P | 44 W |
| Penryn-QC | QX9300 | 4 | 2x6 MB | 45 W | ||
| Penryn-3M | Celeron | T3xxx | 2 | 1 MB | Socket P | 35 W |
| SU2xxx | μFC-BGA 956 | 10 W | ||||
| Penryn-L | 9xx | 1 | 1 MB | Socket P | 35 W | |
| 7x3 | μFC-BGA 956 | 10 W | ||||
| Penryn-3M | Pentium | T4xxx | 2 | 1 MB | Socket P | 35 W |
| SU4xxx | 2 MB | μFC-BGA 956 | 10 W | |||
| Penryn-L | SU2xxx | 1 | 5.5 W |
Penryn
[edit]
Wikinews has related news:
The successor to the Merom core for the Core 2 Duo T5000/T7000 series mobile processors, code-named Penryn, debuted on the 45 nanometer process. Many details about Penryn appeared at the April 2007 Intel Developer Forum. Intel's new 45 nm Penryn-based Core 2 Duo and Core 2 Extreme processors were released on January 6, 2008. The new processors launched exclusively with a TDP of 35 W; later releases were more energy efficient. HP began to offer the first model, the T9500, from late January 2008.[2] The T9500 offered a 2.6 GHz clock rate, higher than all but the Extreme Edition of the Merom range, and 6 MB (rather than 4 MB) of Level 2 Cache.
Important advances[3] included the addition of new instructions including SSE4 (also known as Penryn New Instructions) and new fabrication materials; most significantly a hafnium-based high-k dielectric.
All SL9xxx, SP9xxx, P9xxx, T9xxx and X9xxx processors are Penryn with the full 6 MB L2 cache enabled, while P7xxx, P8xxx and T8xxx can be either Penryn-3M or Penryn with only 3 MB cache enabled. They are indistinguishable by software, but Penryn uses product code 80576.
Intel released an Apple-only Exxx chip on April 28, 2008 that increased the clock rate to 3.06 GHz as well as increasing the Front Side Bus to 1066 MT/s, and changed the Cache to 6 MB shared L2. While it is used in desktop computers and has an E8xxx name, it uses the same packaging as mobile CPUs and is therefore considered a Penryn and not Wolfdale.
On desktops, Penryn pairs with the 2007 desktop Bearlake[4] chipset series, some of whose models include an increase in bus performance (connection to the northbridge, etc.) to 1333 MT/s and support for DDR3 SDRAM. In notebooks and other mobile equipment, Penryn initially paired with the mobile Crestline chipset series which supports DDR2 but not DDR3, (although when Penryn was released, Intel believed[5] future DDR3 support would benefit mobile equipment's power- and heat-constrained environments). Mobile Penryns were later paired with the Cantiga chipset series which (among other enhancements) added DDR3 support.
Penryn-3M
[edit]
The smaller (82 mm2 instead of 107 mm2) Penryn-3M is used in mobile processors with an L2 Cache 3 MB or less as a successor to Merom-2M. Its product code is 80577. The entry level Penryn-3M Core 2 processor is the T6xxx series, with 2 MB L2 Cache and begins with the T6400 at a clock rate of 2 GHz. Other Penryn-3M based processor series are Celeron T3xxx, Pentium T4xxx, as well as most Core 2 Duo SU9xxx, P7xxx, P8xxx, T8xxx processors.
In September 2009, Intel introduced new Consumer Ultra-Low Voltage processors based on Penryn-3M, as Celeron SU2xxx series, Pentium SU4xxx series and Core 2 Duo SU7xxx series, with 1, 2 and 3 MB of active L2 cache. Like the earlier Core 2 Duo SU9xxx series, they are always soldered on using a BGA956 package and have a TDP of only 10 W.
Penryn-L
[edit]Penryn-L does not actually seem to be a separate chip but only a version of Penryn-3M with a single core enabled. However, it has a separate product code of 80585. Penryn-L is used in the ultra-low voltage Core 2 SU3xxx, the standard voltage Celeron 9xx and the CULV Celeron 7xx and Pentium SU2xxx series. The Celeron versions have only 1 MB active L2 cache, Pentium versions have 2 MB.
Penryn-QC
[edit]In August 2008 Intel released their first two quad-core processors for notebooks, the Core 2 Quad Q9100 and Core 2 Extreme QX9300.[6] As these require more power (45 W) and cooling than other Penryn processors they are not automatically compatible with all Centrino 2 notebooks. Also the Extreme version requires the GS45/GM45/PM45 chipset.
Fixes
[edit]Microsoft has released a microcode update (KB2493989) for Windows 7 that addresses several stability issues on selected "Penryn" and "Merom" CPUs.[7]
See also
[edit]References
[edit]- ^ "Intel product specifications".
- ^ HP Slips Intel's Penryn Processor into Consumer Laptops
- ^ "Report on Penryn Series Improvements" (PDF). Technology@Intel Magazine. October 2006. Archived from the original (PDF) on 2007-09-27. Retrieved 2007-08-28.
- ^ "Intel to ship 'Bearlake' chipsets as 3x series?". The Register. Retrieved 2007-03-03.
- ^ "DDR3 advances make it a "must have" for Mobile Memory" (PDF). Intel Developer Forum. 2007. Archived from the original (PDF) on 2011-07-18. Retrieved 2007-08-28.
- ^ "Intel Set To Introduce Mobile Quad-core Processors". Tom's Hardware. 12 August 2008. Retrieved 2009-02-20.
- ^ "Microcode update for Intel processors in Windows 7 or in Windows Server 2008 R2". Retrieved 2020-11-03.
Penryn (microprocessor)
View on Grokipediafrom Grokipedia
Development and Release
Historical Context
In the mid-2000s, Intel underwent a significant architectural transition, moving away from the NetBurst microarchitecture that powered its Pentium 4 processors, which had been criticized for high power consumption and underwhelming performance per clock cycle despite aggressive clock speed scaling. This shift culminated in 2006 with the introduction of the Core microarchitecture, debuting in the Merom mobile processor as part of the Core 2 Duo lineup, emphasizing improved instructions per clock, wider execution resources, and better power efficiency to regain competitive footing in both mobile and desktop markets.[4][5] Penryn emerged as the subsequent "tick" in Intel's tick-tock development model, representing a die shrink of the Core microarchitecture from 65 nm to 45 nm while incorporating the company's pioneering high-k metal gate (HKMG) transistor technology to reduce leakage and enable higher transistor densities without proportional power increases. The Penryn codename was first publicly referenced in late 2006, with Intel confirming the tape-out of its design in November of that year, marking the completion of the processor layout for fabrication. This timeline aligned with Intel's broader push into advanced process nodes, as HKMG was formally demonstrated in January 2007 as the most substantial transistor innovation since the 1960s, allowing Penryn to achieve up to 30% higher performance at equivalent power compared to prior generations.[6][7] Facing intensifying competition from AMD's Barcelona server processor and Phenom desktop chips, both slated for late 2007 launches on AMD's own 65 nm process, Intel prioritized power efficiency in Penryn's design, particularly for mobile applications where battery life and thermal management were critical battlegrounds. This focus was driven by AMD's gains in multi-core performance and integrated memory controllers, prompting Intel to leverage the 45 nm shrink and HKMG for denser, cooler-running chips that could maintain leadership in mobile computing. Key production milestones included the readiness of Intel's D1D fabrication facility in Oregon for initial 45 nm output in the second half of 2007, followed shortly by volume ramp-up at Fab 32 in Arizona, ensuring timely availability ahead of year-end market demands.[8]Launch and Market Positioning
Intel launched the Penryn microarchitecture on November 12, 2007, beginning with high-end desktop and server processors such as the quad-core Core 2 Extreme QX9650 (Yorkfield) and the Xeon 5400 series (Harpertown), which targeted enthusiast and enterprise markets with improved efficiency on the new 45 nm process. Mobile variants followed on January 6, 2008, at the Consumer Electronics Show, introducing the first 45 nm notebook CPUs under the Core 2 Duo branding.[9] Desktop dual-core models, codenamed Wolfdale, arrived later that month, completing the initial consumer rollout. The initial mobile product lineup consisted of the Core 2 Duo T9300 (2.5 GHz), T9500 (2.6 GHz), and the premium Core 2 Extreme X9100 (3.06 GHz), all featuring 6 MB of L2 cache, 800 MHz front-side bus, and a 35 W thermal design power to match prior Merom processors.[9] These models emphasized incremental architectural tweaks alongside the process shrink to enable higher clock speeds without increasing power draw. Intel marketed Penryn primarily as an efficiency-focused upgrade for laptops, promising 20-30% performance gains over equivalent 65 nm Merom chips at similar power envelopes, appealing to OEMs seeking longer battery life and slimmer designs in business and consumer notebooks.[10][11] Early adoption was driven by partnerships with major laptop vendors; Hewlett-Packard integrated Penryn into its Pavilion HDX series shortly after launch, while Dell offered it as an upgrade option in XPS M1330 models by February 2008, enabling rapid market penetration in premium mobile segments.[12][13] For servers, Harpertown expanded the Xeon 5000 lineup starting November 2007, with broader availability in Q1 2008, positioning Penryn as a scalable solution for data centers emphasizing density and energy savings over raw speed.[14] Pricing reflected the transitional nature of the launch, with mobile entry-level options like the subsequent T8100 starting at $209 in volume, mid-range T9300 at $316, and high-end T9900 reaching $530, allowing tiered accessibility across consumer and professional applications.[15][16][17]Architecture and Design
Process Technology
The Penryn microprocessor utilized Intel's 45 nm CMOS process technology, marking the introduction of high-k metal gate (HKMG) transistors in consumer processors. This approach replaced the silicon dioxide gate dielectric with hafnium-based high-k materials, paired with metal gates, to maintain effective gate control and capacitance at the reduced scale while minimizing quantum tunneling effects.[1][7] The HKMG design achieved significant leakage reductions, including over 10 times lower gate oxide leakage and more than five times lower source-drain leakage compared to the prior 65 nm process.[1] It also delivered over 20% higher transistor drive current at equivalent leakage levels, enabling enhanced switching speeds.[7] These improvements stemmed from the hafnium dielectric's higher permittivity, which allowed thicker physical layers without sacrificing electrical thickness, thus curbing leakage while supporting aggressive scaling.[18] Production of Penryn began at Intel's Fab 32 in Chandler, Arizona, and Fab 11X in Rio Rancho, New Mexico, with high-volume manufacturing ramping up in late 2007.[19][20] Capacity expanded to Fab 28 in Kiryat Gat, Israel, in 2008, where process yields improved notably by the first quarter, supporting broader availability.[21] The 45 nm node doubled transistor density to approximately 3.3 million transistors per square millimeter relative to 65 nm Merom, facilitating more compact dies with up to 410 million transistors in dual-core configurations.[22] This, combined with about 30% lower transistor switching power, allowed Penryn to achieve 10-15% higher clock speeds at the same power envelope or up to 30% power savings at equivalent performance.[1][23]Core Microarchitecture Changes
The Penryn microarchitecture introduced several refinements to the Core 2 pipeline beyond the 45 nm process shrink, focusing on execution efficiency and power optimization. A key enhancement was the adoption of a radix-16 integer divider, which processes four bits per iteration compared to the radix-4 approach in the prior Merom generation, effectively doubling the throughput of integer and floating-point divide operations. This change reduced the average latency for 64-bit integer divisions from approximately 36 cycles in Merom to around 19 cycles in Penryn, benefiting workloads involving frequent divisions such as scientific computing and encryption algorithms.[24][25] In terms of execution units, Penryn added hardware support for SSE4.1, including a dedicated super shuffle engine capable of performing full 128-bit vector shuffles in a single cycle, compared to multiple cycles required in Merom. This innovation accelerated data rearrangement in SIMD operations, providing up to 2x performance gains in vector-intensive tasks like video encoding and 3D rendering, while integrating seamlessly with existing SSE instructions for backward compatibility.[1] Power management saw finer-grained clock gating implementations, including an auto-demote feature that optimizes transitions between C-states to minimize energy overhead during idle periods. Combined with Deep Power Down Technology, these improvements reduced idle power consumption by up to 30% relative to 65 nm predecessors, extending battery life in mobile variants without impacting active performance. The front-side bus (FSB) was also enhanced to support speeds up to 1600 MHz, increasing bandwidth by approximately 20% over Merom's maximum of 1333 MHz and improving scalability in multi-core configurations by reducing inter-core communication bottlenecks.[1][26] For thermal management, Penryn incorporated an integrated Digital Thermal Sensor (DTS) per core, enabling more precise temperature monitoring relative to the maximum junction temperature (TjMAX). This allowed for dynamic throttling based on real-time core-specific data, enhancing reliability under load while supporting features like Enhanced Intel SpeedStep Technology for balanced performance and efficiency.[27]Features and Improvements
Instruction Set Extensions
The Penryn microarchitecture introduced SSE4.1, comprising 47 new instructions that extend the x86 SIMD capabilities primarily for multimedia and high-performance computing applications.[28] These extensions build upon the SSE3 instructions from the prior Merom architecture, enabling more efficient vector operations without breaking backward compatibility.[28] Key additions include PTEST, which performs a logical AND operation between packed data and a mask for efficient bit testing and population count-like operations in vectorized code.[28] Rounding instructions such as ROUNDPS allow packed single-precision floating-point values to be rounded to specified modes, aiding in image processing and numerical stability for divisions.[28] Horizontal add and subtract operations, like those in PHADDD and PHSUBD, facilitate summing or differencing across lanes within a register, reducing instruction count for tasks such as dot products in 3D graphics.[28] Other notable instructions are MOVNTSD, a non-temporal store for double-precision floating-point data that bypasses caching to improve streaming workloads like video decoding, and PBLENDVB, which blends packed bytes based on a variable mask from XMM0 for conditional selections in multimedia blending.[28] Unlike later architectures such as Nehalem, initial Penryn implementations do not include SSE4.2 instructions, focusing instead on these SIMD enhancements for vector unit utilization.[1] SSE4.1 maintains full compatibility with prior SSE, SSE2, SSE3, and SSSE3 sets, requiring no additional operating system support beyond what was needed for those extensions, though full utilization depends on compiler and software optimization.[28] In practice, these instructions deliver up to 2x performance improvements in video encoding workloads, such as DivX compression, by accelerating motion estimation and data blending operations.[29]Cache and Memory Enhancements
The Penryn microarchitecture significantly expanded the L2 cache capacity compared to its predecessor, Merom, doubling it from 4 MB to 6 MB of shared unified cache for dual-core configurations, while quad-core variants reached 12 MB. This increase, combined with a higher 24-way associativity (up from 16-way in Merom), improved cache hit rates and reduced latency for frequently accessed data, enhancing overall system performance in memory-intensive workloads. Low-power variants offered a 3 MB L2 option to balance efficiency and capacity.[1][30][31] The L1 caches remained consistent with prior generations at 32 KB instruction cache and 32 KB data cache per core, maintaining the split design for optimized instruction fetch and data access. However, the shrink to the 45 nm process enabled faster transistor switching, resulting in reduced access latencies for these caches relative to the 65 nm Merom, contributing to improved single-threaded execution efficiency without altering the core structure.[32][24] Penryn introduced enhancements to the hardware prefetcher, including improved cache line split load handling that speculatively dispatches data halves ahead of address calculations, better anticipating access patterns in applications like video processing and reducing cache miss rates through proactive data loading. These prefetch improvements, alongside the larger L2, provided up to 20% better performance in bandwidth-bound scenarios compared to Merom. Mobile Penryn processors lacked an L3 cache, relying solely on the L1 and L2 hierarchy for on-die caching; this design choice prioritized power efficiency over the larger shared caches introduced in later desktop and server architectures like Yorkfield and Harpertown.[1][33] Memory support in Penryn centered on DDR2-800 (PC2-6400) in dual-channel configuration, enabling up to 8 GB of system memory to meet growing demands for multitasking and applications in mobile platforms. The memory controller, integrated into the supporting chipset rather than the CPU die, ensured compatibility with existing infrastructure while delivering bandwidth improvements over prior DDR2 speeds. In server variants, the same DDR2 support extended to higher capacities via chipset configurations, maintaining front-side bus architecture without on-die integration.[34][35]Variants and Models
Mobile Single- and Dual-Core Variants
The mobile single- and dual-core variants of the Penryn microprocessor targeted laptop applications, providing enhanced efficiency and performance through 45 nm process technology while maintaining compatibility with existing mobile platforms.[36] The standard dual-core Penryn configuration featured 6 MB of shared L2 cache and was exemplified by models like the Core 2 Duo T9400, operating at 2.53 GHz with a 1066 MHz front-side bus and a 35 W thermal design power (TDP), making it suitable for mainstream laptops requiring balanced performance for productivity and multimedia tasks.[37] These processors utilized Socket P packaging and supported dual-channel DDR2/DDR3 memory up to 1066 MHz.[38] For power-constrained designs, the low-voltage Penryn-3M dual-core variant offered 6 MB L2 cache in a smaller die configuration, as seen in the Core 2 Duo SL9300, which ran at 1.6 GHz with a 1066 MHz bus and 17 W TDP, enabling longer battery life in thin-and-light notebooks without significant performance trade-offs.[39] This series used BGA956 packaging to facilitate integration into compact systems. Single-core implementations, known as Penryn-L and branded as Core 2 Solo, provided 3 MB L2 cache for entry-level mobility, with the SU3500 model clocked at 1.4 GHz, an 800 MHz bus, and a 5.5 W TDP, targeting netbooks and ultra-mobile PCs (UMPCs) focused on basic computing and portability.[40][41] These used BGA956 sockets and emphasized low power consumption for extended runtime in small-form-factor devices.[42] Compared to the prior Merom generation, Penryn variants achieved approximately 10-20% higher instructions per cycle (IPC), contributing to overall performance gains in integer and floating-point workloads; for instance, SPEC CPU2006 integer rates improved by around 15% at equivalent clocks, while floating-point scores saw up to 20% uplift in optimized tests.[36] These improvements stemmed from architectural enhancements like wider execution units and better branch prediction, without relying heavily on SSE4.1 extensions in baseline comparisons.[34] All variants integrated seamlessly into Intel's Centrino 2 platform, paired with the Montevina chipset, which supported up to 8 GB DDR3 memory, Wi-Fi 802.11n, and optional discrete graphics for enhanced mobile connectivity and multimedia capabilities.[43]Low-Power and Embedded Variants
The low-power variants of the Penryn microprocessor targeted ultra-low voltage (ULV) applications with a thermal design power (TDP) of 10 W, enabling deployment in battery-constrained and thermally sensitive environments. These adaptations leveraged the 45 nm process technology to reduce leakage current and overall power draw compared to previous generations.[44] The Core 2 Duo U9xxx series represented key low-power offerings, featuring dual cores, 6 MB of shared L2 cache, and clock speeds between 1.06 GHz and 1.3 GHz. For instance, the U9600 model, with its 1.6 GHz variant adjusted for low-voltage operation, supported embedded industrial systems requiring reliable performance under power limits. These processors delivered up to 40% lower power consumption than equivalent Merom-based models at similar performance levels, facilitating extended operation in compact designs.[45][46] Embedded implementations often utilized 956-ball BGA (ball grid array) packaging, which supported soldered, non-upgradable configurations ideal for compact, integrated systems like thin clients and industrial controllers, in contrast to mPGA sockets for upgradable laptops.[44][47] Common use cases included medical devices for patient monitoring, point-of-sale terminals in retail environments, and early netbooks prioritizing portability and battery life over raw performance. These variants enhanced efficiency, with reports of up to 16% improved battery life in mobile applications relative to prior architectures.[48][46]Quad-Core and Server Variants
The quad-core variants of the Penryn microarchitecture were implemented as multi-chip modules (MCMs) combining two Penryn dies, each containing two cores and 6 MB of L2 cache, resulting in a total of four cores and 12 MB of L2 cache. These designs targeted high-end mobile applications, providing enhanced multi-threaded performance for demanding laptop workloads such as content creation and multimedia processing. A representative example is the Core 2 Quad Q9100, operating at 2.26 GHz with a 45 W TDP and compatibility with Socket P, launched in 2008 for premium mobile platforms.[49] For desktop systems, the Yorkfield series adopted the same dual-die MCM approach based on Penryn cores, delivering 12 MB of shared L2 cache across the four cores to support workstation tasks like video editing and 3D rendering. The Core 2 Quad Q9550, clocked at 2.83 GHz with a 95 W TDP and LGA 775 socket, exemplified this lineup, offering improved efficiency over prior 65 nm quad-core designs while maintaining compatibility with existing motherboards.[50] In server environments, the Harpertown processors extended the Penryn architecture with dual-die configurations optimized for dual-socket setups, featuring 12 MB of L2 cache and support for up to 2.66 GHz clock speeds in the Xeon 5400 series, with a typical 80 W TDP for balanced power and performance in enterprise applications. These used LGA 775 sockets for most models, while some Xeon variants employed Socket R (LGA 771) for enhanced scalability in rack-mounted systems. The E0 stepping introduced refinements for stability, though no dedicated L3 cache was added in this generation. Overall, quad-core Penryn implementations provided 50-70% uplift in multi-threaded workloads compared to dual-core counterparts, making them suitable for early virtualization and database servers.Revisions and Fixes
Stepping Revisions
The Penryn microarchitecture saw several stepping revisions to address fabrication issues and improve reliability. The initial C0 stepping debuted in November 2007 with the launch of mobile processors such as the Core 2 Duo T9300 and server Harpertown Xeons, supporting up to 6 MB of L2 cache per dual-core die.[51] Subsequent C1 and M1 steppings were introduced in early 2008, primarily as bug fix versions for quad-core configurations like Yorkfield. M0 stepping was used in low-power Penryn-3M mobile variants. These revisions resolved certain fabrication defects from the 45 nm process. The E0 and R0 steppings, introduced around mid-2008 for platforms like Montevina, replaced earlier steppings and provided minor enhancements, including improved compatibility. Production of the C0 stepping was limited initially due to yield challenges on the 45 nm process, with later steppings achieving broader adoption as manufacturing improved.Errata and Resolutions
The Penryn processors had several documented errata across steppings, as detailed in Intel's specification updates.[52] Notable issues included:- L2 Cache ECC Reporting (AW17): Address reported by Machine Check Architecture (MCA) on single-bit L2 ECC errors may be incorrect. No workaround available; affects all steppings (C0, M0, E0, R0).
- DTS Threshold Programming (AW30): Programming the Digital Thermal Sensor (DTS) threshold may cause unexpected thermal interrupts. Workaround: Temporarily disable DTS interrupt before updating the threshold. Affects all steppings.