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| |||
| Type | USB | ||
|---|---|---|---|
| Production history | |||
| Designer | USB Promoter Group | ||
| Designed | 29 August 2019 | ||
| Superseded | USB 3.2 | ||
| General specifications | |||
| Daisy chain | No | ||
| Audio signal | DisplayPort | ||
| Video signal | DisplayPort | ||
| Pins | 24 | ||
| Connector | USB-C | ||
| Electrical | |||
| Max. voltage | 48 V (PD 3.1) | ||
| Max. current | 5 A (PD) | ||
| Data | |||
| Data signal | USB or PCIe | ||
| Bitrate |
20 Gbit/s 40 Gbit/s 80 Gbit/s 120/40 Gbit/s asymmetric | ||

Universal Serial Bus 4 (USB4), sometimes erroneously referred to as USB 4.0, is the most recent technical specification of the USB (Universal Serial Bus) data communication standard. The USB Implementers Forum originally announced USB4 in 2019.
USB4 enables multiple devices to dynamically share a single high-speed data link. USB4 defines bit rates of 20 Gbit/s, 40 Gbit/s and 80 Gbit/s.[1][2] USB4 is only defined for USB-C connectors and its Type-C specification[3] regulates the connector, cables and also power delivery features across all uses of USB-C cables, in part[4] with the USB Power Delivery specification.[5]
The USB4 standard mandates backwards compatibility to USB 3.x and dedicated backward compatibility with USB 2.0.[6] The dynamic sharing of bandwidth of a USB4 connection is achieved by encapsulating multiple virtual connections ("tunnels") of other protocols, such as USB 3.x, DisplayPort and PCI Express.
USB4 is based on the Thunderbolt 3 protocol. However, it is different enough that backwards compatibility to Thunderbolt 3 is optional for many device types.[7]
History
[edit]Prior to USB4, Thunderbolt provided a way to dynamically share bandwidth between multiple DP and PCIe connections over a single cable. Thunderbolt originally used the mDP connector and was only backward compatible to DP connections and did not support power transfer.
The introduction of the Type-C connector in 2014 provided a connector that could support USB data connectivity and power transfer as well as DP connections. It also allowed the static sharing of bandwidth between DP and USB connections over the same cable.
Thunderbolt 3 switched over to using the new Type-C connector and also added backwards compatibility for USB connections and power transfer features.
USB4 Version 1.0
[edit]USB4 was announced in March 2019 by the USB Promoter Group.[8][9] The version 1.0 of the USB4 specification, released 29 August 2019, is titled "Universal Serial Bus 4 (USB4™)". Several news reports before the release of that version sometime use the wrong terminology "USB 4.0" and "USB 4".[10][11]
In the announcement press release, the USB Promoter Group mentions that USB4 is "based on the Thunderbolt™ protocol specification recently contributed by Intel Corporation".[12] Goals stated in the USB4 specification are increasing bandwidth, helping to converge the USB-C connector ecosystem, and "minimize end-user confusion". Some of the key areas to achieve this are using a single USB-C connector type, to offer display and data transfer features, while retaining "compatibility with existing and Thunderbolt products".[13]
Version 1.0 defined 20 Gbit/s and 40 Gbit/s connections, the required support of USB 2.0 and USB 3.x connections at up to 10 Gbit/s with support for tunneling connections according to the PCIe 4.0, USB 3.2 and DP 1.4a specifications. Optional backwards compatibility to Thunderbolt 3 as well as Host-to-Host networking were also defined. Compared to Thunderbolt 3, USB4 changed the raw bit rates slightly to bring them in line with other USB specifications, where the nominal bit rate matches the raw bit rate. USB4 also added support for USB3 tunnels and use of the USB2 wires for improved backwards compatibility with previous USB standards and to allow for simpler USB4 devices without support for PCIe. USB4 also added support for hub topologies compared to Thunderbolt's previous restriction to daisy-chaining topology.
In July 2020 Intel announced Thunderbolt 4 as an implementation of USB4 40 Gbit/s with additional requirements, such as mandatory backwards compatibility to Thunderbolt 3 and requirement for smaller notebooks to support being charged over Thunderbolt 4 ports.[14] Publications such as Anandtech described Thunderbolt 4 as "superset of TB3 and USB4" and "able to accept TB4, TB3, USB4, and USB 3/2/1 connections". Intel itself describes Thunderbolt 4 as "delivering increased minimum performance requirements, expanded capabilities and USB4 specification compliance" and as building "on the innovation of Thunderbolt 3".[15]
USB4 Version 2.0
[edit]On 18 October 2022 the USB Promoter Group released the USB4 Version 2.0 specification.[16][17]
It added a new transmission speed that allows 80 Gbit/s symmetric connections or asymmetric connections supporting 120 Gbit/s in one direction and 40 Gbit/s in the other. The new PAM3 encoding scheme enables this over existing, passive "USB 40Gbps" cables. Active cables are not forwards compatible in the same way, instead a new speed grade of active cables was added. It also upgraded the support of DP tunnels to DP 2.1, allowing the tunneling of DP connections with up to 80 Gbit/s (UHBR20). It also added a replacement of the previous tunneling of classic USB 3.2 connection speeds with "USB3 Gen T tunneling", which can exceed 20 Gbit/s and also removed PCIe overhead limitations.
Around the release of the new USB4 2.0 specification, USB-IF also mandated new logos and marketing names to simplify representing the maximum supported bit rates and wattages to consumers.[18]
In September 2023, Intel announced the launch of Thunderbolt 5 as an implementation of USB4, using the new abilities of 80 Gbit/s connections and updated DP support[19] Intel's own press release describes it as "built on industry standards – including USB4 V2".[20]
Functionality of USB4 ports
[edit]This section may be too technical for most readers to understand. (November 2024) |
Similarly to how USB 3.x specifications defined the new SuperSpeed(Plus) protocols for faster signaling rates, they also mandated that USB 3.x physically and architecturally implement USB 2.0 specification with dedicated wires, where the USB4 specification describes 2 different aspects. The first one is what type of existing connections and compatibility a USB4 port guarantees. The USB4 specification speaks of downstream facing ports (DFP) and upstream facing ports (UFP) rather than host and peripheral ports. Downstream facing ports includes host ports as well as any "outputs" of a USB4 hub, while upstream facing ports include anything that is connectable to a downstream facing port, like the ports of peripherals or the "input" port of a USB4 hub.[21]
Any USB4 DFP port is required to also implement USB 2.0, USB 3.2 and DP Alternative Mode support, each according to their own specifications. As such, a USB4 DFP is backwards compatible to all previous USB standards and DP output.[22]
USB 2.0 DFP features
[edit]USB 2.0 defines 3 different bit rates (Low-, Full-, High-Speed), all are required to be supported.[23] USB 2.0 abilities uses separate wires on the Type-C connector that are not used by USB 3.2 or USB4.
USB 3.x DFP features
[edit]USB 3.2, the current version, defines 3 different bit rates ("5 Gbps" a.k.a. SuperSpeed, "10 Gbps" a.k.a. SuperSpeed+, "20 Gbps" a.k.a. SuperSpeed+ 20 Gbps). While USB 3.2 specification[24] has been referenced USB4 from the start, only the 2 lower speeds (5 Gbit/s, 10 Gbit/s) are mandatory for USB4 DFPs to support.
DP Alt Mode DFP features
[edit]The USB4 specifications make no reference to a minimum feature set for its DP Alternative Mode functionality, but Thunderbolt 3 does. In practice, Intel's family of TB 3 controllers requires at least DisplayPort 1.2 at HBR2 speeds to support 4K60 output, but is also available with up to HBR3 speeds according to the DisplayPort 1.4a specification.[25]
Power transfer features for DFP
[edit]The USB4 specification makes no explicit demands on power output. It outsources all requirements in terms of power to the Type-C[26] specification that underpins all USB, DP and other standards that use the USB-C connector. This requires a USB4 DFP to supply at least 7.5W Type-C current. No power consumption features (e.g., charging of a notebook) are required, but can be supported following the USB PD specification,[5] as well as supplying considerably more power. The USB PD protocol must always have support for exchanging data according to the protocol. This is separate from any functionality of PD to negotiate actual power delivery other than 5V or >15W.
USB4 hubs & docks
[edit]USB4 hubs and docks are defined as their own category of USB4 devices that include further requirements. For example, a USB4 hub must also serve as a classic USB 3.2 hub with DP Alternative Mode passthrough with hosts that do not support USB4 connections. See USB4 capabilities by device type for more details.
USB4 protocol/connections
[edit]Every USB4 port must support the USB4 protocol/connections, which is a distinct standard to establish USB4 links/connections between USB4 devices that exists in parallel to previous USB protocols. Unlike USB 2.0 and USB 3.x, it does not provide a way to transfer data directly, it is rather a mere vessel that can contain multiple virtual connections ("tunnels").
Other specifications are referenced to define the contents and internal functionality of a tunnel. USB4 defines the following tunnel types:
- USB3 connections
- DisplayPort connections
- PCIe connections
- Ethernet/network connections according to the included USB4Net and Cross-Domain specifications[27]
General principles of USB4
[edit]USB4 forms a tree-like topology of USB4 routers, where each USB4 device includes a USB4 router to participate in this network. A tunnel can be end-to-end, where the route through the entire network of routers is preconfigured. But tunnels can also be single-hop, where it exists only for a single USB4 link (i.e., between 2 routers). In this case, the tunnel will be "unpacked" by the recipient and will use some other means specific to the tunnel type to identify where data needs to be sent next. If the next hop is another USB4 router, data will be ingested again into the next single-hop tunnel until it exits the USB4 network.[28]
Accordingly, single-hop tunnels require specific support in each USB4 router, just to support passing them through to further USB4 routers. However, end-to-end tunnels require support of a USB4 router only when the data is ingested into the tunnel and at the target, to the point where the tunnel ends.
Protocol input/output adapters
[edit]A Protocol Input Adapter will ingest a connection according to whatever protocol it is based on and convert the contents into a USB4 tunnel. Protocol Output Adapters do the reverse. They extract a tunnel from the USB4 network and if needed recreate a regular connection from the tunnel contents.
The conversion into a tunnel typically entails removing any Phy/Electrical layer and encoding of the underlying connection standard and potentially losslessly compresses the contents; for example, by leaving out empty filler data. A USB4 tunnel itself is virtual and doesn't need to conform to any fixed bandwidth or other limitations that stem from the Phy/Electrical layer of the underlying connection standard. But since most tunnel types will eventually be converted back to a regular, physical connection again, most of those physical limitations, like max. bandwidth, are still likely to apply in the end.
USB3 Gen X tunneling
[edit]This is a single-hop tunnel that essentially can transport any Enhanced SuperSpeed connection according to the USB 3.2 specification. USB3 Gen X follows the Enhanced SuperSpeed Hub topology, where every USB4 router with more than one USB3 endpoint must include a USB3 hub as well. It is the default way USB3 connections through USB4 are made. Supporting it at 10 Gbit/s (SuperSpeed USB 10 Gbps, Gen 2×1) is mandatory on every USB4 DFP. The minimum supported speed for the USB3 connection being tunneled is 10 Gbit/s as every USB4 device already has to support this speed and USB3 hubs handle converting this to 5 Gbit/s devices that may be connected.
This means, that a USB4 hub will share a single upstream USB3 connection and distribute its bandwidth across all its downstream facing ports that make use of USB3 connections.
USB3 Gen T tunneling
[edit]This is an optional alternative to USB3 Gen X tunneling that was introduced in USB4 Version 2.0. It is an end-to-end variant of USB3 Gen X tunnel.
Through this, it eschews the need for USB3 hubs in every USB4 router that can and will limit the throughput. It allows multiple separate USB3 Gen T tunnels even over shared links. Since it is an end-to-end tunnel, every USB4 hub will support passing it through. USB3 Gen T is intended as exclusively virtual, there exists no physical equivalent for it. Thus, it can only be used inside of a USB4 controller. This allows it to leave the limitations to 10 or 20 Gbit/s connections of USB 3.2 behind, while reusing most of the other parts of the Enhanced SuperSpeed protocol.[29]
No known USB4 controller implements support for Gen T tunneling to date (August 2024).
DP tunneling
[edit]DisplayPort is also tunneled as end-to-end connection. There can be multiple independent DP tunnels, but each will be delivered to a single protocol output adapter (at which point DisplayPort MST might be used to further split each connection up).
USB4 Version 1.0 only defines how to tunnel DP connections according to the DisplayPort 1.4a specification (up to HBR3 speeds). USB4 Version 2.0 updates this support to the full DisplayPort 2.1 specification (up to UHBR20 speeds). Notably, the USB4 specification explicitly carves out needing to support the UHBR13.5 DP speed, even if UHBR20 is supported. The DP specification is not public. It is unknown if it makes similar carve-outs.
DP tunneling has great understanding of the contents of DP connections, and will efficiently skip/transmit any filler data, reducing the actually utilized bandwidth of a DP tunnel. But since DP connections have real-time requirements, bandwidth must be reserved for them. USB4 mandates that in absence of any other information, the maximum possible bandwidth for the particular DP connection (DP lanes and speed) must be reserved. This reservation only applies to other real-time tunnels though. Reserved, but unused bandwidth can be used by non-real-time tunnels such as PCIe or USB3, but the reservation may still block other DP tunnels from being established.[30]
PCIe tunneling
[edit]Similar to USB3 Gen X tunneling, PCIe tunneling uses single-hop tunnels, requiring PCIe switches in every USB4 router that supports PCIe tunneling. USB4 has, from the start, referenced the PCI Express Specification Revision 4 and with USB4 Version 2.0 added references to PCI Express Specification Revision 5.0.
PCIe tunneling has had a significant limitation in USB4 Version 1.0 and also Thunderbolt 3: PCIe Express has a variable maximum payload size, which applies end-to-end to a transmission. If any one component or PCIe Switch has a limited MPS, all packets passing through must be limited accordingly. Because USB4 uses a payload of up to 256 Byte per USB4 packet and a PCIe tunnel packet contains further PCIe headers and meta data, the MPS for PCIe tunnels was limited to 128 Byte. This limitation can reduce the efficiency of the PCIe connection greatly for all devices and systems that would otherwise support 256 Byte or even larger MPS.
USB4 Version 2.0 removes this bottleneck (mandatory for all implementers), by defining how a larger PCIe packet can be split across multiple USB4 packets. Support for this new feature requires every USB4 component / controller involved in the PCIe tunnel to implement USB4 Version 2.0.[31]
USB4 signaling modes
[edit]Signaling refers to the lowest layer of the OSI Model, also called physical layer or phy. USB4 connections can be expressed with consumer facing names that are also the basis for the official logos used on packaging and products. These are the "20 Gbps", "40 Gbps", "80 Gbps" labels and they do not explicitly indicate how the connection is achieved on the physical layer. There are also more technical names based on the implementation and use of the USB-C cables. These usually consist of a speed per wire-pair expressed as Gen 1/2/3/4 (5 Gbit/s, 10 Gbit/s, 20 Gbit/s, 40 Gbit/s respectively) and some further information on how many wire-pairs are used in which combination.
USB commonly defines a "Lane" as a (bidirectional) connection, which for all recent transmission modes consists of one sending and one receiving wire-pair. The "Gen AxB" notation refers to B Lanes of operation mode A. Since Gen 4 modes also introduced asymmetric connections with uneven numbers of wire-pairs dedicated to sending and receiving, the Lane-notation is no longer applicable.
The USB 3.x family has had the same technical notation retroactively added in the USB 3.1 and USB 3.2 specification versions. Though this shows common principles and the same generations refer to the same nominal speeds, "Gen A" does not have the same exact meaning in both USB 3.x and USB4 specifications. The overlap in naming mainly becomes relevant for cables as shown in Cable Compatibility, which is regulated by the Type-C specification shared across all users of Type-C connector.
USB family
|
Signaling mode name[a] | Introduced in | Encoding | Wire-pairs sending/receiving | Raw bit rate (Gbit/s) |
Net data rate[b] (Gbit/s) |
USB-IF current marketing name[32] |
Logo[32] | |
|---|---|---|---|---|---|---|---|---|---|
| per wire-pair | total (per direction) | ||||||||
USB 2.x
|
High-Speed | USB 2.0 | NRZI with bit stuffing | 1 (shared) | 0.480 (half-duplex) | 0.480 (half-duplex) | ? | Hi-Speed USB | |
USB 3.x
|
Gen 1×1 | USB 3.0 | 8b/10b | 1/1 | 5 | 5 | 4 | USB 5Gbps | |
| Gen 2×1[c] | USB 3.1 | 128b/132b | 1/1 | 10 | 10 | ~9.7 | USB 10Gbps | ||
| Gen 1×2 | USB 3.2 | 8b/10b | 2/2 | 5 | 10 | 8 | (fallback)[d] | ||
| Gen 2×2[c] | 128b/132b | 2/2 | 10 | 20 | ~19.39 | USB 20Gbps | |||
USB4
|
Gen 2×1[c] | USB4 v1.0 | 64b/66b[e] | 1/1 | 10 | 10 | ~9.697 | (transient/fallback)[f] | |
| Gen 2×2[c] | 2/2 | 10 | 20 | ~19.39 | USB 20Gbps | ||||
| Gen 3×1 | 128b/132b[e] | 1/1 | 20 | 20 | ~19.39 | (transient/fallback)[f] | |||
| Gen 3×2 | 2/2 | 20 | 40 | ~38.79 | USB 40Gbps | ||||
| Gen 4 symmetric | USB4 v2.0 | PAM-3[33]
11b/7t |
2/2 | ~40.58[g] | ~81.15 | ~80.46 | USB 80Gbps | ||
| Gen 4 asymmetric 3:1 | 3/1 | 3×: ~121.725 1×: ~40.58 |
3×: ~120.69 1×: ~40.23 |
—[h] | |||||
| Gen 4 asymmetric 1:3 | 1/3 | —[h] | |||||||
| — | TB3 Gen 2×2 | — | 64b/66b | 2/2 | 10.3125 | 20.625 | 20 | — | |
| TB3 Gen 3×2 | 128b/132b | 2/2 | 20.625 | 41.25 | 40 | — | |||
- ^ Names according to the newest specifications.
- ^ Total data rate (1 direction) with encoding overhead removed.
- ^ a b c d USB4 Gen 2 is different from USB3 Gen 2. They both signify the same signal rate of 10 Gbit/s, but use different encoding and differ on the electrical layer. They also have different requirements for signal quality.
- ^ USB3 Gen 1×2 connection requires both sides to be USB3 "20 Gbps" / Gen 2×2 capable, but fail to establish Gen 2 / 10 Gbit/s per wire-pair connections.
- ^ a b USB4 Gen 2 & 3 can use optional Reed–Solomon forward error correction (RS FEC). In this mode, 12 × 16 B (128 bit) symbols are assembled together with 2 B (12 bit + 4 bit reserved) synchronisation bits indicating the respective symbol types and 4 B of RS FEC to allow to correct up to 1 B of errors anywhere in the total 198 B block.
- ^ a b USB4 is required to support dual-lane modes, but it uses single-lane operations during initialization of a dual-lane link; single-lane link can also be used as a fallback mode in case of a lane bonding error.
- ^ Per spec, lines run at 25.6 GBaud. One symbol contains 1 trit of information. Encoding transforms each group of 11 bits into 7 trits. 7 trits give 2187 different values or bits/trit. USB4 Version 2.0 Specification 2023, p84, sec. 3.2
- ^ a b Optional features of USB 80Gbps connections and devices.
Thunderbolt 3 Gen 2 and Gen 3 and the USB4 Gen 2 and Gen 3 modes use very similar signaling. However, Thunderbolt 3 runs at slightly higher speeds, called legacy speeds, compared to rounded speeds of USB4.[34] It is driven slightly faster at 10.3125 Gbit/s (for Gen 2) and 20.625 Gbit/s (for Gen 3), as required by Thunderbolt specifications.
USB4 Gen 4 is normally referred to as a speed of "40 Gbps" or 40 Gbit/s, with the full connections based on it being referred to as 80, 120/40, 40/120 Gbit/s. But since the actual signaling is no longer binary, the actual raw bit rates no longer match those numbers exactly.
USB4 capabilities by device type
[edit]USB4 hub
[edit]A USB4 hub is defined by having 1 USB4 UFP and one or more USB4 DFP.
USB4-based dock
[edit]A USB4-based dock is defined as a USB4 hub that also has more specialized outputs like HDMI or DP, but still keeping some USB4 DFP.
USB4 peripheral device
[edit]A USB4 peripheral device is defined by not having any USB4 DFP. This means devices that are colloquially called "USB-C hubs" may use USB4 to support the dynamic bandwidth sharing or higher bandwidths of USB4. But they are not USB4 hubs if they do not have any USB4 DFP. Not having any USB4 DFP allows the peripheral to only support exactly those USB4 features that it has uses for, potentially simplifying its implementation considerably.
| Feature | Host | Hub (dock) | Peripheral device | |
|---|---|---|---|---|
| Type | ||||
| USB4
connection |
"20 Gbps" (Gen 2×2) | Yes | Yes | Yes |
| "40 Gbps" (Gen 3×2) | Optional | Yes | Optional | |
| "80 Gbps" (Gen 4 symm.) | Optional | Optional | Optional | |
| "120/40 Gbps" (Gen 4 3:1) | Optional | Optional[a] | Optional | |
| "40/120 Gbps" (Gen 4 1:3) | Optional | Optional[a] | Optional | |
| Tunneled | USB3 "10 Gbps" (Gen 2×1) | Yes | Yes | Optional |
| USB3 "20 Gbps" (Gen 2×2) | Optional | Optional | Optional | |
| USB3 Gen T (variable bandwidth)[b] | Optional | Optional | Optional | |
| DisplayPort | Yes | Yes | Optional | |
| PCI Express | Optional[c] | Yes | Optional | |
| Host-to-host communications/
USB4 networking |
Yes | Yes | — | |
| Native | USB3 "5 Gbps" (Gen 1×1) | Yes | Yes | Optional |
| USB3 "10 Gbps" (Gen 2×1) | Yes | Yes | Optional | |
| USB3 "20 Gbps" (Gen 2×2) | Optional | Optional | Optional | |
| USB 2.0
(Low-, Full-, High-Speed)[d] |
Yes | Yes | Optional | |
| DisplayPort Alternate Mode[e] | Yes | Yes | Optional | |
| Thunderbolt Alternate Mode | Optional[c] | Yes | Optional | |
| Other alternate modes | Optional | Optional | Optional | |
- ^ a b Even for "80 Gbps" USB4 hubs, supporting asymmetric connections (in either direction) is optional, but 80 Gbit/s support is a prerequisite for any asymmetric support.
- ^ USB3 Gen T tunneling has defined bandwidth options. They match the total USB4 speed numbers 10,20,40,80 and even asymmetric 40/120,120/40 connections. USB4 v2 specification, p536, tab.9-19
- ^ a b Windows HLK requires any USB4 port support PCIe tunneling and TB3 compatibility. No minimum PCIe bandwidth requirements.[36]
- ^ As with USB3, USB2 connection runs on separate wires from main (USB3/USB4) connection. Tunneling is not required as it runs in parallel on the cable.
- ^ The USB4 specification makes no requirements on the minimum speed or capabilities of any DP output.
Cable compatibility
[edit]The Type-C standard supports cable backward/downward compatibility in many situations. The compatibility typically only breaks between the different families of standards (USB 2.0, USB 3.2, USB4). The USB4 standard mandates that classic active or hybrid active cables still have vast backward compatibility support, so as to behave as if they were regular, passive cables in the eyes of the consumer.[37] But forward compatibility is limited for active cables. Only optically isolated active cables (OIAC), which should be clearly distinguishable by price, design, cable thickness, and advertising, are allowed to strip most of the backwards compatibility away.
The Gen 4 transmission mode with PAM-3 uses signalling very different from that of previous modes. Every active component needs to explicitly support this new signaling, but it stays within all signal quality requirements of existing, passive Gen 3 cables (USB4 and TB3).
Cable naming and relation to specification versions
[edit]USB-IF intends only for the new bandwidth-based logos and names to be used with consumers.[38] For cables, the type (passive, active) and the highest supported bandwidth are usually enough to uniquely identify a cable and its supported features. Although some active types make clear distinctions where further details on the type are required. Formally, a cable type and properties are defined by a distinct specification version, which was used during the development/design of said cable model, so each cable would be a valid and possibly certified cable according to a specific set of USB specification versions, like "Type-C 2.3, USB 3.2, USB4 Version 2.0". But the standard is also designed to be interoperable, in that a newer specification version typically adds new modes of operation, new cable types, but does not restrict previously existing things. Because that would make existing things incompatible with new products. For this purpose, even the older USB logos and labels did not include a specification version, but only stated "Certified USB SuperSpeed+ 10 Gbps". This logo identified cables that could support the 10 Gbit/s connection speeds of USB3 across both the USB 3.1 and USB 3.2 version, because the requirements for the cables have not changed. Thus, a precise specification version is usually not relevant and would not make a difference.
Transmission modes such as Gen2×2 are also irrelevant to cables, as valid cables are either full-featured, having all the high speed wire-pairs for up to dual-lane connections at the stated speed or they are USB2-only or some other specific and restrictive type, as listed below.
USB4 cable compatibility
[edit]| Cable type | Speed | Marketing names | Max. USB4 bit rate | Expected max. cable length[a] | Other support | Power | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| Remarks | USB2 | USB3 | TB3 | DP | ||||||
USB2
|
— | Hi-Speed USB | ≤ 4m | Yes | No | No | No | USB PD:
60W or 100W or 240W | ||
Full-Featured passive
|
— | Gen 1 | USB 5Gbps | 20 Gbit/s[b] | ≤ 2m | Yes | 5 Gbit/s | No | Yes[c] | |
| Gen 2 | USB 20Gbps
(USB 10Gbps deprecated) |
20 Gbit/s | ≤ 1m | Yes | Yes | 20 Gbit/s | ||||
| (incl. passive TB4 & TB5) | Gen 3 & Gen 4 | USB 40Gbps
USB 80Gbps |
80 Gbit/s
(or asymm.) |
≤ 0.8m | Yes | Yes | Yes[d] | Yes[c][e] | ||
Full-Featured active (also optical hybrid)
|
— | Gen 2 | USB 20Gbps
(USB 10Gbps deprecated) |
20 Gbit/s | < 5m | Yes | Yes | Yes | Optional[f] | |
| (incl. active TB4) | Gen 3 | USB 40Gbps | 40 Gbit/s | Yes | Yes | Yes | Optional[f]
TB up to 2m[e] | |||
| (incl. active TB5) | Gen 4 | USB 80Gbps | 80 Gbit/s
(or asymm.) |
Yes | Yes | Yes | ||||
| USB3 active | Gen 2 | ? | Yes | Yes | No | Optional | ||||
OIAC
|
USB3 | Gen 2 | ? | ≤ 50m | only if optical | Gen 2 only (10 / 20 Gbit/s) | No | Optional | — | |
| USB4 | Gen 3 | ? | 40 Gbit/s | Optional | ||||||
| Gen 4 | ? | 80 Gbit/s
(asymm. optional) | ||||||||
Thunderbolt 3
|
passive | Gen 2 | TB Logo without "3" | 20 Gbit/s | ≤ 2m | Yes | only 5 Gbit/s when > 1m[42] | 20 Gbit/s | Yes[c] | USB PD:
60W or 100W |
| Gen 3 | TB Logo + "3" | 80 Gbit/s
(or asymm.)[43] |
≤ 0.8m | Yes | Yes | Yes | ||||
| active | Gen 3 | TB Logo + "3" | (longest available: 3m) | Yes | (mostly no)[44] | Yes | (mostly no)[45] | |||
| optical[46] | Gen 3 | TB Logo + "3" | ? | No | No | Yes | No | — | ||
- ^ Maximum cable lengths are not normative, but simply estimates of the USB specification, based on the expected physical limits of conventional copper cables.
- ^ USB4 Gen 2 has less strict signal requirements than USB 3 Gen 2. Spec compliant USB3 Gen 1 cables should support USB4 Gen 2 / 20 Gbit/s connections
- ^ a b c No specific max. DP speed guaranteed by Type-C specification
- ^ USB4 launched with passive Gen 3 cables supporting TB3 40 Gbit/s on an electrical level, but where not mandated to identify in the historical way TB3 identified those cables (because that predates the existence of "Gen 3"). Early passive USB4 cables may thus not be identified as TB3 40 Gbit/s capable by old TB3 equipment predating the existence of USB4. This was fixed with a later revision.[citation needed]
- ^ a b TB4 & TB5 cables up to 2m length (active & passive) are "universal cables", including DP support. DP guarantees may only include the highest speeds covered by DP 1.4 for TB4 (HBR3) or DP 2.1 for TB5 (UHBR20).
- ^ a b No specific max. DP speed guaranteed by Type-C specification. There are different implementations of active cable implementations that may behave differently.
- ^ The Apple TB3 Pro cable is one of the few active TB3 cables that supports DP and USB3. It is unclear if that is special behavior or the cable would be compatible to USB4 as well."Apple now sells a $129 Thunderbolt 3 Pro cable". theverge.com. The Verge. 2020-07-27. Retrieved 2024-08-09.
DP Alt Mode support for USB4 cables
[edit]The Type-C specification does not name specific DP speeds that it considers supported for passive cables where support is optional for active cables. The USB-C presentation on DP Alt mode[47] calls out passive full-featured USB-C cables for their DisplayPort support and headroom for future DP speed increases. HBR3 was the highest available DP speed at the time.
Active cables may have additional complications, because the active electronics does not need to operate all high speed wire-pairs in the same direction for normal USB operations (but "80 Gbps" cables are mandated to support asymmetric connections, which includes at least some of the wire-pairs operating in either direction). Active cables can have further limitations, since the active electronics may only support specific signaling modes. There are 2 variants of active electronics. Linear ReDrivers only amplify the signal without any particular signaling mode or encoding in mind. ReTimers explicitly reconstruct the incoming signal for a higher quality result.
TB4 cables, even active ones, at least up to 2m in length, are guaranteed to support DP Alt mode. A specific maximum speed is also not mentioned, but the other requirements for TB4 all refer to DP 1.4 and its maximum speed of HBR3.[48] TB5 renews the same guarantee[49] for "80 Gbps" cables while referencing the DP 2.1 specification (up to UHBR20 speeds).
DP 2.1 aligned itself to the USB4 PHY layer, according to VESA, the creator of DisplayPort.[50] It is unclear how complete this alignment is. However, the UHBR10 DP speed matches USB4 Gen 2 in bit rate and encoding, whereas the UHBR20 DP speed matches USB4 Gen 3 in bit rate and encoding. A USB and DP certification service lists USB Gen 1 cables ("5 Gbps") as supporting UHBR10 speeds, which would fit for having the same requirements as USB4 "20 Gbps" connections.[51]
Anandtech reports[52] that "this also means that DP Alt Mode 2.0 should largely work with USB4-compliant cables, although VESA is being careful to avoid promising compatibility with all cables".
There are linear redrivers[53] and retimers[54] available that are advertised for USB4 Gen 3 speeds and all current DP speeds up to UHBR20 and including UHBR13.5.
Thunderbolt compatibility
[edit]USB4 is a backward-compatible extension of Thunderbolt 3. Thunderbolt 4 and Thunderbolt 5 are profiles of USB4 specifying higher levels of mandatory features.
Thunderbolt 3
[edit]The USB4 specification states that a design goal is to "Retain compatibility with existing ecosystem of USB and Thunderbolt products." Compatibility with Thunderbolt 3 is required for USB4 hubs, where this is optional for USB4 hosts and USB4 peripheral devices.[55] Compatible products need to implement 40 Gbit/s mode, at least 15W of supplied power and a different clock. Implementers need to sign the license agreement and register a Vendor ID with Intel.[56]
The USB4 protocol is based on and related to the operating principles of Thunderbolt 3. The USB4 specification simply defines which features to disable, downgrade and which parameters to change to get to an implementation compatible with Thunderbolt 3.[57] This includes, for example: limitation to daisy-chain topology (a hub must expose at most one USB4 DFP), downgrade of DP capabilities to DP 1.2, disabling/replacing the USB3 tunnel with an integrated PCIe-USB3 Host controller attached via PCIe tunnel, switching back to the previous, slightly higher signaling rate of TB3 and its separate way of initiating a connection as an Alt Mode.
Thunderbolt 4
[edit]During CES 2020, USB-IF and Intel stated their intention to allow USB4 products that optionally support any or all of the same functionality as Thunderbolt 4 products. The first products compatible with USB4 were Intel's Tiger Lake processors, with more devices appearing around the end of 2020.[58][59]
Thunderbolt 4 is an implementation of USB4. Thunderbolt 4 mandates some features that are optional in USB4, including backwards compatibility to Thunderbolt 3, minimum PCIe ("32 Gbps") and DP capabilities (2 DP tunnels, "4K60 each", HBR3+DSC).[60]
Thunderbolt 5
[edit]Thunderbolt 5 is an implementation of USB4 "80 Gbps". It mandates even higher minimum PCIe ("64 Gbps") and DP capabilities (2 DP tunnels, "6K60 each", unclear min. DP speed). It also mandates support for asymmetric 120/40 Gbit/s connections from hosts to docks, but does not mention the reverse.[61]
Pinout
[edit]
USB4 has 24 pins in a symmetrical USB Type-C shell. USB4 has 12 A pins on the top and 12 B pins on the bottom.[62]
USB4 has two lanes of differential SuperSpeed pairs. Lane one uses TX1+, TX1−, RX1+, RX1− and lane two uses TX2+, TX2−, RX2+, RX2−. USB4 transfers signals at 20 Gbit/s per lane. USB4 also keeps the differential D+ and D− for USB 2.0 transfer.[63]
The CC configuration channels have roles of creating a relationship between attached ports, detecting plug orientation due to the reversible USB Type-C shell, discovering the VBUS power supply pins, determining the lane ordering of the SuperSpeed lanes and, finally, the USB protocol makes the CC configuration channel responsible for entering USB4 operation.[64]
| Pin | Name | Description |
|---|---|---|
| A1 | GND | Ground return |
| A2 | SSTXp1 ("TX1+") | SuperSpeed differential pair #1, TX, positive |
| A3 | SSTXn1 ("TX1-") | SuperSpeed differential pair #1, TX, negative |
| A4 | VBUS | Bus power |
| A5 | CC1 | Configuration channel |
| A6 | Dp1 | USB 2.0 differential pair, position 1, positive |
| A7 | Dn1 | USB 2.0 differential pair, position 1, negative |
| A8 | SBU1 | Sideband use (SBU) |
| A9 | VBUS | Bus power |
| A10 | SSRXn2 ("RX2-") | SuperSpeed differential pair #4, RX, negative |
| A11 | SSRXp2 ("RX2+") | SuperSpeed differential pair #4, RX, positive |
| A12 | GND | Ground return |
| Pin | Name | Description |
|---|---|---|
| B12 | GND | Ground return |
| B11 | SSRXp1 | SuperSpeed differential pair #2, RX, positive |
| B10 | SSRXn1 | SuperSpeed differential pair #2, RX, negative |
| B9 | VBUS | Bus power |
| B8 | SBU2 | Sideband use (SBU) |
| B7 | Dn2 | USB 2.0 differential pair, position 2, negative[a] |
| B6 | Dp2 | USB 2.0 differential pair, position 2, positive[a] |
| B5 | CC2 | Configuration channel |
| B4 | VBUS | Bus power |
| B3 | SSTXn2 | SuperSpeed differential pair #3, TX, negative |
| B2 | SSTXp2 | SuperSpeed differential pair #3, TX, positive |
| B1 | GND | Ground return |
Software support
[edit]USB4 is supported by:
- Linux kernel 5.6, released on 29 March 2020[65]
- macOS Big Sur (11.0), released on 12 November 2020[66]
- Windows 11, released with support for USB4 Version 1.0 on 5 October 2021[67]
- upgraded to USB4 Version 2.0 support including 80 Gbit/s around March 2024[68]
Connection manager
[edit]Connection manager is the part of a USB4 host that manages connections across the entire USB4 topology, establishing of tunnels, handling any bandwidth reservations and data prioritization, like which DP tunnels can be established and at what speed. The USB4 driver in Windows 11 implements native OS support of USB4, where the connection manager is part of a driver that only works with matching controllers. Older controllers had the connection manager implemented inside their firmware and thus required far less support from the OS.
On Linux, the USB4 and Thunderbolt driver (named "thunderbolt") supports both firmware-managed and also OS-managed controllers via the same tools.
Hardware support
[edit]Brad Saunders, CEO of the USB Promoter Group, anticipates that most PCs with USB4 will support Thunderbolt 3, but for phones the manufacturers are less likely to implement Thunderbolt 3 support.[69]
On 3 March 2020, Cypress Semiconductor announced new Type-C power (PD) controllers supporting USB4, CCG6DF as dual port and CCG6SF as single port.[70]
In November 2020, Apple unveiled MacBook Air (M1, 2020), MacBook Pro (13-inch, M1, 2020) and Mac mini (M1, 2020), featuring two USB4 ports.
AMD also stated that Zen 3+ (Rembrandt) processors will support USB4[71] and released products do have this feature after a chipset driver update.[72] However, AMD has only announced support for USB 3.2 Gen 2×2 in Zen 4 processors that were released in September 2022.[73][74] Intel supported Thunderbolt 3 and USB-C with their 8th generation mobile processors in 2018. For example, the Lenovo P52 has dual TB3 ports on the rear. TB/USB has evolved as Intel is able to refine logic design.
Manufacturer
|
Controller | Family | Type | native managed[a]
|
USB4 ver.
|
Speed Gbit/s
|
USB4 Ports
(up / down) |
DP In / out
protocol adapters[b] |
USB3
Gbit/s |
PCIe[c] | TB3 compat.
|
Other ports | Certified |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Intel
|
JHL8540[75] | Maple Ridge | Host | No | 1 | 40 | 2 dn | 2 in
DP 1.4 (up to HBR3) |
10
(integ. ctrl.) |
x4 Gen 3 ("32 Gbit/s") | Yes | — | TB4 |
| JHL8440[76] | Goshen Ridge | Hub / Peri. | — | 1 up,
3 dn |
2 out
DP 1.4 (up to HBR3) |
10
(hub, integ. ctrl.) |
(32 Gbit/s) | PCIe x1 Gen 3 dn,
1 USB3 dn | |||||
| JHL8140[citation needed] | Hoover Ridge | Peri. | 1 up | 2 out
DP 1.4 (up to HBR3) |
10
(hub, integ ctrl.) |
— | 3 USB3/DP down,
1 USB3 dn | ||||||
| JHL9450[77] | Barlow Ridge | Host | Yes | 2 | 2 dn | 3 in
DP 2.1 (up to UHBR10, +UHBR20)[d] |
20
(integ. ctrl.) |
x4 Gen 4 ("64 Gbit/s") | 1 DP out[e] | ||||
| JHL9440[78] | Hub / Peri. | — | 1 up,
3 dn |
3 out
2 in DP 2.1 (up to UHBR10, +UHBR20)[d] |
20
(hub, integ. ctrl.) |
x4 Gen 4 ("64 Gbit/s") | 2 DP in,
1 USB3 dn | ||||||
| JHL9580[79][80] | Host | Yes | 80 | 2 dn | 3 in
DP 2.1 (up to UHBR10, +UHBR20)[d] |
20
(integ. ctrl.) |
x4 Gen 4 ("64 Gbit/s") | 1 DP out[e] | TB5 | ||||
| JHL9480[81] | Hub / Per. | — | 1 up,
3 dn |
3 out
2 in DP 2.1 (up to UHBR10, +UHBR20)[d] |
20
(hub, integ. ctrl.) |
x4 Gen 4 ("64 Gbit/s") | 2 DP in,
1 USB3 dn | ||||||
| Tiger Lake[82] | CPU-integrated | Host | No | 1 | 40 | up to
2 + 2 dn[f] |
2 in/group:
up to HBR3 |
10 | (32 Gbit/s) | — | TB4 | ||
| Alder Lake[83] | Yes | 10[g] | — | ||||||||||
| Raptor Lake[84] | 10
(20 internal)[g] |
native output:[h]
DP UHBR10, +UHBR20,[d] USB3 20G | |||||||||||
| Meteor Lake[85] | ? | 20[g] | native output:[h]
DP UHBR10, +UHBR20[d] | ||||||||||
| Lunar Lake[86] | up to
2 +1 dn[f] | ||||||||||||
| Arrow Lake[87] | 2 dn | ||||||||||||
AMD
|
AMD CPU-integrated[citation needed] | — | 1 | up to 1+1 dn[f] | 2 in/port
up to HBR3 |
10 | — | native output:[h]
DP UHBR10 |
? | ||||
Apple
|
M1/2 | Apple USB4/TB3 | Host | ? | 1 | 40 | ? | 1 in/port
up to HBR3 |
10 | — | — | TB3 | |
| M1-3 Pro, Max, M4 | Apple TB4 | 2 in/port
up to HBR3 |
TB4 | ||||||||||
| M3 Ultra,
M4 Pro/Max[citation needed] |
Apple TB5 | 2 | 80 | 2 in/port
up to UHBR10, +UHBR20[d] |
TB5 | ||||||||
Via
|
VL830[88] | — | Peri. | — | 1 | 40 | 1 up | 1 out: DP 1.4 (up to HBR3) | 10 (hub) | No | No | 5 USB3 dn,
1 USB2 dn |
— |
| VL832[89] | USB4 | ||||||||||||
Asmedia
|
ASM2464PD[90] | Peri. / NVMe | 1 up | — | 20 (peripheral) | x4 Gen 4 ("64 Gbit/s") | Yes | (USB3 NVMe ctrl., only integ. PD) | USB4, TB4 | ||||
| ASM2464PDX[91] | Peri. / NVMe | 1 up | 20 (peripheral) | x4 Gen 4,
(bifurcat. x1) |
Yes | (USB3 NVMe ctrl.) | ? | ||||||
| ASM4242[92] | Host | Yes | 2 dn | 2 in: DP 1.4 (up to HBR3) | 20 (integ. ctrl.) | x4 Gen 4 ("64 Gbit/s") | Yes | — | USB4,
TB4 | ||||
Realtek
|
RTX5490[93][94] | Peri. / Hub | — | 2? | 40 | 2 dn | USB4 up/dn: UHBR20, ? | 20 (hub, integ. ctrl.) | ? | Yes | 2 USB3 20G, 1 DP UHBR20 | — |
- ^ Host controller is not managing itself with onboard firmware, but via ACPI and USB4 standard with generic OS drivers, such as Windows 11 USB4 drivers. Only applicable to host controllers. All other controllers have always been managed by the host's connection manager, no matter if that is implemented in firmware or by the OS.
- ^ Protocol adapters are what converts between a tunnel and a connection external to USB4. DP In adapters map directly to some input from a GPU. DP Out adapters may be shared across multiple physical outputs, in which case they limit how many can be used at the same time.
- ^ Main PCIe port of the controller. Not applicable for CPU-integrated host controllers. If PCIe is only used internal to the controller, PCIe throughput specifications are rarely given.
- ^ a b c d e f g Supports UHBR10 and all lower speeds. And UHBR20, while not supporting UHBR13.5 speeds. UHBR10 and UHBR20 are aligned to USB4 Gen 2 and Gen 3 respectively, UHBR13.5 is not aligned to any existing USB4 signaling.
- ^ a b Unclear how much the output can do / be used for yet. Per leak "side port", may only be a passthrough of the third DP input
- ^ a b c "2+2" indicates 2 separate dual-port USB4 host routers. But because integrated into the CPU, can share functionality that is not technically part of USB4 host router, like USB3. Systems may share a common USB3 controller, supplying 1 USB3 root port per USB4 port, similar with PCIe ports.
- ^ a b c What the respective USB4 ports can output directly, instead of tunneled through USB4. Can be higher than tunneled support, as not limited by the USB4 specification and technically independent of USB4 operations/connections.
References
[edit]- ^ USB4 Version 2.0 Specification 2023
- ^ "USB-IF Announces Publication of New USB4 Specification to Enable USB 80Gbps Performance" (PDF). 2022-10-18.
- ^ Type-C Cable and Connector Specification 2023
- ^ Type-C Cable and Connector Specification, p216f, sec. 4.6
- ^ a b USB Power Delivery Specification 2023
- ^ USB4 Version 2.0 Specification 2023, p1, sec. 1.5, p12, sec. 2
- ^ USB4 Version 2.0 Specification 2023, p15, sec. 2.1.5
- ^ Hill, Brandon (2019-03-04). "USB4 Leverages Thunderbolt 3 Protocol Doubling Speeds To 40Gbps". HotHardware. Archived from the original on 2021-10-23. Retrieved 2020-04-28.
- ^ "USB4 announced with 40Gbps bandwidth, it's based on Thunderbolt 3". GSMArena.com. Archived from the original on 2022-01-15. Retrieved 2020-04-29.
- ^ "With USB 4, Thunderbolt and USB will converge". 2019-03-04. Archived from the original on 2022-09-10. Retrieved 2020-05-01.
- ^ Hagedoorn, Hilbert (2019-06-13). "USB 4.0 Will Arrive in Late 2020". Guru3D. Archived from the original on 2021-10-26. Retrieved 2020-04-30.
- ^ USB Promoter Group (2019-03-04). "USB Promoter Group Announces USB4 Specification" (PDF). usb.org. Retrieved 2024-12-21.
- ^ "USB4 Specification". p1, sec 1.4 Design Goals. Archived from the original on 2021-04-19.
- ^ Dr. Cutress, Ian (2020-07-08). "Intel Thunderbolt 4 Update: Controllers and Tiger Lake in 2020". Archived from the original on 2020-07-08. Retrieved 2024-12-21.
- ^ "Introducing Thunderbolt 4: Universal Cable Connectivity for Everyone". 2020-07-08. Retrieved 2024-12-21.
- ^ "USB Promoter Group Announces USB4 Version 2.0". www.businesswire.com. 2022-09-01. Archived from the original on 2022-09-02. Retrieved 2022-09-02.
- ^ "USB-IF Announces Publication of New USB4 Specification to Enable USB 80Gbps Performance" (PDF). USB-IF. USB Implementers Forum. 2022-10-18. Retrieved 2023-01-19.
- ^ Porter, Jon (2022-09-30). "USB kills off SuperSpeed branding as it tries to simplify its ubiquitous connector". The Verge. Retrieved 2024-08-05.
- ^ Ganesh, T S (2023-10-12). "Intel Unveils Barlow Ridge Thunderbolt 5 Controllers - TB5 Launching In 2024". Archived from the original on 2023-09-12. Retrieved 2024-12-21.
- ^ "Intel Introduces Thunderbolt 5 Connectivity Standard". 2022-10-12. Retrieved 2024-12-21.
- ^ USB4 Version 2.0 Specification 2023, p13ff, fig. 2-1 USB4/USB3.2 Dual Bus System Architecture
- ^ USB4 Version 2.0 Specification 2023, p12ff, sec. 2 Architectural Overview
- ^ USB 2.0 Specification 2024
- ^ USB 3.2 Specification 2022
- ^ "Intel® JHL8540 Thunderbolt™ 4 Controller Product Specifications". www.intel.com. Retrieved 2024-08-06.
- ^ Type-C Cable and Connector Specification 2023, p244 sec. 5.3
- ^ USB4 Version 2.0 Specification Inter-Domain Service 2023
- ^ USB4 Version 2.0 Specification 2023, p13
- ^ USB4 Version 2.0 Specification 2023, p487
- ^ USB4 Version 2.0 Specification Connection Manager Guide 2023, p59, sec. 6.1
- ^ USB4 Version 2.0 Specification 2023, p660, sec. 11.1.1.1.3
- ^ a b USB Trademark Requirements Chart from USB-IF
- ^ Team GraniteRiverLabs (2023-01-17). "Welcome to the 80Gpbs Ultra-High Speed Era of USB4". www.graniteriverlabs.com. GraniteRiverLabs Taiwan. Archived from the original on 2023-02-21. Retrieved 2023-02-21.
- ^ "How to Test and Troubleshoot USB4" (PDF). Archived (PDF) from the original on 2022-09-10. Retrieved 2022-07-25.
- ^ USB4 Version 2.0 Specification 2023, p17ff, sec. 2.1.1.4
- ^ windows-driver-content (2022-05-18). "USB4 Systems PCIe Tunneling Support". learn.microsoft.com. Retrieved 2024-08-05.
- ^ Type-C Cable and Connector Specification 2023, p261 para. 3
- ^ "USB Branding Session 2019" (PDF). usb.org. 2020-02-07. p16. Retrieved 2024-07-08.
- ^ Type-C Cable and Connector Specification 2023, p42, Tab 3-1
- ^ "How to Beat the Maximum USB Cable Length Limit". blog.tripplite.com. Retrieved 2024-03-14.
- ^ Type-C Cable and Connector Specification 2023, p261 sec. 6
- ^ "Cable Matters 107002 40 Gbps / 20 Gbps Thunderbolt 3 Cable". kb.cablematters.com. 2024-10-09. Retrieved 2024-08-12.
When connected to USB-C devices, the data rate can reach 10 Gbps (0.5m & 1m) and 5 Gbps (2m).
- ^ Type-C Cable and Connector Specification 2023, p246, fig. 5-1
- ^ "USB-C Cables, Thunderbolt 3 Cables - How to tell them apart". archive.caldigit.com. CalDigit. Retrieved 2024-08-08.
- ^ "How to select a Thunderbolt 3 cable?". chargerlab.com. 2019-05-11. Retrieved 2024-08-08.
- ^ "Corning Thunderbolt™ 3 Optical Cable (40 Gb/s)" (PDF). Corning. Retrieved 2024-08-08.
- ^ "VESA – DisplayPortTM Alternate Mode on USB-C®" (PDF). 2019-11-19. p23. Retrieved 2024-08-08.
- ^ "Intel Thunderbolt 4™ Announcement Press Deck" (PDF). Intel. p9, p13. Retrieved 2024-08-08.
- ^ "Thunderbolt 5™ Press Deck" (PDF). thunderbolttechnology.net. Intel. Retrieved 2024-08-09.
- ^ "VESA Releases DisplayPort 2.1 Specification". Retrieved 2024-08-06.
- ^ "Specification and Test Overview of DisplayPort™ 2.1". Granite River Labs. Ultra High Bit Rate in DisplayPort™ 2.1. Retrieved 2024-08-08.
- ^ "DisplayPort Alt Mode 2.0 Spec Released: Defining Alt Mode for USB4". Anandtech. Archived from the original on 2020-04-30. Retrieved 2024-08-08.
- ^ "PI2DPX2020". Diodes. 2011-03-02. Retrieved 2024-08-08.
- ^ "KM864742". Nuvoton. Retrieved 2024-08-09.
- ^ USB4 Specification V1.0 August 2019 Chapter 13: "A USB4 host and USB4 peripheral device may optionally support TBT3-Compatibility. If a USB4 host or USB4 peripheral device supports TBT3-Compatibility, it shall do so as defined in this chapter".
- ^ "USB4 Thunderbolt3 Compatibility Requirements Specification – USB-F". Archived from the original on 2021-11-24. Retrieved 2021-11-13.
- ^ USB4 Version 2.0 Specification 2023, p709ff, sec. 13 Interoperability with Thunderbolt 3 (TBT3) Systems
- ^ "USB4 devices are clear to roll out next year". Engadget. 2019-09-03. Archived from the original on 2021-11-24. Retrieved 2020-04-28.
- ^ Maislinger, Florian (2019-06-14). "First USB 4 devices to be launched at the end of 2020". Archived from the original on 2021-11-24. Retrieved 2020-04-28.
- ^ "Intel Thunderbolt 4 Announcement Press Deck" (PDF). thunderbolttechnology.net. Intel. p4. Retrieved 2024-08-08.
- ^ "Thunderbolt 5™ Press Deck" (PDF). thunderbolttechnology.net. Intel. p19. Retrieved 2024-08-09.
- ^ "The Relationship Between USB4 and the USB Type-C Connector". Total Phase Blog. 2020-02-18. Archived from the original on 2022-09-10. Retrieved 2022-04-05.
- ^ "USB4 Specification". www.usb.org. Archived from the original on 2022-04-14. Retrieved 2022-04-05.
- ^ Leung, Benson (2018-11-19). "USB Type-C's Configuration Channel". Medium. Archived from the original on 2022-04-05. Retrieved 2022-04-05.
- ^ "Linux 5.6 Kernel Released With WireGuard, USB4, New AMD + Intel Hardware Support – Phoronix". Phoronix.com. Archived from the original on 2021-11-02. Retrieved 2020-04-28.
- ^ "Introducing the next generation of Mac". apple.com. 2020-11-10. Archived from the original on 2021-03-01. Retrieved 2020-11-13.
- ^ "Introduction to the USB4 connection manager in Windows". docs.microsoft.com. 2021-09-03. Archived from the original on 2021-11-03. Retrieved 2021-11-03.
- ^ "February 29, 2024—KB5034848 (OS Builds 22621.3235 and 22631.3235) Preview - Microsoft Support". support.microsoft.com. Retrieved 2024-08-05.
- ^ Piltch, Avram (2021-04-20). "USB 4: Everything We Know So Far". Tom's Hardware. Archived from the original on 2021-06-30. Retrieved 2020-04-30.
- ^ Shilov, Anton. "Cypress Announces USB 3.2 & USB4-Ready Controllers: EZ-PD CCG6DF & CCG6SF". www.anandtech.com. Archived from the original on 2021-12-06. Retrieved 2020-04-28.
- ^ Cutress, Ian (2022-01-04). "AMD Announces Ryzen 6000 Mobile CPUs for Laptops: Zen3+ on 6nm with RDNA2 Graphics". Anandtech. Archived from the original on 2022-06-25. Retrieved 2022-07-26.
- ^ Klotz, Aaron (2022-06-28). "AMD Introduces USB 4 Support in Chipset Update for Ryzen 6000 Mobile (Updated)". Tom's Hardware.
- ^ Bonshor, Gavin (2022-05-23). "AMD Ryzen 7000 Announced: 16 Cores of Zen 4, Plus PCIe 5 and DDR5 for Socket AM5, Coming This Fall". Anandtech. Archived from the original on 2022-07-26. Retrieved 2022-07-26.
- ^ "AMD confirms Zen4 & Ryzen 7000 series lineup: Raphael in 2022, Dragon Range and Phoenix in 2023". VideoCardz.com. Retrieved 2022-11-29.
- ^ "Intel JHL8540 USB4 Controller Specifications".
- ^ "Intel JHL8440 USB4 Controller Specifications".
- ^ "Intel JHL9540 USB4 Controller Specifications".
- ^ "Intel JHL9440 USB4 Controller Specifications".
- ^ "Intel JHL9580 USB4 Controller Specifications".
- ^ "Barlow Ridge Leak".
- ^ "Intel JHL9480 USB4 Controller Specifications".
- ^ "Intel Tiger Lake CPU Specifications".
- ^ "Intel Alder Lake CPU Specifications".
- ^ "Intel Raptor Lake CPU Specifications".
- ^ "Intel Meteor Lake CPU Specifications".
- ^ "Intel Lunar Lake CPU Specifications".
- ^ "Intel Arrow Lake CPU Specifications".
- ^ "Via VL830 USB4 Controller Specifications".
- ^ "Via VL832 USB4 Controller Specifications".
- ^ "ASM2464PD USB4 Controller Specifications".
- ^ "ASM2464PDX USB4 Controller Specifications".
- ^ "ASM4242 USB4 Controller Specifications".
- ^ "RTS5490 Multi-Port USB4 Hub Router Controller".
- ^ "RealTek RTS5490 USB4 hub controller port analysis".
Specification References
[edit]- "USB Type-C® Cable and Connector Specification Release 2.3 | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
- "USB4® Specification v2.0 | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
- "USB4® Specification v2.0, Adopters Agreement | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
- "USB4® Specification v2.0, Connection Manager Guide | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
- "USB4® Specification v2.0 Inter-Domain Service | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
- "USB Power Delivery | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
- "USB 2.0 Specification | USB-IF". usb.org. Retrieved 2024-08-05.
- "USB 3.2 Revision 1.1 - June 2022 | USB-IF". usb.org. USB-IF. Retrieved 2024-08-05.
External links
[edit]Overview
Key Features
USB4 represents a significant advancement in connectivity standards by integrating the protocols of USB 3.2, Thunderbolt 3, and DisplayPort 1.4 into a unified protocol stack, enabling seamless transfer of data, video, and power over a single USB Type-C connection.[1] This integration, based on the Thunderbolt protocol contributed by Intel, allows for versatile applications such as high-speed data storage, external graphics processing, and multi-display setups, while maintaining compatibility with existing USB ecosystems.[4] A core feature is the bandwidth provisioning, with a minimum guaranteed rate of 20 Gbps to ensure reliable performance across devices, and optional support scaling up to 40 Gbps in Version 1.0 for bidirectional symmetric transfer.[1] Version 2.0 extends this further with up to 80 Gbps symmetric operation or an asymmetric mode reaching 120 Gbps in one direction and 40 Gbps in the other, optimizing for scenarios like high-bandwidth video output or data ingestion.[5] USB4 ensures backward compatibility with USB 2.0, USB 3.x, and Thunderbolt 3 devices, as well as the broader USB Type-C ecosystem, including USB Power Delivery (PD) capabilities up to 240 W for charging high-power devices like laptops.[1][3] The standard's dynamic resource allocation allows asymmetric bandwidth distribution to prioritize traffic types, such as dedicating more capacity to display streams over data transfers, enhancing efficiency in mixed-use environments.[4] For video applications, USB4 supports DisplayPort tunneling, enabling configurations like dual 4K displays at 60 Hz or a single 8K display at 60 Hz, depending on the implementation and cable quality.[1] Additionally, it briefly references PCIe tunneling for external GPU connectivity, though detailed mechanisms are defined elsewhere.[1]Technical Specifications
USB4 establishes performance tiers based on signaling generations to balance speed, compatibility, and cable requirements. Version 1.0 mandates a minimum bandwidth of 20 Gbps via Gen 2x2 operation, which utilizes two lanes at 10 Gbps each, while supporting a maximum of 40 Gbps through Gen 3x2 signaling over certified 40 Gbps cables.[1] Version 2.0 extends this to 80 Gbps symmetric bandwidth using PAM3 signaling over two lanes, doubling the aggregate throughput for demanding applications like high-resolution displays and storage; an optional asymmetric mode allocates 120 Gbps in one direction (primarily for video output) paired with 40 Gbps in the reverse, enhancing efficiency for unidirectional high-bandwidth scenarios.[1] The protocol relies on a packet-based architecture for flexible data handling across tunneled protocols, employing 128b/132b encoding in Gen 3 modes to minimize overhead to about 3%, compared to higher losses in prior schemes like 8b/10b. This encoding supports robust error detection and synchronization for concurrent protocol multiplexing, such as USB, PCIe, and DisplayPort. Packets vary in size up to 256 bytes payload, allowing dynamic allocation while maintaining link efficiency. Latency is optimized for real-time applications, with low round-trip times for USB tunneling to preserve legacy USB performance. PCIe tunneling introduces variable latency based on configuration, scaling with link width up to x4 Gen 3 (approximately 32 Gbps raw), where added overhead from encapsulation results in slightly higher delays than native PCIe but remains suitable for external GPUs and storage.[6][7] Power efficiency is a core design goal, with low idle consumption to support battery-powered hosts and reduce thermal impact.[1] This metric aligns with USB Power Delivery profiles up to 240 W for active operation, emphasizing low standby draw during inactivity.[1] Certification by the USB Implementers Forum (USB-IF) ensures interoperability and reliability through standardized testing, including eye diagram assessments for signal integrity at 40 Gbps. These tests verify transmitter output against masks defined in the specification (e.g., Table 3-6), measuring jitter, voltage levels, and eye opening to confirm robust performance over cables up to 0.8 m.[8] Additional compliance matrices cover protocol layers, power negotiation, and backward compatibility with USB 3.2 and Thunderbolt 3.History and Development
Origins and Standardization
The development of USB4 originated from initiatives by the USB Promoter Group, a consortium comprising leading technology companies including Intel, Microsoft, Apple, Hewlett-Packard, and Renesas Electronics, to create a unified connectivity standard that integrates USB, Thunderbolt, and DisplayPort functionalities over the USB Type-C connector. These efforts addressed growing bandwidth fragmentation across disparate interfaces by enabling a single-cable solution capable of handling high-speed data transfer up to 40 Gbps, support for 8K video output via DisplayPort tunneling, and power delivery up to 100 W through USB Power Delivery protocols. The motivation stemmed from the need to streamline device connectivity for advanced applications, such as external storage, displays, and peripherals, while maintaining backward compatibility with prior USB generations.[9][10] Intel played a pivotal role by contributing its Thunderbolt 3 protocol specification to the USB Promoter Group, which formed the architectural foundation for USB4 and facilitated broader industry adoption beyond Intel's proprietary ecosystem. This collaboration extended to AMD, which supported USB4 integration in its processor platforms, and display technology organizations like the Video Electronics Standards Association (VESA), ensuring seamless incorporation of DisplayPort Alternate Mode for enhanced video capabilities. An initial draft of the specification emerged in early 2019, building on the Thunderbolt 3's tunneling mechanisms to support multiple protocols dynamically over shared links.[11][4] The USB Implementers Forum (USB-IF) ratified the USB4 Version 1.0 specification on August 29, 2019, marking it as a significant evolution from USB 3.2 by doubling aggregate bandwidth for optimized performance. The formal publication followed on September 3, 2019, making the specification available for adopters and spurring ecosystem development. This standardization process involved over 50 companies through the USB-IF, emphasizing interoperability and certification to mitigate compatibility issues in the evolving USB Type-C landscape. The specification was later extended with Version 2.0 in October 2022, supporting up to 80 Gbps bandwidth.[12]USB4 Version 1.0
The USB4 Version 1.0 specification was released on August 29, 2019, with the full technical details becoming available to developers through the USB Implementers Forum (USB-IF) shortly thereafter.[13] This version marked a significant evolution in USB connectivity by basing its protocol on Thunderbolt 3, enabling higher bandwidth while maintaining backward compatibility with prior USB standards. The core specifications mandate support for a minimum data rate of 20 Gbps using two lanes of differential signaling, with optional extension to 40 Gbps for devices capable of bonding those lanes to achieve full bidirectional throughput. This design prioritized symmetric data transfer, addressing limitations in predecessors like USB 3.2 by capping maximum speeds at 40 Gbps without asymmetric modes, thus simplifying implementation for high-performance applications such as external storage and display tunneling.[14] The USB-IF launched its certification program for USB4 Version 1.0 in 2020 to ensure interoperability and compliance among devices.[15] The first certified products emerged in 2021, including Intel's JHL8540 Thunderbolt 4 controller, which integrated USB4 capabilities into add-in cards and motherboards for enhanced connectivity.[16] Initial focus emphasized seamless compatibility with Thunderbolt 3 ecosystems, allowing USB4 hosts to support Thunderbolt 3 peripherals at up to 40 Gbps without requiring new cables or adapters, thereby easing the transition for existing users. Market rollout began with early adoption in premium laptops by mid-2021, exemplified by models like the Dell XPS 13 (9310) and Lenovo ThinkPad X1 Carbon Gen 9, which incorporated USB4 ports powered by Intel's Tiger Lake processors. These devices demonstrated the specification's practical impact by enabling faster external GPU connections and multi-monitor setups, accelerating ecosystem growth despite initial hardware costs. Subsequent enhancements in USB4 Version 2.0 would build on this foundation by introducing higher speeds beyond 40 Gbps.[14]USB4 Version 2.0
USB4 Version 2.0 was officially released by the USB Implementers Forum (USB-IF) in October 2022, introducing significant enhancements to the USB4 standard with support for up to 80 Gbps symmetric data transfer rates and 120 Gbps asymmetric modes (80 Gbps upstream and 40 Gbps downstream). These updates build on the foundational 40 Gbps capabilities of Version 1.0 by incorporating a new physical layer architecture that enables higher performance over existing USB Type-C cables and connectors. The specification also maintains backward compatibility with prior USB4 ports, ensuring seamless integration with older devices while unlocking advanced features on compatible hardware.[17] Key advancements in Version 2.0 include the adoption of PAM3 (Pulse Amplitude Modulation with 3 levels) signaling, which operates at 25.6 GBaud to achieve the elevated throughput without requiring entirely new cabling infrastructure. This is complemented by improved PCIe tunneling capabilities, supporting up to PCIe Gen 4 x4 (64 Gbps), allowing for more efficient external device connectivity such as GPUs and storage arrays. Additionally, power delivery has been extended to support up to 240 W via USB Power Delivery 3.1 with Extended Power Range (EPR), enabling charging of high-power devices like laptops and peripherals directly through the connection. These features collectively enhance overall system efficiency and versatility.[18][19] The first controllers supporting USB4 Version 2.0, such as Intel's JHL9480 for Thunderbolt 5 integration, received certification in 2024, paving the way for commercial products. Initial devices incorporating these capabilities began launching in 2025, including docking stations and laptops from manufacturers like ASUS and HP, which leverage the standard for expanded connectivity options.[20][21] These improvements provide better support for demanding applications, such as AI workloads, through increased PCIe bandwidth that facilitates faster data transfer to external accelerators, and reduced latency for high-speed external storage solutions. As of 2025, market analyses predict widespread adoption of USB4 Version 2.0 in gaming PCs and professional workstations, driven by its integration into Thunderbolt 5-certified devices that offer enhanced performance for graphics-intensive tasks and data-heavy computing. This shift is expected to accelerate with a projected compound annual growth rate (CAGR) of 19.3% for related high-speed connectivity solutions through 2031, as vendors prioritize compatibility with emerging AI and multimedia ecosystems.[22][23]Architecture and Protocols
Core Principles
USB4 employs a packet-switched fabric architecture, leveraging the USB4 Router as the central component for managing data flow. The USB4 Router serves as the foundational building block in any USB4 implementation, facilitating dynamic path allocation across hosts, devices, and protocol tunnels. This router core handles packet routing within the fabric, enabling efficient multiplexing of multiple data streams over a shared high-speed link. By design, the architecture supports connection-oriented tunneling for protocols such as USB 3.x and PCIe, allowing seamless integration without requiring software modifications for basic operations.[24][25] Ports in USB4 systems are role-based to maintain clear host-device hierarchies while accommodating flexibility. The Downstream Facing Port (DFP) is designated for host roles, sourcing power and initiating connections, whereas the Upstream Facing Port (UFP) is used by devices to receive power and connect upstream. Dual-role ports (DRP) support switching between DFP and UFP roles based on negotiation via USB Power Delivery (PD), enabling versatile configurations such as host-to-host tunneling or device-to-device links. This role assignment ensures topological stability, with the Connection Manager (CM) detecting and preventing invalid connections like DFP-to-DFP loops.[24] Bandwidth arbitration in USB4 utilizes a credit-based flow control mechanism to optimize resource sharing across the link. The CM oversees path setup, teardown, and allocation, dynamically allocating bandwidth to active paths while employing lazy allocation for idle paths to maximize efficiency. Up to 90% of the total link bandwidth—such as 18 Gbps on a 20 Gbps link or 36 Gbps on a 40 Gbps link—can be reserved for tunneled protocols, with the system prioritizing isochronous traffic such as USB 3.x within allocated bandwidth. USB4 Version 1.0 supports a minimum link speed of 20 Gbps. This system prevents oversubscription and supports dynamic adjustments based on real-time demands.[24][25] Security in USB4 incorporates built-in authentication mechanisms akin to those in Thunderbolt, particularly for protecting against direct memory access (DMA) attacks via PCIe tunneling. The architecture supports kernel DMA protection on compatible systems, using DMA remapping (such as Intel VT-d on Intel platforms) to isolate device memory access and prevent unauthorized reads or writes to system memory. PCIe tunneling can be selectively disabled through BIOS settings or operating system controls, ensuring only authenticated devices gain elevated privileges. These features mitigate risks from external peripherals, with the CM enforcing secure path establishment.[25] The logical topology of USB4 forms a tree structure rooted at the host router, with support for daisy-chaining up to seven devices through a maximum of six downstream routers. This configuration allows aggregated bandwidth management across the chain, where the CM constructs a spanning tree to synchronize timing via the Time Management Unit (TMU) and allocate resources holistically. Each link in the chain operates at up to 40 Gbps bidirectionally, with the overall domain ensuring end-to-end flow control and preventing bandwidth bottlenecks through credit grants and hop-based credits.[24][26]Tunneling Mechanisms
USB4 employs tunneling mechanisms to encapsulate and transport protocols such as USB 3.x, DisplayPort, and PCIe over its high-speed serial link, enabling simultaneous operation of multiple data streams within a single physical connection. This encapsulation occurs at the USB4 transport layer, where packets from native protocols are wrapped in USB4 headers for routing across the fabric, allowing dynamic multiplexing without dedicated lanes for each protocol. The design ensures backward compatibility and native performance for tunneled devices, with the USB4 router managing path selection and bandwidth distribution to prioritize active sessions.[25][27] For USB 3.x tunneling, USB4 provides native support for USB 3.2 Gen 2 (10 Gbps) and Gen 2x2 (20 Gbps) operation through dedicated adapters that map Enhanced SuperSpeed packets directly onto the USB4 transport layer. This eliminates physical layer overheads like scrambling and SKIP ordered sets from the original USB 3.x signaling, improving efficiency by reducing unnecessary protocol elements during transit. The tunneling supports both single-lane and dual-lane configurations, allowing USB 3.x devices to operate as if connected natively, with hot-plug detection handled via USB Type-C mechanisms. In USB4 Version 2.0, this extends to higher effective rates leveraging the 80 Gbps link, though capped by USB 3.x protocol limits.[28][29][30] DisplayPort tunneling in USB4 supports up to 32.4 Gbps for DisplayPort 1.4 (High Bit Rate 3 mode) in Version 1.0, enabling high-resolution video output such as 8K at 60 Hz or 4K at 120 Hz. Version 2.0 extends this to DisplayPort 2.0 capabilities at up to 80 Gbps, utilizing the full link bandwidth for ultra-high-definition displays. The mechanism includes multi-stream transport (MST), which allows a single USB4 port to drive multiple displays by branching video streams within the tunnel. Hot-plug events are signaled through auxiliary channel packets, ensuring seamless display detection and configuration. Buffering at adapters compensates for timing variations between USB4 and DisplayPort clocks.[31][10][25] PCIe tunneling facilitates external expansion devices, supporting up to PCIe Gen 3 x4 (approximately 32 Gbps bidirectional) in USB4 Version 1.0, suitable for applications like external GPUs and NVMe storage. Version 2.0 upgrades this to PCIe Gen 4 x4 (approximately 64 Gbps bidirectional), requiring all components in the tunnel path to comply with the enhanced specification. The tunneling maps PCIe transaction layer packets (TLPs) and data link layer packets (DLLPs) into USB4 frames, with single-hop topology necessitating PCIe switches in routers for multi-device support. Hot-plug functionality is preserved through dedicated control packets, enabling dynamic attachment of PCIe endpoints without system reboot.[32][30][27] Bandwidth sharing among tunnels is managed dynamically by the USB4 connection manager, which allocates portions of the total link bandwidth—20 Gbps, 40 Gbps, or 80 Gbps depending on the version and cable—to active protocols based on demand and priority. For instance, on a 40 Gbps link, 20 Gbps might be assigned to a DisplayPort tunnel for video while the remaining 20 Gbps supports USB 3.x data transfer. The allocation formula reserves approximately 10% of the link bandwidth for management and overhead, with available bandwidth calculated as roughly 0.9 times the total USB4 link rate minus committed resources for other tunnels, using weighted round-robin (WRR) scheduling for fairness. This ensures low-latency performance across mixed workloads.[25][33] Encapsulation in USB4 tunneling introduces overhead from added headers, such as packet headers, header error correction (HEC), and cyclic redundancy checks (CRC), typically amounting to 5-10% in scenarios with mixed traffic due to the combined effects of USB4 framing and native protocol remnants. Idle symbols and certain control elements from the original protocols are not tunneled, further optimizing efficiency, while forward error correction (FEC) parity for DisplayPort is omitted to minimize latency. In pure-protocol tunnels, overhead is lower, approaching the ~2.5% from 128b/130b encoding alone.[27][34][35]Protocol Adapters
Protocol adapters in USB4 serve as the interface components that convert and manage the tunneling of various input/output protocols over the USB4 fabric, enabling seamless integration of legacy and high-speed protocols such as USB 3.x, PCI Express (PCIe), and DisplayPort (DP).[24] These adapters operate within the protocol adapter layer, mapping specific I/O protocols to USB4 packets for encapsulation and decapsulation, allowing up to 64 adapters per router to support dynamic resource allocation across the link.[24] By handling protocol-specific processing without altering the underlying USB4 transport, they ensure compatibility and efficiency in multi-protocol environments.[29] The USB3 I/O adapter facilitates backward compatibility by converting USB4 packets into USB 3.x SuperSpeed formats, encapsulating and decapsulating USB 3.2 protocol data while supporting configurations like Gen 2 single-lane (2x1) or dual-lane (2x2) modes.[24] This adapter bypasses USB4-specific physical layer elements such as scrambling and SKIP ordered sets, directly translating native USB 3.2 traffic to tunneled formats for legacy devices without requiring additional hardware intervention.[29] It ensures that USB 3.x devices connected via USB4 ports operate at their native speeds, up to 20 Gbps in compatible configurations.[24] The PCI I/O adapter manages PCIe transaction layer packets by encapsulating them into USB4 tunnels, incorporating PCIe-native error correction mechanisms such as acknowledgments and negative acknowledgments (ACK/NAK) for reliable data transfer, along with retry protocols to handle transmission errors.[24] This adapter interfaces with internal PCIe switches or root complexes, enabling applications like external storage and graphics processing units by maintaining end-to-end PCIe integrity over the USB4 link.[36] The DP I/O adapter handles DisplayPort protocol tunneling by packing and unpacking video streams, supporting single-stream transport (SST) or multi-stream transport (MST) across 1 to 4 lanes at rates from reduced bit rate (RBR) to high bit rate 3 (HBR3).[24] It manages the DP AUX channel for control signaling and synchronizes the main link using time management units (TMUs) to ensure low-latency video delivery without intermediate buffering.[36] During operation, input and output DP adapters coordinate link training progress via configuration packets to maintain synchronization. Adapter negotiation occurs during USB4 link training and initialization, where adapters declare their capabilities through USB4 entry packets and sideband channel communications, allowing the connection manager to configure paths based on detected protocols and bandwidth needs.[24] This process, part of the five-phase link initialization, involves lane adaptation state machines that negotiate Gen 2 (10 Gbps) or Gen 3 (20 Gbps) speeds before proceeding to protocol-specific setup.[37] In USB4 Version 2.0, protocol adapters receive enhancements to support higher-performance tunneling, including compatibility with DisplayPort 2.0 for ultra-high bit rate (UHBR) modes and elevated PCIe speeds leveraging the 80 Gbps physical layer, enabling more efficient use of the increased bandwidth for USB 3.2, DP, and PCIe traffic. These adapters also incorporate firmware updatability provisions, allowing post-deployment updates to optimize protocol handling and compatibility via USB4's configuration layer.Physical Layer and Signaling
Signaling Modes
USB4 employs multiple signaling modes to support varying bandwidth requirements and ensure compatibility with legacy USB standards. The primary signaling mode for high-speed operation in USB4 version 1.0 utilizes Non-Return-to-Zero (NRZ) signaling at a symbol rate of 20 GT/s per lane, enabling an aggregate data rate of 40 Gbps across two lanes.[18] USB4 version 1.0 also supports Pulse Amplitude Modulation with 3 levels (PAM3) at 22.5 GT/s per lane when operating in Thunderbolt 3 tunneling mode for compatibility. This provides higher spectral efficiency in that context while maintaining compatibility with existing USB Type-C cabling. For lower-speed fallback operations, USB4 supports USB 3.2 Gen 2x2 at 20 Gbps or Gen 2 at 10 Gbps, both using Non-Return-to-Zero (NRZ) signaling with binary levels.[12] These modes ensure backward compatibility with previous USB generations by negotiating the link speed during initialization. The link training process is managed by the Link Training and Status State Machine (LTSSM), an extension of the USB 3.x protocol, which handles mode detection, equalization, and synchronization.[38] In USB4 version 2.0, forward error correction (FEC) using Reed-Solomon coding is introduced to enhance reliability at higher speeds, correcting up to 12 symbol errors per block to achieve a bit error rate below 10^{-19}. The electrical characteristics include a transmitter (TX) differential output swing of 0.8 to 1.2 V, optimized for signal integrity over typical cable lengths.[39] Receivers (RX) incorporate adaptive equalization capable of up to 40 dB of loss compensation to mitigate channel impairments such as attenuation and crosstalk.[40] USB4 version 2.0 introduces enhancements with PAM3 signaling at 25.6 GT/s per lane, supporting 80 Gbps symmetric or 120 Gbps asymmetric operation (using three lanes for transmit and one for receive), along with improved adaptive equalization for longer reach active cables. These pin assignments for signaling are defined within the USB Type-C connector standard.[1]Pinout and Connectors
USB4 employs the USB Type-C connector, which consists of 24 pins arranged in two symmetric rows (A1–A12 and B1–B12) to enable reversible, orientation-independent connections without signal remapping. The high-speed differential pairs—TX1± (A2/A3), RX1± (B2/B3), TX2± (A11/A12), and RX2± (B10/B11)—are reused for USB4 signaling, supporting two lanes for data rates up to 40 Gbps in Version 1.0 and 80 Gbps in Version 2.0.[41] Additional pins include VBUS (A6, A9, B6, B9) for power delivery up to 240 W in Version 2.0, GND (A1, A12, B1, B12) for grounding, D+ and D- (A4/A5, B4/B5) for legacy USB 2.0 signaling, CC1 and CC2 (A7, B7) for cable orientation detection and configuration channel communication, and SBU1/SBU2 (A8, B8) for sideband use, including mapping to SBTX/SBRX in USB4 operation and fallback to DisplayPort Alternate Mode. The pinout ensures flipping the connector swaps the TX/RX pairs (e.g., TX1 becomes RX1), maintaining full functionality through protocol-level adaptation.| Pin | Row A Signal | Row B Signal |
|---|---|---|
| 1 | GND | GND |
| 2 | TX1+ | RX1+ |
| 3 | TX1- | RX1- |
| 4 | D+ | D+ |
| 5 | D- | D- |
| 6 | VBUS | VBUS |
| 7 | CC1 | CC2 |
| 8 | SBU1 | SBU2 |
| 9 | VBUS | VBUS |
| 10 | RX2- | TX2- |
| 11 | RX2+ | TX2+ |
| 12 | GND | GND |