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Silvermont
Intel Mobile Celeron N2830
General information
LaunchedFrom 2013
Common manufacturer
Architecture and classification
Technology node22 nm
Instructionsx86-16, IA-32, x86-64
Extensions
Physical specifications
Cores
  • 2–8
Products, models, variants
Brand names
History
PredecessorsBonnell
Saltwell
SuccessorsAirmont (die shrink),
Goldmont (new microarchitecture)

Silvermont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. Silvermont forms the basis for a total of four SoC families:[1]

  • Merrifield and Moorefield  – consumer SoCs intended for smartphones
  • Bay Trail – consumer SoCs aimed at tablets, hybrid devices, netbooks, nettops, and embedded/automotive systems
  • Avoton – SoCs for micro-servers and storage devices
  • Rangeley – SoCs targeting network and communication infrastructure.

Silvermont is the successor of the Bonnell, using a newer 22 nm process (previously introduced with Ivy Bridge) and a new microarchitecture, replacing Hyper Threading with out-of-order execution.[2]

Silvermont was announced to news media on May 6, 2013, at Intel's headquarters at Santa Clara, California.[3] Intel had repeatedly said the first Bay Trail devices would be available during the Holiday 2013 timeframe, while leaked slides showed that the release window for Bay Trail-T as August 28 – September 13, 2013.[4] Both Avoton and Rangeley were announced as being available in the second half of 2013. The first Merrifield devices were announced in 1H14.[5]

According to the Tick–tock model Airmont is the 14 nm die shrink of Silvermont, launched in early 2015 and first seen in the Atom x7-Z8700 as used in the Microsoft Surface 3.[6] Airmont microarchitecture includes the following SoC families:[7]

  • Braswell  – consumer SoCs aimed at PCs
  • Cherry Trail  – consumer SoCs aimed at tablets.

Silvermont based cores have also been used, modified, in the Knight's Landing iteration of Intel's Xeon Phi HPC chips.

Design

[edit]

Silvermont was the first Atom processor to feature an out-of-order architecture.[8]

Technology

[edit]
See also: Intel Graphics Technology

Errata

[edit]

Intel revealed in its Q4 2016 quarterly report that there were quality issues in the C2000 product family, which had an effect on the financial performance of the company's Data Center Group that quarter.[12] An erratum named AVR54 published by Intel; state there is a defect in the chip's LPC clock, and affected systems "may experience inability to boot or may cease operation".[13][14][15] A workaround is available requiring platform hardware changes. The SoC failures are thought to have led to failures in Cisco and Synology products,[16] though discussion of the C2000 as the root cause of failure has been reported to be under a non-disclosure agreement for many vendors.[17]

Intel released a new C0 stepping of the C2000 series in April 2017 which corrected the bug.[18]

In July 2017 Intel published that a similar quality issue affects also Atom E3800 series embedded processors. The erratum named VLI89 published by Intel state, similar to issue with Atom C2000, that there is a defect in the chip's LPC clock and affected systems "may experience inability to boot or may cease operation".[19] Issues extend also to USB bus and SD card circuitry and should happen "under certain conditions where activity is high for several years". In April 2018 Intel announced it is releasing a new D1 stepping to fix the issue.[20]

The LPC, USB and SD Card buses circuitry degradation issues also apply to other Bay Trail processors such as Intel Celeron J1900 and N2800/N2900 series;[21] also to Pentium N3500, J2850, J2900 series; and Celeron J1800 and J1750 series—as those are based on the same affected silicon.

Cisco stated failures of Atom C2000 processors can occur as early as 18 months of use with higher failure rates occurring after 36 months.[22]

Mitigations were found to limit impact on systems. Firmware update for the LPC bus called LPC_CLKRUN# reduces the utilization of the LPC interface what in turn decreases (but not eliminates) LPC bus degradation - some systems are however not compatible with this new firmware. USB should have a maximum of 10% active time and there is a 50TB transmit traffic life expectancy over the lifetime of the port. It is recommended not to use SD card as a boot device and to remove the card from the system when not in use.

Bay Trail issues on Linux

[edit]

It has been widely reported that Bay Trail CPUs (and possibly their derivatives including Airmont/Braswell/Cherry Trail) experience random freezes / lock-ups on various Linux kernels. Reference Linux bug report 109051 on Kernel.org Bugzilla, first reported Dec-2015. Workaround seems to be setting the Linux kernel flag intel_idle.max_cstate=1, which while eliminating the system freezes/lock-ups, results in increased CPU power/battery usage by preventing the CPU from entering higher power-saving C-states. Systems running Windows-OSes apparently do not experience these lockup/freeze issues. The issue had been addressed in the commit "drm/i915: Disable preemption and sleeping while using the punit sideband".

Bay Trail issues on FreeBSD

[edit]

A potential fix is to set hw.acpi.cpu.cx_lowest=C1 and dev.cpu.<n>.lowest via /etc/sysctl.conf.

Airmont issues

[edit]

14 nm Airmont architecture processors are also affected by the design flaws as noted in the Braswell Specification Update under CHP49 errata.[23] In addition to LPC and SD Card circuitry degradation issues those 14 nm designs also have issues with Real Time Clock (RTC) circuitry degradation, their USB buses are however not affected. Unspecified firmware changes are required to mitigate RTC circuitry degradation. Intel does not plan to release a new stepping for Braswell. Intel admitted the issue stating the impact on consumers depends on use condition.[24]

List of Silvermont processors

[edit]

Desktop processors (Bay Trail-D)

[edit]

List of desktop processors as follows:

Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU model TDP Turbo
(GHz) 		GPU freq.
(MHz) 		L2
cache
(MB) 		Release
date 		Price
(USD)
1-core Base Turbo
Value 4 (4) Pentium J2900 HD Graphics
(4 EU) 		10 W / 2.41 GHz 2.67 688 896 2 Q4 2013 $94
J2850 — 792 Q3 2013
Celeron J1900 10 W / 2.0 GHz 2.42 854 Q4 2013 $82
J1850 — 792 Q3 2013
2 (2) J1800 10 W / 2.41 GHz 2.58 1 Q4 2013 $72
J1750 — 750 Q3 2013

Server processors (Avoton)

[edit]

It has been found that a bug in the blueprint of the C2000 CPUs family may cause failure of its embedded Ethernet ports.[citation needed]

List of server processors as follows:[25]

Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU model TDP CPU
Turbo
(GHz) 		Graphics clock rate L2
cache
(MB) 		Release
date 		Price
(USD)
1-core Normal Turbo
Server 8 (8) Atom C2750 — 20 W / 2.4 GHz 2.6 — — 4 Q3 2013 $171
C2730 12 W / 1.7 GHz 2.0 $150
 4 (4) C2550 14 W / 2.4 GHz 2.6 2 $86
C2530 9 W / 1.7 GHz 2.0 $70
 2 (2) C2350 6 W / 1.7 GHz 1 $43

Communications processors (Rangeley)

[edit]

List of communications processors as follows:[26]

Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU model TDP CPU Turbo
(GHz) 		GPU freq. Intel
QuickAssist 		L2
cache
(MB) 		Release
date 		Price
(USD)
1-core Normal Turbo
Communications 8 (8) Atom C2758 — 20 W / 2.4 GHz — — — Yes 4 Q3 2013 $208
C2738 No
C2718 18 W / 2.0 GHz Yes $182
4 (4) C2558 15 W / 2.4 GHz 2 $104
C2538 No
C2518 13 W / 1.7 GHz Yes $91
C2508 9.5 W / 1.25 GHz Q2 2014 $98
2 (2) C2358 7 W / 1.7 GHz 2.0 1 Q3 2013 $60
C2338 No
C2308 6 W / 1.25 GHz — Yes Q2 2014

Embedded/automotive processors (Bay Trail-I)

[edit]

List of embedded processors as follows:[27]

Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU model TDP CPU Turbo GPU freq.
(MHz) 		L2
cache 		Release
date 		Price
(USD)
1-core Base Turbo
Embedded 4 (4) Atom E3845 HD Graphics
(4 EU) 		10 W / 1.91 GHz — 542 792 2 MB Q4 2013 $52
 2 (2) E3827 8 W / 1.75 GHz 1 MB $41
E3826 7 W / 1.46 GHz 533 677 $37
E3825 6 W / 1.33 GHz — $34
 1 (1) E3815 5 W / 1.46 GHz 400 512 KB $31
 2 (2) E3805 — 3 W / 1.33 GHz — 1 MB Q4 2014

Mobile processors (Bay Trail-M)

[edit]

List of mobile processors as follows:

Target
segment 		Cores
(threads) 		Processor
branding & model 		GPU model TDP CPU
turbo
(GHz) 		GPU freq.
(MHz) 		L2
cache
(MB) 		Release
date 		Price
(USD)
Base Turbo
Value  4 (4) Pentium N3540 Intel HD Graphics
(4 EU) 		7.5 W / 2.16 GHz 2.66 313 896 2 2014-07-20 $161
N3530 2.58 2014-02-23
N3520 7.5 W / 2.166 GHz 2.42 854 2013-11-03
N3510 7.5 W / 2.0 GHz — 750 2013-09-11
Celeron N2940 7.5 W / 1.83 GHz 2.25 854 Q3 2014 $107
N2930 2.16 2014-02-23
N2920 7.5 W / 1.86 GHz 2.0 844 2013-11-03
N2910 7.5 W / 1.6 GHz — 756 2013-09-11
 2 (2) N2840 7.5 W / 2.16 GHz 2.58 311 792 1 Q3 2014
N2830 2.41 313 750 2014-02-23
N2820 7.5 W / 2.13 GHz 2.39 756 2013-11-03
N2815 7.5 W / 1.86 GHz 2.13
N2810 7.5 W / 2.0 GHz — 2013-09-11
N2808 4.5 W / 1.58 GHz 2.25 311 792 Q3 2014
N2807 4.3 W / 1.58 GHz 2.16 313 750 2014-02-23
N2806 4.5 W / 1.6 GHz 2.0 756 2013-11-03
N2805 4.3 W / 1.46 GHz — 667 2013-09-11

Tablet processors (Bay Trail-T)

[edit]

List of tablet and hybrid processors as follows:

Target
segment 		Cores
(threads) 		Processor
branding & model 		SDP[28](W) CPU freq.
(GHz) 		L2
cache
(MB) 		GPU model GPU freq.
(MHz) 		Memory Max display resolution Socket Release
date 		Price
(USD)
Base Turbo Base Burst Type # channels Max speed Max bandwidth Max supported
Value 4 (4) Atom Z3795 2 1.66 2.39 2 HD Graphics (4 EU) 311 778 LPDDR3 2x64b 1067MT/s 17.1 GB/s 4 GB FCBGA1380 Q1 2014 $40.00
Z3785 2.2 1.49 2.41 313 833 1333MT/s 21.3 GB/s Q2 2014
Z3775 2 1.46 2.39 311 778 1067MT/s 17.1 GB/s Q1 2014 $35.00
Z3775D 2.2 1.49 2.41 792 DDR3L-RS 1x64b 1333MT/s 10.6 GB/s Q1 2014 $35.00
Z3770 2 1.46 2.39 667 LPDDR3 2x64b 1067MT/s 17.1 GB/s 2560×1600 11 September 2013 $37.00
Z3770D 2.2 1.5 2.41 313 688 DDR3L-RS 1x64b 1333MT/s 10.6 GB/s 2 GB 1920×1280
Z3740 2 1.33 1.86 311 667 LPDDR3 2x64b 1067MT/s 17.1 GB/s 4 GB 2560×1600 $32.00
Z3740D 2.2 1.83 313 688 DDR3L-RS 1x64b 1333MT/s 10.6 GB/s 2 GB 1920×1280
Z3735F 311 646 10.6 GB/s 1920×1200 FCBGA592 Q1 2014 $17.00
Z3735G 1x32b 5.3 GB/s 1 GB 1200×800
 2 (2) Z3680 2.0 1 667 LPDDR3 1x64b 1067MT/s 8.5 GB/s 1280×800 11 September 2013 —
Z3680D 688 DDR3L-RS 1x64b 1333MT/s 10.6 GB/s 2 GB 1920×1280

Smartphone processors (Merrifield)

[edit]

List of smartphone processors as follows:

Model sSpec
number 		Cores Clock rate GPU
frequency 		L2
cache 		I/O bus Memory Voltage TDP Socket Release date Part
number(s) 		Release
price (USD)
Atom Z3460
  • SR1WR (B1)
  • SR20G (B1)
  • SR20U (B1)
 2 1.6 GHz 400–457 MHz 1 MB 2 × LPDDR3-1066 March 2014
  • FG8065201850100
Atom Z3480
  • SR1WS (B1)
  • SR20F (B1)
 2 2.13 GHz 457–533 MHz 1 MB 2 × LPDDR3-1066 March 2014
  • FG8065201850200

Smartphone processors (Moorefield)

[edit]

List of smartphone processors as follows:

Model sSpec
number 		Cores Clock rate GPU
frequency 		L2
cache 		I/O bus Memory Voltage TDP Socket Release date Part
number(s) 		Release
price (USD)
Atom Z3530
  • SR1YR (B0)
 4 1.33 GHz 457 MHz 2 × 1 MB 2 × LPDDR3-1600 H2 2014
  • GA8066301896101
Atom Z3560
  • SR1WW (B0)
  • SR1WX (B0)
 4 1.83 GHz 457–533 MHz 2 × 1 MB 2 × LPDDR3-1600 H2 2014
  • GA8066301600200
Atom Z3570 4 2.00 GHz 457–640 MHz 2 × 1 MB 2 × LPDDR3-1600 Q4 2014
Atom Z3580
  • SR1WU (B0)
  • SR1WV (B0)
 4 2.33 GHz 457–533 MHz 2 × 1 MB 2 × LPDDR3-1600 H2 2014
  • GA8066301600100
Atom Z3590 4 2.50 GHz 457–640 MHz 2 × 1 MB 2 × LPDDR3-1600 H2 2015

List of Airmont processors

[edit]

Desktop processors (Braswell)

[edit]

List of desktop processors as follows:

Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU model TDP Turbo
(GHz) 		GPU freq.
(MHz) 		L2
cache
(MB) 		Release
date 		Price
(USD)
Brand name &
model number 		EU 1-core Base Turbo
Desktop 4 (4) Pentium J3710 HD Graphics 405 18 6.5 W /
1.6 GHz 		2.64 400 740 2 January
2016 		N/A
Celeron J3160 HD Graphics 400 12 6 W /
1.6 GHz 		2.24 320 700
2 (2) J3060 2.48 2
[note 1]

Mobile processors (Braswell)

[edit]

List of mobile processors as follows:

Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU Model TDP Turbo
(GHz) 		GPU freq.
(MHz) 		L2
cache
(MB) 		Release
date 		Price
(USD)
Brand name &
model number 		EU 1-core Base Turbo
Mobile 4 (4) Pentium N3710 HD Graphics 405 16 6W /
1.6 GHz 		2.56 400 700 2 Q1 2016 $161
N3700 HD Graphics (Braswell)[note 2] 2.4 Q1 2015
Celeron N3160 HD Graphics 400 12 2.24 320 640 Q1 2016 $107
N3150 HD Graphics (Braswell)
[note 2] 		2.08 Q1 2015
2 (2) N3060 HD Graphics 400 2.48 600 2[note 1] Q1 2016
N3050 HD Graphics (Braswell)
[note 2] 		2.16 Q1 2015
N3010 HD Graphics 400 4W / 1.04 GHz 2.24 Q1 2016
N3000 HD Graphics (Braswell)
[note 2] 		2.08 Q1 2015
  1. ^ a b Some initial reports stated that the processor has 1 MB L2 cache; see Anthony Shvets. "Notes below Specifications". CPU World.
  2. ^ a b c d Klaus Hinum (January 26, 2016). "Intel HD Graphics (Braswell)". Notebookcheck Publishing GmbH.

Tablet processors (Cherry Trail)

[edit]
Further information: List of Intel Atom microprocessors § "Cherry Trail-T" (14 nm)

List of smartphone and tablet processors as follows:

Target
segment 		Cores
(threads) 		Processor
branding and model 		SDP
(W) 		L2
cache
(MB) 		CPU freq.
(GHz) 		GPU Socket Release
date 		Price
(USD)
Brand name EU Freq. (MHz)
Base Turbo 1-core Base Turbo
Tablet 4 (4) Atom x7 Z8750 2 2 1.6 2.56 HD Graphics 16 200 600 FCBGA1380 Q1 2016 $37
Z8700 2.4 Q1 2015
Atom x5 Z8550 1.44 12 $27
Z8500 2.24
Z8350 1.92 500 FCBGA594 Q1 2016 $21
Z8330
Z8300 1.84 Q2 2015 $21

Other uses

[edit]

Silvermont based processor cores have been used in Knights Landing versions of Intel's Xeon Phi multiprocessor HPC chips, with changes for HPC including AVX-512 vector units.[29][30]

Intel also licensed Airmont CPU cores to Spreadtrum (now UNISOC) for use with two of its SoCs launched in 2017: SC9861G-IA[31] and SC9853l.[32]

See also

[edit]

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Silvermont

View on Grokipedia
from Grokipedia
Silvermont is a developed by Corporation for low-power processors in its Atom, , and product lines, primarily targeting systems-on-a-chip (SoCs) for mobile and embedded applications. Introduced in , it represents a significant advancement in Intel's Atom family, succeeding the Saltwell architecture and incorporating for improved single-threaded performance. Fabricated on Intel's 22 nm Tri-Gate process technology, Silvermont enables multi-core designs scalable up to eight cores, with enhanced features like Intel Burst Technology 2.0 to optimize efficiency across varying workloads. The delivers approximately three times the peak of its predecessor or equivalent at about five times lower power consumption, making it suitable for devices such as tablets, smartphones, microservers, network equipment, storage systems, entry-level laptops, and in-vehicle units. Silvermont's design emphasizes a balance between computational efficiency and energy savings, supporting 64-bit x86 instruction sets and integrating advanced graphics capabilities in certain implementations. It powered a range of products including the Bay Trail and Valleyview SoCs, which were deployed in and industrial applications starting in late 2013. Subsequent iterations, such as Airmont, built upon Silvermont's foundation to further refine and power metrics in later Atom generations.

Background

Overview

Silvermont is a low-power x86 developed by , introduced as the first in the Atom lineup to incorporate , targeting systems-on-chip (SoCs) for mobile, embedded, and low-power computing applications. It powers Atom, , and branded processors fabricated on a 22 nm Tri-Gate process node, marking a significant evolution from the in-order designs of previous generations. The architecture employs a with dual-core units, enabling scalable configurations up to eight cores across multi-module setups. Announced on May 6, 2013, Silvermont succeeded the Saltwell (part of the Bonnell/Saltwell lineage) and launched later that year in products like Bay Trail and Merrifield SoCs. Its primary goals were to enhance performance-per-watt efficiency by approximately 3x in peak performance or deliver equivalent performance at about 5x lower power consumption relative to prior Atom cores, addressing limitations in and energy use from predecessors like Saltwell. Basic specifications include support for 2 threads per dual-core module (one per core), clock speeds typically ranging from 1.3 to 2.4 GHz, and (TDP) ratings of 2 to 10 W. As part of Intel's broader strategy to reinvent the Atom brand for the post-PC era, Silvermont aimed to expand into competitive segments including tablets, smartphones, microservers, and automotive systems, challenging dominance in low-power markets. This was later succeeded by the 14 nm Airmont shrink in 2015.

Development history

Development of the Silvermont microarchitecture began around 2010-2011 as part of 's strategic response to intensifying competition from ARM-based processors in the mobile and low-power computing markets. recognized the need to overhaul its Atom lineup, which had struggled with power efficiency and performance in emerging segments like smartphones and tablets, prompting a roadmap revision to prioritize sub-10W designs. Internally code-named Silvermont, the architecture was first publicly revealed in Intel's 2012 product roadmap, emphasizing a ground-up redesign to deliver substantial improvements in instructions per cycle (IPC) while incorporating out-of-order execution to improve performance while controlling power consumption. The design targeted a 50% IPC uplift over the prior Saltwell microarchitecture, addressing the latter's limitations in single-threaded performance and efficiency, where Saltwell typically achieved around 0.6 IPC compared to Silvermont's goal of approximately 1.0 IPC. This focus, including the adoption of out-of-order execution optimized for low power, aimed to enable competitive SoCs for tablets and embedded systems. Key milestones included in late 2012, followed by first silicon validation in mid-2013, culminating in the launch of Silvermont-based products like the Bay Trail SoC platform in the fourth quarter of 2013. officially unveiled Silvermont on May 6, 2013, highlighting its integration into quad-core configurations for consumer devices and its projected 3x performance-per-watt gains over predecessors. Challenges during development centered on balancing die size reductions with enhanced branch prediction and wider execution units, all while fabricating in-house on 's 22 nm process to meet aggressive power envelopes under 3W for mobile applications. Following its debut, Silvermont evolved into the Airmont , a 14 nm shrink introduced in 2015 for broader adoption in tablets and 2-in-1 devices, which refined power management and graphics integration while retaining core design principles. This led to the architecture in 2016, marking a further iteration with enhanced vector processing and security features for IoT and entry-level computing.

Microarchitecture

Core design

The Silvermont features an engine for integer operations, marking a significant departure from the in-order designs of prior Atom generations like Saltwell, while maintaining in-order execution for floating-point and memory operations to balance performance and power efficiency in low-power SoCs. This design enables better single-threaded performance without excessive power draw, with cores organized in a modular cluster configuration where pairs of cores share key resources. Each cluster includes two physical cores that share a 1 MB L2 cache with 16-way set associativity, a common bus interface, and unified power domains, allowing for efficient scaling up to eight cores in multi-cluster SoCs while minimizing overhead from independent core operation. Silvermont cores fully support the , including SSE4.2 for 128-bit SIMD vector processing, but lack native AVX support in standard implementations to prioritize area and power constraints in mobile and embedded applications; optional () is available in select configurations, such as server-oriented variants, enabling up to four threads per dual-core cluster by doubling logical processors per core. Integer execution per core includes two arithmetic logic units (ALUs) for basic operations like add and shift, paired with dedicated address generation units (AGUs) in a separate execution cluster for load/store address calculations; the is a 128-bit wide optimized for SSE instructions, capable of handling both scalar and packed floating-point data types with latencies of 3 cycles for add and 3-5 cycles for multiply operations. The front-end employs a 2-wide decoder that can process up to two x86 instructions per , emitting up to two micro-operations (uops), and incorporates macro-op fusion to combine common instruction pairs—such as compare-and-branch—into a single uop for reduced decode bandwidth and improved on control-heavy code. Branch prediction is handled by a dual-scheme mechanism: a primary fetch-directed predictor for early direction and target speculation, augmented by a secondary decode-stage predictor that can override the initial guess for higher accuracy, representing a substantial upgrade over Saltwell's simpler predictor with lower misprediction penalties (around 10-12 cycles) and better handling of indirect branches through global history tracking. The overall pipeline spans 14 stages for simple operations, integrating these elements into a cohesive flow that emphasizes responsiveness in power-sensitive environments.

Pipeline and execution units

Silvermont employs a 14-stage out-of-order to enhance instruction throughput while maintaining low power consumption. The front-end, comprising fetch and decode stages, spans approximately four stages overall, enabling efficient handling of instruction streams. The execution phase includes six stages that integrate integer and floating-point processing, followed by a four-stage back-end for retirement and writeback. This structure reduces latency compared to prior Atom designs by decoupling memory access from the core integer . The fetch unit processes 16 bytes of , supported by a branch target buffer and predictor to minimize disruptions. A loop stream detector identifies small loops and buffers up to 32 decoded instructions in an instruction queue, allowing the front-end to be clock-gated for power savings during repetitive execution. Decode follows with a width of two macroinstructions per cycle, fusing common operations where possible to optimize queue entry. Dispatch occurs at two instructions per cycle into the out-of-order engine, accompanied by a register rename stage that allocates from 32 physical registers each for and floating-point/SSE operations. Execution throughput reaches two operations per cycle across two arithmetic logic units, one 128-bit floating-point vector operation per cycle, and one load plus one store per core, leveraging distributed reservation stations for scheduling. The back-end retires up to two instructions per cycle in program order via a 32-entry reorder buffer. Branch misprediction incurs a penalty of 10 cycles, three cycles lower than in Saltwell, due to streamlined recovery mechanisms. Overall, these enhancements yield about 50% higher (IPC) than Saltwell, driven by wider decoding, out-of-order capabilities, and superior branch prediction, with typical workloads achieving 0.6 to 0.8 IPC.

Cache and memory subsystem

Silvermont employs a two-level on-chip designed for low-power efficiency, with no dedicated L3 cache; instead, it relies directly on for higher-level caching needs. Each core features a private L1 instruction cache of 32 KB, organized as 8-way set associative with 64-byte cache lines, alongside a 24 KB L1 cache that is 6-way set associative using the same line size. These L1 caches are non-inclusive, allowing for optimized power and area usage without requiring the L2 to duplicate all L1 contents. The load/store units in the execution interface directly with these caches, achieving a typical L1 hit latency of 3 cycles to support timely access. The L2 cache is unified and shared within a dual-core cluster, providing 1 MB per pair (totaling 2 MB in quad-core configurations), implemented as 16-way set associative with 64-byte lines, inclusive of the L1 instruction cache but non-inclusive and non-exclusive of the L1 cache, to balance coherence management and efficiency. This design balances capacity and latency, with load-to-use times around 14-17 cycles, while delivering up to 32 bytes per cycle bandwidth shared between the cores in the cluster. The absence of an L3 cache underscores Silvermont's focus on embedded and mobile applications, where system serves as the next level in the . Translation lookaside buffers (TLBs) in Silvermont support efficient virtual-to-physical address translation, with a 48-entry fully associative L1 instruction TLB and TLB, covering 4 KB pages. A unified L2 TLB backs these with 512 entries, also 4-way set associative, to handle misses and larger page sizes including 2 MB and 4 MB. Hardware enhance memory access patterns: the implements stride detection for regular accesses and adjacent-line prefetching to anticipate sequential loads, while the instruction uses a 128-entry buffer to fetch ahead in code streams. The integrated memory controller supports dual-channel DDR3L-1600 memory, delivering up to 25.6 GB/s aggregate bandwidth, with mobile variants also accommodating LPDDR3 for lower power consumption. It operates within a 64-bit , enabling access to large memory configurations suitable for embedded systems. This subsystem prioritizes bandwidth efficiency over raw capacity, aligning with Silvermont's power-constrained environments.

Key technologies

Manufacturing process

Silvermont processors are fabricated using Intel's technology, which incorporates 3-D tri-gate s—Intel's implementation of FinFETs—to achieve superior gate control and significantly reduced leakage current compared to planar s. This structure enables up to 37% higher performance at low voltages or 50% lower power consumption at equivalent performance levels relative to the prior 32 nm planar process used in the Saltwell microarchitecture. The 22 nm node delivers approximately double the density of the 32 nm process, facilitating more compact system-on-chip (SoC) designs suitable for mobile and embedded applications. The manufacturing supports dynamic frequency and voltage scaling, with core voltages ranging from 0.8 V to 1.1 V to balance performance and power efficiency across varying workloads. For the Bay Trail implementation, the dual-core die contains approximately 1.9 billion transistors and measures about 102 mm², reflecting the density advantages of the FinFET technology. High-volume production of Silvermont-based SoCs commenced in the third quarter of 2013, primarily at Intel's fabrication facilities in the United States ( and ) and , ensuring scalable output for platforms like Bay Trail and Avoton. These sites benefited from process optimizations that improved yields for the complex tri-gate structures, enabling TDP ranges as low as 2 W for ultra-low-power devices.

Integrated graphics and I/O

The integrated graphics in Silvermont-based systems vary by platform to suit different form factors and power envelopes. In consumer and embedded implementations such as Bay Trail, the SoC incorporates HD Graphics (Generation 7), derived from the Ivy Bridge architecture, featuring 4 execution units with base clocks around 313 MHz and boosts up to 896 MHz depending on thermal and power conditions. This GPU supports 11 feature level 11_0, 4.0, and 1.2, enabling hardware-accelerated video decode for formats like H.264 and basic 3D rendering for embedded applications. Mobile-oriented Merrifield platforms, however, utilize a licensed PowerVR G6400 GPU with 4 shader cores operating at 457 MHz base and up to 533 MHz boost, tailored for workloads with support for 3.0 and efficient for battery life. Server variants like Avoton and Rangeley exclude integrated entirely, focusing instead on dense I/O for networked environments without display requirements. The graphics bandwidth in these SoCs relies on the integrated DDR3L/LPDDR3 , which provides up to 12.8 GB/s in dual-channel configurations for Bay Trail. Display capabilities in Silvermont SoCs with graphics integration support up to two independent outputs, including HDMI 1.4a (up to 1920x1080 at 60 Hz), DisplayPort 1.2 (up to 2560x1600 at 60 Hz), and LVDS/eDP interfaces for panel integration at similar resolutions. These features facilitate multi-monitor setups in tablets and thin clients, with hardware support for overlay planes and color space conversions. The I/O complement emphasizes connectivity for low-power embedded systems, including PCIe 2.0 with up to 4 lanes (x1 or x4 configurations) for peripherals and storage expansion. USB support comprises one USB 3.0 port (5 Gb/s) and up to five USB 2.0 ports (480 Mb/s), alongside two SATA 3.0 (6 Gb/s) ports for HDD/SSD attachment and an SD 3.0 card controller in mobile variants for removable media. Networking integration appears in server models like Avoton, which includes up to four 10/100/1000 Ethernet MACs with IEEE 1588 precision timing, while mobile platforms offload Wi-Fi (802.11ac) and Bluetooth 4.0 via PCIe or USB interfaces to external modules.

Power management features

Silvermont incorporates Enhanced Intel SpeedStep Technology (EIST) for dynamic frequency and voltage scaling, allowing the processor to adjust operating points based on workload demands to balance performance and power efficiency. Additionally, Intel Turbo Boost Technology enables short bursts of higher performance, up to 2.4 GHz in select implementations, when thermal and power headroom is available. The supports C-states ranging from C0 (active state) to C6 (), where the C6 state reduces core voltage to near zero volts, minimizing leakage and enabling low-power idle modes. Per-cluster permits independent shutdown of dual-core clusters sharing a 1 MB L2 cache, reducing static power when inactive cores or entire clusters are not needed. Fine-grained is applied at various stages and functional units to eliminate unnecessary switching activity, thereby lowering dynamic power dissipation. The features separate voltage and domains for the CPU cores, integrated , and I/O subsystems, with adaptive voltage scaling (AVS) compensating for variations to optimize margins and efficiency. Thermal power design is configurable across implementations, with thermal design power (TDP) ratings as low as 2.2 for mobile tablet platforms and up to 10 for embedded desktop variants; idle power consumption approaches 0.5 per core in optimized systems. The 22 nm tri-gate manufacturing process contributes to these efficiencies by reducing leakage currents compared to prior planar transistors.

Implementations

Bay Trail platforms

The Bay Trail family of system-on-chips (SoCs), introduced in the fourth quarter of , marked Intel's initial implementation of the Silvermont for and embedded applications. These SoCs targeted low-power devices such as netbooks, all-in-one PCs, and automotive systems, offering improved and over prior Atom generations. Configurations support up to four cores organized as two dual-core clusters, with each cluster sharing a 1 MB L2 cache to optimize power and area in multi-core setups. Bay Trail-D variants focus on desktop and entry-level computing, branded under the and lines in the J and N series for fanless, compact systems. The J1900, for example, provides four cores and four threads at a base frequency of 2.0 GHz (burst up to 2.42 GHz) with a 10 W TDP, and is frequently deployed in small-form-factor devices like Intel's (NUC) kits. The Bay Trail-M series extends similar capabilities to mobile platforms but with reduced (TDP) levels of 2.5–7.5 W for better battery life in portable devices. Representing this lineup, the N2815 offers two cores and two threads, operating at a 1.86 GHz base (burst to 2.13 GHz), and suits ultrathin laptops and netbooks. Optimized for tablets, Bay Trail-T emphasizes ultra-low power consumption at 2–4 W to enable all-day battery life in slim designs. The Atom Z3735F exemplifies this with four cores and four threads, a 1.33 GHz base frequency (burst to 1.83 GHz), and integrated support for tablets. Bay Trail-I delivers hardened options for embedded and automotive environments, supporting extended temperature ranges for industrial and in-vehicle applications. The Atom E3825, a dual-core model at 1.33 GHz with a 6 W TDP and two threads, powers rugged systems like in-vehicle (IVI) units. In terms of performance, Bay Trail SoCs achieve roughly twice the multi-threaded throughput of Saltwell-based predecessors while delivering up to three times the graphics performance through an Ivy Bridge-derived GPU.

Avoton and Rangeley

Avoton, launched in the second half of , comprises Intel's server-grade system-on-chips (SoCs) based on the , optimized for microserver and storage deployments. These processors emphasize energy efficiency and integration, supporting up to 8 cores configured in clustered modules with and frequencies reaching 2.4 GHz. Representative models include the C2538, a quad-core/quad-thread configuration at 2.4 GHz with a 15 W (TDP), and the C2750, an octa-core/octa-thread variant operating at base frequencies of 2.40 GHz with turbo up to 2.60 GHz and a 20 W TDP. The series features the Avoton S and D variants, where S models target single-SoC setups and D models enable dual-SoC configurations for enhanced scalability in compact form factors. Rangeley, a communications-oriented released in , extends the C2000 family to applications such as gateways, routers, and appliances. It shares the Silvermont but includes optimizations for network processing, exemplified by the C2550 model with 4 cores/4 threads at 2.4 GHz and a 12 W TDP. Rangeley prioritizes single-SoC implementations tailored for universal (uCPE), facilitating virtualized network functions at the edge. Both Avoton and Rangeley incorporate shared enterprise features, including support for up to 8 cores across quad-core clusters, an integrated 2.5 GbE media access controller (MAC) for high-speed networking, and Intelligent Platform Management Interface (IPMI) for out-of-band system management and reliability monitoring. These SoCs also provide enhanced error-correcting code (ECC) support for DDR3 memory, enabling up to 64 GB at 1600 MT/s to ensure data integrity in demanding environments. Their low-power profile and integrated I/O, including PCIe Gen2 lanes and SATA ports, enable dense deployments in cloud edge computing and network-attached storage (NAS) systems, delivering significant performance-per-watt gains over prior Atom generations for scalable infrastructure.

Merrifield and Moorefield

Merrifield, introduced in 2013 as part of Intel's Atom Z3000 series, represented the company's push into processors with a focus on low-power x86 architecture for Android devices. The platform featured dual-core configurations, exemplified by the Atom Z3460 operating at a base frequency of 1.6 GHz with burst capabilities up to 2.13 GHz, all within a power envelope of approximately 3W to optimize battery life in mobile handsets. A key innovation was Intel's first integrated LTE modem, the XMM 7160, supporting multimode // connectivity with up to 15 LTE bands and download speeds of 150 Mbps, enabling seamless global roaming without relying on external chips. This integration marked a shift toward fully unified SoCs for , reducing size and power draw compared to prior Clover Trail+ designs. Moorefield served as a 2014 refresh under the Atom Z3700 series, expanding to quad-core setups for mid-range smartphones while maintaining the 22 nm Silvermont core and a similar 3W target to balance and . The flagship Atom Z3590 delivered base clocks from 1.66 GHz to 2.0 GHz, with bursts reaching 2.39 GHz, paired with an upgraded GPU in the form of PowerVR Series 6 G6430, which offered improved rendering over the prior generation's PowerVR SGX544MP2 implementation. Early Merrifield variants utilized the PowerVR SGX544MP2 GPU clocked at up to 533 MHz, and Moorefield continued with PowerVR for . Merrifield supported dual-channel (2x32-bit) LPDDR3-1066 up to 4 GB; Moorefield supported dual-channel (2x32-bit) LPDDR3-1600 up to 4 GB to prioritize cost and power savings in slim phone designs. These SoCs emphasized mobile adaptations like MIPI CSI for camera interfaces up to 20 MP and MIPI DSI for displays up to , alongside techniques such as dynamic voltage scaling and S0ix low-power states to extend battery life within the constrained 3W envelope. Intel partnered with and under the "Intel Inside" initiative to develop reference phones, including devices like the 5 and K900, aiming to challenge -based competitors in the Android ecosystem. However, adoption remained limited due to the entrenched dominance of architectures in power-sensitive mobile markets, resulting in fewer than a dozen commercial models by 2015. The Merrifield lineup included the Z3460 and Z3480, both dual-core at 1.6 GHz base with minor variations in burst speeds and I/O tuning. Moorefield models comprised the Z3560 (1.8 GHz quad-core base), Z3580 (2.0 GHz quad-core base), and Z3590 (2.0 GHz quad-core base), offering progressive performance tiers for handsets.

Airmont derivative

Architectural modifications

Airmont is a 14 nm die-shrink of the Silvermont , transitioning from Intel's 22 nm Tri-Gate process to the more efficient 14 nm Tri-Gate process while retaining the fundamental out-of-order dual-core design. This process optimization yielded a substantial reduction in die size, with the dual-core module approximately 64% smaller than Silvermont's equivalent, enabling higher density and improved power efficiency without a major redesign. The was released in – to prolong the viability of the Silvermont family in low-power applications ahead of the subsequent redesign. The pipeline structure remains consistent with Silvermont's 14-stage flow as a baseline, incorporating targeted enhancements for modest performance gains. Notable tweaks include a larger reorder buffer (48 entries versus 32 in Silvermont), deeper reservation stations and store buffers, support for more outstanding load misses, and doubled data TLB size, collectively delivering a 5–10% instructions-per-clock (IPC) uplift primarily through refined decoder efficiency and better handling of instruction streams. accuracy was bolstered by doubling the sizes of arrays, which also enlarged the branch target buffer (BTB) to 20,000 entries from Silvermont's smaller capacity, reducing the misprediction penalty to 13 cycles compared to 15 cycles in the prior design. Cache hierarchy sizes stayed unchanged at 24 KB L1 instruction cache, 16 KB L1 data cache per core, and 512 KB L2 per core, but access latencies are consistent with Silvermont, with L1 data cache hits achievable in 3 cycles. saw refinements in gating mechanisms, facilitating operation at sub-2 W (TDP) levels suitable for ultra-low-power devices, further leveraging the 14 nm for density gains estimated at around 1.3× over Silvermont in effective logic utilization. The resulting dual-core die area measured approximately 37 mm², underscoring the shrink's focus on compactness.

Braswell and Cherry Trail platforms

The Braswell platform, launched in 2015, consisted of low-power system-on-chips (SoCs) designed for entry-level desktop and , primarily under the N3000 series branding. These processors featured dual- or quad-core configurations based on the Airmont , with base clock speeds ranging from 1.04 GHz to 1.60 GHz and burst speeds up to 2.24 GHz, all while maintaining a 6 W (TDP) envelope. They integrated 2 MB of L2 cache and supported dual-channel DDR3L-1600 or LPDDR3-1600 , enabling efficient operation in compact form factors. Braswell SoCs powered budget-oriented devices such as Chromebooks and convertible 2-in-1 laptops, where their balanced CPU and graphics capabilities suited web browsing, light productivity, and media consumption tasks. The integrated HD Graphics, derived from the Gen8 architecture, provided up to 12 execution units (EUs) clocked at 320–640 MHz, supporting hardware-accelerated video decode for 4K content and multiple display outputs via eDP, DP, or . Additional platform features included ports for faster data transfer and compatibility with 802.11ac modules for improved wireless connectivity, all optimized for ecosystems.
ModelCores/ThreadsBase FrequencyBurst FrequencyCacheTDP
N30002/21.04 GHz2.08 GHz2 MB L26 W
N30502/21.60 GHz2.16 GHz2 MB L26 W
N31604/41.60 GHz2.24 GHz2 MB L26 W
The Cherry Trail platform, also introduced in 2015, targeted tablet and ultra-mobile devices with the Atom x5-Z series SoCs, emphasizing extreme power efficiency for always-connected scenarios. These quad-core processors, such as the x5-Z8300, operated at a 1.44 GHz base clock with bursts up to 1.84 GHz and a scenario design power (SDP) of 2 W, integrating 2 MB of L2 cache alongside the same DDR3L/LPDDR3-1600 memory support as Braswell. The Gen8-based Intel HD Graphics scaled to 12–16 EUs (e.g., 16 EUs in the x5-Z8500 at up to 500 MHz), delivering enhanced media rendering and basic gaming capabilities compared to prior generations. Like Braswell, Cherry Trail incorporated and 802.11ac readiness, with specific tuning for touch and sensor integrations. Cherry Trail found adoption in slim tablets like the Microsoft Surface 3, where its low SDP enabled fanless designs for portability and extended battery life in and consumer markets. Overall, both platforms benefited from the Airmont core's architectural improvements, yielding roughly a 20% performance uplift in CPU tasks over Bay Trail equivalents while prioritizing efficiency.
ModelCores/ThreadsBase FrequencyBurst FrequencyCacheSDP
Atom x5-Z83004/41.44 GHz1.84 GHz2 MB L22 W
Atom x5-Z83504/41.44 GHz1.92 GHz2 MB L22 W
Atom x5-Z85004/41.44 GHz2.24 GHz2 MB L22 W

Known issues

Bay Trail errata

Bay Trail implementations encountered several notable software and hardware issues, primarily related to and peripheral controllers, which impacted compatibility with non-proprietary operating systems. Early versions of the Linux kernel in the 3.x series experienced kernel panics during power state transitions, particularly when attempting to enter the C6 idle state, due to incomplete ACPI handling tailored to the Silvermont microarchitecture's low-power features. These panics often resulted in system freezes or crashes, especially under idle conditions or during suspend-resume cycles. Support was improved starting with kernel 3.14 through targeted ACPI patches that enabled better recognition and management of Bay Trail's C-states and P-states, reducing the frequency of such failures. Additionally, graphics driver hangs were reported in Mesa implementations using the i915 DRM driver, leading to random X11 session freezes on Bay Trail hardware, often exacerbated by interactions between the kernel's power management and the integrated Intel HD Graphics. A common workaround involved booting with the kernel parameter intel_idle.max_cstate=1 to limit deeper idle states and prevent crashes. FreeBSD faced analogous power management challenges on Bay Trail platforms, including difficulties with C-state transitions that mirrored Linux issues, alongside USB 3.0 controller resets that could cause device detachments or system instability during high-load scenarios. These USB resets stemmed from xHCI host controller behavior, where resets occasionally failed to complete properly, triggering corrected errors or hangs. Resolutions were incorporated in FreeBSD 10.1 via driver enhancements and ACPI refinements, stabilizing power handling and USB operations for affected systems. On the hardware side, the Intel Atom E3800 series (the automotive-oriented Bay Trail variant) included documented errata affecting reliability. For instance, erratum VLI91 described scenarios where an xHCI host controller reset could lead to a system hang, as the controller might not respond, asserting CATERR# and requiring mitigation through a 1 ms post-reset delay in firmware. Similarly, erratum VLI63 noted that reset sequences might not complete under certain conditions during G3 (mechanical off) to S0 transitions, potentially hanging the SoC and necessitating a full power cycle; no silicon fix was available, but BIOS workarounds were recommended. Thermal throttling exhibited inconsistencies in automotive deployments, where environmental stressors could trigger uneven frequency scaling due to interactions with these power-related errata, though no dedicated erratum addressed this directly. These errata collectively delayed adoption of Bay Trail in Linux-based embedded applications, as developers relied on workarounds that increased power consumption or limited functionality, while Windows environments saw minimal disruption thanks to 's optimized drivers and . issued updates in 2014, such as revisions targeting idle state handling, alongside patches to mitigate power and USB issues without full hardware fixes.

Airmont errata

Airmont-based processors, implemented in platforms such as Braswell and Cherry Trail, encountered a range of errata primarily affecting stability and system-level operations, though these were generally less prevalent than in the preceding Silvermont generation due to refinements from the 14 nm process shrink. These issues often required updates, driver revisions, or hardware stepping changes for mitigation, impacting the reliability of low-power tablets and embedded systems. Graphics functionality presented notable challenges, particularly with the integrated Gen8 GPU. In Cherry Trail devices, the GPU had limited DirectX 12 compatibility, which could lead to instability in applications attempting to use it. Braswell variants experienced HDMI audio output issues in some environments, affecting playback and requiring driver adjustments. Operating system interactions revealed additional limitations. Early Braswell silicon had challenges, patched via firmware updates from OEMs. Under , thermal management in custom distributions could be complicated by sensor interpretations. Overall, while Airmont's errata count was reduced compared to Bay Trail—owing to greater manufacturing maturity—these bugs nonetheless compromised tablet reliability, particularly in graphics-intensive or power-cycling use cases, underscoring the challenges of scaling low-power architectures.

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