Motorola 68000 series

• Generation one (internally 16/32-bit, and produced with 8-, 16-, and 32-bit interfaces)
  • 68000
  • 68EC000
  • 68SEC000
  • 68HC000
  • 68008
  • 68010
  • 68012
• Generation two (internally fully 32-bit)
  • 68020
  • 68EC020
  • 68030
  • 68EC030
• Generation three (pipelined)
  • 68040
  • 68EC040
  • 68LC040
• Generation four (superscalar)
  • 68060
  • 68EC060
  • 68LC060
• Others
  • Freescale 683XX (CPU32 aka 68330, 68360 aka QUICC)
  • Freescale ColdFire
  • Freescale DragonBall
  • Philips 68070
  • APOLLO CORE 68080 ^[2]

68010:

• Virtual memory support (restartable instructions)
• 'Loop mode' for faster string and memory library primitives
• Multiply instruction uses 14 fewer clock ticks
• 2 GiB directly accessible memory (68012 variant)

68020:

• 32-bit address & arithmetic logic unit (ALU)
• Three stage pipeline
• Instruction cache of 256 bytes
• Unrestricted word and longword data access (see alignment)
• 8× multiprocessing ability
• Larger multiply (32×32 → 64 bits) and divide (64÷32 → 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations
• Addressing modes added scaled indexing and another level of indirection
• Low cost, EC = 24-bit address

68030:

• Split instruction and data cache of 256 bytes each
• On-chip memory management unit (MMU) (68851)
• Low cost EC = No MMU
• Burst Memory Interface

68040:

• Instruction and data caches of 4 KB each
• Six stage pipeline
• On-chip floating-point unit (FPU)
• FPU lacks IEEE transcendental function ability
• FPU emulation works with 2E71M and later chip revisions
• Low cost LC = No FPU
• Low cost EC = No FPU or MMU

68060:

• Instruction and data caches of 8 KB each
• 10 stage pipeline
• Two cycle integer multiplication unit
• Branch prediction
• Dual instruction pipeline
• Instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU
• Low cost LC = No FPU
• Low cost EC = No FPU or MMU

The 680x0 line of processors has been used in a variety of systems, from high-end Texas Instruments calculators (the TI-89, TI-92, and Voyage 200 lines) to all of the members of the Palm Pilot series that run Palm OS 1.x to 4.x (OS 5.x is ARM-based), and even radiation-hardened versions in the critical control systems of the Space Shuttle.

The 680x0 CPU family became most well known for powering desktop computers and video game consoles such as the Macintosh 128K, Amiga, Sinclair QL, Atari ST, Genesis / Mega Drive, NG AES/Neo Geo CD, CDTV. They were the processors of choice in the 1980s for Unix workstations and servers such as AT&T's UNIX PC, Tandy's Model 16/16B/6000, Sun Microsystems' Sun-1, Sun-2, Sun-3, NeXT Computer, Silicon Graphics (SGI), and numerous others. The Saturn uses the 68000 for audio processing and other I/O tasks, while the Jaguar includes a 68000 intended for basic system control and input processing, but was frequently used for running game logic. Many arcade boards also use 68000 processors including those from Capcom, SNK, and Sega.

The first several versions of Adobe's PostScript interpreters were 68000-based. The 68000 in the Apple LaserWriter and LaserWriter Plus was clocked faster than the version used then in Macintosh computers. A fast 68030 in later PostScript interpreters, including the standard resolution LaserWriter IIntx, IIf and IIg (also 300 dpi), the higher resolution LaserWriter Pro 600 series (usually 600 dpi, but limited to 300 dpi with minimum RAM installed) and the very high resolution Linotronic imagesetters, the 200PS (1500+ dpi) and 300PS (2500+ dpi). Thereafter, Adobe generally preferred a RISC for its processor, as its competitors, with their PostScript clones, had already gone with RISCs, often an AMD 29000-series. The early 68000-based Adobe PostScript interpreters and their hardware were named for Cold War-era U.S. rockets and missiles: Atlas, Redstone, etc.

Microcontrollers derived from the 68000 family have been used in a huge variety of applications. CPU32 and ColdFire microcontrollers have been manufactured in the millions as automotive engine controllers.

Many proprietary video editing systems used 68000 processors, such as the MacroSystem Casablanca, which was a black box with an easy to use graphic interface (1997). It was intended for the amateur and hobby videographer market. It is also worth noting its earlier, bigger and more professional counterpart, the "DraCo" (1995). The groundbreaking Quantel Paintbox series of early based 24-bit paint and effects system was originally released in 1981 and during its lifetime it used nearly the entire range of 68000 family processors, with the sole exception of the 68060, which was never implemented in its design. Another contender in the video arena, the Abekas 8150 DVE system, used the 680EC30, and the Play Trinity, later renamed Globecaster, uses several 68030s. The Bosch FGS-4000/4500 Video Graphics System manufactured by Robert Bosch Corporation, later BTS (1983), used a 68000 as its main processor; it drove several others to perform 3D animation in a computer that could easily apply Gouraud and Phong shading. It ran a modified Motorola VERSAdos operating system.

People who are familiar with the PDP-11 or VAX usually feel comfortable with the 68000 series. With the exception of the split of general-purpose registers into specialized data and address registers, the 68000 architecture is in many ways a 32-bit PDP-11.

It had a more orthogonal instruction set than those of many processors that came before (e.g., 8080) and after (e.g., x86). That is, it was typically possible to combine operations freely with operands, rather than being restricted to using certain addressing modes with certain instructions. This property made programming relatively easy for humans, and also made it easier to write code generators for compilers.

The 68000 series has eight 32-bit general-purpose data registers (D0-D7), and eight address registers (A0-A7). The last address register is the stack pointer, and assemblers accept the label SP as equivalent to A7.

In addition, it has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from the carry flag. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.

While the 68000 had a 'supervisor mode', it did not meet the Popek and Goldberg virtualization requirements due to the single instruction 'MOVE from SR', which copies the status register to another register, being unprivileged but sensitive. In the Motorola 68010 and later, this was made privileged, to better support virtualization software.

The 68000 series instruction set can be divided into the following broad categories:

• Load and store (MOVE)
• Arithmetic (ADD, SUB, MULS, MULU, DIVS, DIVU)
• Bit shifting (ASL, ASR, LSL, LSR)
• Bit rotation (ROR, ROL, ROXL, ROXR)
• Logic operations (AND, OR, NOT, EOR)
• Type conversion (byte to word and vice versa)
• Conditional and unconditional branches (BRA, Bcc - BEQ, BNE, BHI, BLO, BMI, BPL, etc.)
• Subroutine invocation and return (BSR, RTS)
• Stack management (LINK, UNLK, PEA)
• Causing and responding to interrupts
• Exception handling
• There is no equivalent to the x86 CPUID instruction to determine what CPU or MMU or FPU is present.

The Motorola 68020 added some new instructions that include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.

The standard addressing modes are:

• Register direct
  • Data register, e.g. "D0"
  • Address register, e.g. "A0"
• Register indirect
  • Simple address, e.g. (A0)
  • Address with post-increment, e.g. (A0)+
  • Address with pre-decrement, e.g. −(A0)
  • Address with a 16-bit signed offset, e.g. 16(A0)
  • Register indirect with index register and 8-bit signed offset e.g. 8(A0,D0) or 8(A0,A1)

  For (A0)+ and −(A0), the actual increment or decrement value is dependent on the operand size: a byte access adjusts the address register by 1, a word by 2, and a long by 4.

• PC (program counter) relative with displacement
  • Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful for position-independent code.
  • Relative with 8-bit signed offset with index, e.g. 8(PC,D2)
• Absolute memory location
  • Either a number, e.g. "$4000", or a symbolic name translated by the assembler
  • Most assemblers used the "$" symbol for hexadecimal, instead of "0x" or a trailing H.
  • There were 16 and 32-bit versions of this addressing mode
• Immediate mode
  • Data stored in the instruction, e.g. "#400"
• Quick immediate mode
  • 3-bit unsigned (or 8-bit signed with moveq) with value stored in opcode
  • In addq and subq, 0 is the equivalent to 8
  • e.g. moveq #0,d0 was quicker than clr.l d0 (though both made D0 equal to 0)

Plus: access to the status register, and, in later models, other special registers.

The Motorola 68020 added a scaled indexing address mode, and added another level of indirection to many of the pre-existing modes.

Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes (".b"), 16-bit words (".w"), and 32-bit longs (".l").

Most instructions are dyadic, that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were:

• Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU, DIVS, NEG (additive negation), and CMP (a comparison done by subtracting the arguments without storing the result, setting the status bits)
• Binary-coded decimal arithmetic: ABCD, NBCD, and SBCD
• Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)
• Shifting: (logical, i.e. right shifts put zero in the most-significant bit) LSL, LSR, (arithmetic shifts, i.e. sign-extend the most-significant bit) ASR, ASL, (rotates through eXtend and not) ROXL, ROXR, ROL, ROR
• Bit test and manipulation in memory or data register: BSET (set to 1), BCLR (clear to 0), BCHG (invert) and BTST (no change). All of these instructions first test the destination bit and set (clear) the CCR Z bit if the destination bit is 0 (1), respectively.
• Multiprocessing control: TAS, test-and-set, performed an indivisible bus operation, permitting semaphores to be used to synchronize several processors sharing a single memory
• Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from subroutine), RTE (return from exception, i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)
• Branch: Bcc (where the "cc" specified one of 14 tests of the condition codes in the status register: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register). Of the remaining two possible conditions, always true and always false, BRA (branch always) has a separate mnemonic, and BSR (branch to subroutine) takes the encoding that would otherwise have been 'branch never'.
• Decrement-and-branch: DBcc (where "cc" was as for the branch instructions), which, provided the condition was false, decremented the low word of a D-register and, if the result was not -1 ($FFFF), branched to a destination. This use of −1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with, with no need for another check before entering the loop. This also facilitated nesting of DBcc.

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Motorola mainly used even numbers for major revisions to the CPU core such as 68000, 68020, 68040 and 68060. The 68010 was a revised version of the 68000 with minor modifications to the core, and likewise the 68030 was a revised 68020 with some more powerful features, none of them significant enough to classify as a major upgrade to the core.

The 68050 was reportedly "a minor upgrade of the 68040" that lost a battle for resources within Motorola, competing against projects that had been scheduled to succeed it: the 0.5μm, low-power, low-cost "LP040", and the superscalar, superpipelined "Q", borrowing from the 88110 and anticipated as the 68060.^[20] Subsequent reports indicated that Motorola had considered the 68050 as not meriting the necessary investment in production of the part.^[21] Odd-numbered releases had always been reactions to issues raised within the prior even numbered part; hence, it was generally expected that the 68050 would have reduced the 68040's power consumption (and thus heat dissipation), improved exception handling in the FPU, used a smaller feature size and optimized the microcode in line with program use of instructions. Many of these optimizations were included with the 68060 and were part of its design goals. For any number of reasons, likely that the 68060 was in development, that the Intel 80486 was not progressing as quickly as Motorola assumed it would, and that 68060 was a demanding project, the 68050 was cancelled early in development.

There is also no revision of the 68060, as Motorola was in the process of shifting away from the 68000 and 88k processor lines into its new PowerPC business, so the 68070 was never developed. Had it been, it would have been a revised 68060, likely with a superior FPU (pipelining was widely speculated upon on Usenet).

There was a CPU with the 68070 designation, which was a licensed and somewhat slower version of the 16/32-bit 68000 with a basic DMA controller, I²C host and an on-chip serial port. This 68070 was used as the main CPU in the Philips CD-i. This CPU was, however, produced by Philips and not officially part of Motorola's 680x0 lineup.

Motorola had announced a product roadmap beyond the 68060 featuring the 68080 rated at 200-350 MIPS, due by 1995, and a product rated at 800 MIPS, possibly with the name 68100, by 2000.^[21]

The 4th-generation 68060 provided equivalent functionality (though not instruction-set-architecture compatibility) to most of the features of the Intel P5 microarchitecture.

The Personal Computers XT/370 and AT/370 PC-based IBM-compatible mainframes each included two modified Motorola 68000 processors with custom microcode to emulate S/370 mainframe instructions.^[22][23]

An Arizona-based company, Edge Computer Corp, reportedly founded by former Honeywell designers, produced processors compatible with the 68000 series, these being claimed as having "a three to five times performance – and 18 to 24 months' time – advantage" over Motorola's own products.^[24] In 1987, the company introduced the Edge 1000 range of "32-bit superminicomputers implementing the Motorola instruction set in the Edge mainframe architecture", employing two independent pipelines - an instruction fetch pipeline (IFP) and operand executive pipeline (OEP) - relying on a branch prediction unit featuring a 4096-entry branch cache, retrieving instructions and operands over multiple buses.^[25] An agreement between Edge Computer and Olivetti subsequently led to the latter introducing products in its own "Linea Duo" range based on Edge Computer's machines.^[26] The company was subsequently renamed to Edgcore Technology Inc.^[27]: 12 (also reported as Edgecore Technology Inc.^[28]). Edgcore's deal with Olivetti in 1987 to supply the company's E1000 processor was followed in 1989 by another deal with Philips Telecommunications Data Systems to supply the E2000 processor, this supporting the 68030 instruction set and reportedly offering a performance rating of 16 VAX MIPS.^[29] Similar deals with Nixdorf Computer and Hitachi were also signed in 1989.^[30][31]

Edge Computer reportedly had an agreement with Motorola.^[28] Despite increasing competition from RISC products, Edgcore sought to distinguish its products in the market by emphasising its "alliance" with Motorola, employing a marketing campaign drawing from Aesop's fables with "the fox (Edgecore) who climbs on the back of the stallion (Motorola) to pluck fruit off the higher branches of the tree".^[32] Other folktale advertising themes such as Little Red Riding Hood were employed.^[33] With the company's investors having declined to finance the company further, and with a number of companies having been involved in discussions with other parties, Arix Corp. announced the acquisition of Edgcore in July 1989.^[31] Arix was reportedly able to renew its deal with Hitachi in 1990, whereas the future of previous deals with Olivetti and Philips remained in some doubt after the acquisition of Edgcore.^[34]

In 1992, a company called International Meta Systems (IMS) announced a RISC-based CPU, the IMS 3250, that could reportedly emulate the "Intel 486 or Motorola 68040 at full native speeds and at a fraction of their cost". Clocked at 100 MHz, emulations had supposedly been developed of a 25 MHz 486 and 30 MHz 68040, including floating-point unit support, with the product aiming for mid-1993 production at a per-unit cost of $50 to 60.^[35] Amidst the apparent proliferation of emulation support in processors such as the PowerPC 615, in 1994, IMS had reportedly filed a patent on its emulation technology but had not found any licensees.^[36] Repeated delays to the introduction of this product, blamed on one occasion on "a need to improve the chip's speech-processing capabilities",^[37] apparently led to the company seeking to introduce another chip, the Meta6000, aiming to compete with Intel's P6 products.^[38] Ultimately, IMS entered bankruptcy having sold patents to a litigator, TechSearch, who in 1998 attempted to sue Intel for infringement of an IMS patent.^[39] TechSearch reportedly lost their case but sought to appeal, also seeking to sue Intel for "libel and slander" on the basis of comments made by an Intel representative who had characterised TechSearch's business model unfavourably in remarks to the press.^[40]

After the mainline 68000 processors' demise, the 68000 family has been used to some extent in microcontroller and embedded microprocessor versions. These chips include the ones listed under "other" above, i.e. the CPU32 (aka 68330), the ColdFire, the QUICC and the DragonBall.

With the advent of FPGA technology an international team of hardware developers have re-created the 68000 with many enhancements as an FPGA core. Their core is known as the 68080 and is used in Vampire-branded Amiga accelerators.^[41]

Magnetic Scrolls used a subset of the 68000's instructions as a base for the virtual machine in their text adventures.

During the 1980s and early 1990s, when the 68000 was widely used in desktop computers, it mainly competed against Intel's x86 architecture used in IBM PC compatibles. Generation 1 68000 CPUs competed against mainly the 16-bit 8086, 8088, and 80286. Generation 2 competed against the 80386 (the first 32-bit x86 processor), and generation 3 against the 80486. The fourth generation competed with the P5 Pentium line, but it was not nearly as widely used as its predecessors, since much of the old 68000 marketplace was either defunct or nearly so (as was the case with Atari and NeXT), or converting to newer architectures (PowerPC for the Macintosh and Amiga, SPARC for Sun, and MIPS for Silicon Graphics (SGI)).

There are dozens of processor architectures that are successful in embedded systems. Some are microcontrollers which are much simpler, smaller, and cheaper than the 68000, while others are relatively sophisticated and can run complex software. Embedded versions of the 68000 often compete with processor architectures based on PowerPC, ARM, MIPS, SuperH, and others.

• VMEbus, an external computer bus standard designed for the 68000 series