Hubbry Logo
Gate arrayGate arrayMain
Open search
Gate array
Community hub
Gate array
logo
8 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
Contribute something
Gate array
Gate array
Gate array
View on Wikipedia
from Wikipedia
Sinclair ZX81 ULA

A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.[1]

Similar technologies have also been employed to design and manufacture analog, analog-digital, and structured arrays, but, in general, these are not called gate arrays.

Gate arrays have also been known as uncommitted logic arrays ('ULAs'), which also offered linear circuit functions,[2] and semi-custom chips.[3]

History

[edit]

Development

[edit]

Gate arrays had several concurrent development paths. Ferranti in the UK pioneered commercializing bipolar ULA technology,[4] offering circuits of "100 to 10,000 gates and above" by 1983,[5][6] although in practice delivering products with 4,000 gates at that time.[7] The company's early lead in semi-custom chips, with the initial application of a ULA integrated circuit involving a camera from Rollei in 1972, expanding to "practically all European camera manufacturers" as users of the technology, led to the company's dominance in this particular market throughout the 1970s. However, by 1982, as many as 30 companies had started to compete with Ferranti, reducing the company's market share to around 30 percent. Ferranti's "major competitors" were other British companies such as Marconi and Plessey, both of which had licensed technology from another British company, Micro Circuit Engineering.[8] A contemporary initiative, UK5000, also sought to produce a CMOS gate array with "5,000 usable gates", with involvement from British Telecom and a number of other major British technology companies.[9]

IBM developed proprietary bipolar master slices that it used in mainframe manufacturing in the late 1970s and early 1980s, but never commercialized them externally. Fairchild Semiconductor also flirted briefly in the late 1960s with bipolar arrays diode–transistor logic and transistor-transistor logic called Micromosaic and Polycell.[10]

CMOS (complementary metal–oxide–semiconductor) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp[11][12] in 1974 for International Microcircuits, Inc.[10] (IMI) a Sunnyvale photo-mask shop started by Frank Deverse, Jim Tuttle and Charlie Allen, ex-IBM employees. This first product line employed 7.5 micron single-level metal CMOS technology and ranged from 50 to 400 gates. Computer-aided design (CAD) technology at the time was very rudimentary due to the low processing power available, so the design of these first products was only partially automated.

This product pioneered several features that went on to become standard in future designs. The most important were: the strict organization of n-channel and p-channel transistors in 2-3 row pairs across the chip; and running all interconnect on grids rather than minimum custom spacing, which had been the standard until then. This later innovation paved the way to full automation when coupled with the development of 2-layer CMOS arrays. Customizing these first parts was somewhat tedious and error-prone due to the lack of good software tools.[10] IMI tapped into PC board development techniques to minimize manual customization effort. Chips at the time were designed by hand, drawing all components and interconnecting on precision gridded Mylar sheets, using colored pencils to delineate each processing layer. Rubylith sheets were then cut and peeled to create a (typically) 200x to 400x scale representation of the process layer. This was then photo-reduced to make a 1x mask. Digitization rather than rubylith cutting was just coming in as the latest technology, but initially, it only removed the rubylith stage; drawings were still manual and then "hand" digitized. PC boards, meanwhile, had moved from custom rubylith to PC tape for interconnects. IMI created to-scale photo enlargements of the base layers. Using decals of logic gate connections and PC tape to interconnect these gates, custom circuits could be quickly laid out by hand for these relatively small circuits, and photo-reduced using existing technologies.

After a falling out with IMI, Robert Lipp went on to start California Devices, Inc. (CDI) in 1978 with two silent partners, Bernie Aronson, and Brian Tighe. CDI quickly developed a product line competitive to IMI and, shortly thereafter, a 5-micron silicon gate single-layer product line with densities of up to 1,200 gates. A couple of years later, CDI followed up with "channel-less" gate arrays that reduced the row blockages caused by a more complex silicon underlayer that pre-wired the individual transistor connections to locations needed for common logic functions, simplifying the first-level metal interconnect. This increased chip densities by 40%, significantly reducing manufacturing costs.[11]

Innovation

[edit]
Ferranti ULA 2C210E on a Timex Sinclair 1000 motherboard

Early gate arrays were low-performance and relatively large and expensive compared to state-of-the-art n-MOS technology then being used for custom chips. CMOS technology was being driven by very low-power applications such as watch chips and battery-operated portable instrumentation, not performance. They were also well under the performance of the existing dominant logic technology, transistor–transistor logic. However, there were many niche applications where they were invaluable, particularly in low power, size reduction, portable and aerospace applications as well as time-to-market sensitive products. Even these small arrays could replace a board full of transistor–transistor logic gates if performance were not an issue. A common application was combining a number of smaller circuits that were supporting a larger LSI circuit on a board was affectionately known as "garbage collection". And the low cost of development and custom tooling made the technology available to the most modest budgets. Early gate arrays played a large part in the CB craze in the 1970s as well as a vehicle for the introduction of other later mass-produced products such as modems and cell phones.[13]

By the early 1980s, gate arrays were starting to move out of their niche applications to the general market. Several factors in technology and markets were converging. Size and performance were increasing; automation was maturing; the technology became "hot" when in 1981 IBM introduced its new flagship 3081 mainframe with CPU comprising gate arrays. They were used in a consumer product, the ZX81, and new entrants to the market increased visibility and credibility.[14][15]

In 1981, Wilfred Corrigan, Bill O'Meara, Rob Walker, and Mitchell "Mick" Bohn founded LSI Logic.[16] Their initial intention was to commercialize emitter coupled logic gate arrays, but discovered the market was quickly moving towards CMOS. Instead, they licensed CDI's silicon gate CMOS line as a second source. This product established them in the market while they developed their own proprietary 5-micron 2-layer metal line. This latter product line was the first commercial gate array product amenable to full automation. LSI developed a suite of proprietary development tools that allowed users to design their own chip from their own facility by remote login to LSI Logic's system.

Sinclair Research ported an enhanced ZX80 design to a ULA chip for the ZX81, and later used a ULA in the ZX Spectrum. A compatible chip was made in Russia as T34VG1.[17] Acorn Computers used several ULA chips in the BBC Micro, and later a single ULA for the Acorn Electron. Many other manufacturers from the time of the home computer boom period used ULAs in their machines. The IBM PC took over much of the personal computer market, and the sales volumes made full-custom chips more economical. Commodore's Amiga series used gate arrays for the Gary and Gayle custom chips, as their code names may suggest.

In an attempt to reduce the costs and increase the accessibility of gate array design and production, Ferranti introduced in 1982 a computer-aided design tool for their uncommitted logic array (ULA) product called ULA Designer. Although costing £46,500 to acquire, this tool promised to deliver reduced costs of around £5,000 per design plus manufacturing costs of £1-2 per chip in high volumes, in contrast to the £15,000 design costs incurred by engaging Ferranti's services for the design process.[18] Based on a PDP-11/23 minicomputer running RSX/11M, together with graphical display, keyboard, "digitalizing board", control desk and optional plotter, the solution aimed to satisfy the design needs of gate arrays from 100 to 10,000 gates, with the design being undertaken entirely by the organisation acquiring the solution, starting with a "logic plan", proceeding through the layout of the logic in the gate array itself, and concluding with the definition of a test specification for verification of the logic and for establishing an automated testing regime. Verification of completed designs was performed by "external specialists" after the transfer of the design to a "CAD center" in Manchester, England or Sunnyvale, California, potentially over the telephone network. Prototyping completed designs took an estimated 3 to 4 weeks. The minicomputer itself was also adaptable to run as a laboratory or office system where appropriate.[19]

Ferranti followed up on the ULA Designer with the Silicon Design System product based on the VAX-11/730 with 1 MB of RAM, 120 MB Winchester disk, and utilising a high-resolution display driven by a graphics unit with 500 KB of its own memory for "high speed windowing, painting, and editing capabilities". The software itself was available separately for organisations already likely to be using VAX-11/780 systems to provide a multi-user environment, but the "standalone system" package of hardware and software was intended to provide a more affordable solution with a "faster response" during the design process. The suite of tools involved in the use of the product included logic entry and test schedule definition (using Ferranti's own description languages), logic simulation, layout definition and checking, and mask generation for prototype gate arrays. The system also sought to support completely auto-routed designs, utilising architectural features of Ferranti's auto-routable (AR) arrays to deliver a "100-percent success auto-layout system" with this convenience incurring an increase in silicon area of approximately 25 percent. [20]

Other British companies developed products for gate array design and fabrication. Qudos Limited, a spin-off from Cambridge University, offered a chip design product called Quickchip available for VAX and MicroVAX II systems and as a complete $11,000 turnkey solution, providing a suite of tools broadly similar to those of Ferranti's products including automatic layout, routing, rule checking and simulation functionality for the design of gate arrays. Qudos employed electron beam lithography,[21] etching designs onto Ferranti ULA devices that formed the physical basis of these custom chips. Typical prototype production costs were stated as £100 per chip.[22] Quickchip was subsequently ported to the Acorn Cambridge Workstation, with a low-end version for the BBC Micro,[23] and to the Acorn Archimedes.[24]

Alternatives

[edit]

Indirect competition arose with the development of the field-programmable gate array (FPGA). Xilinx was founded in 1984, and its first products were much like early gate arrays, slow and expensive, fit only for some niche markets. However, Moore's law quickly made them a force and, by the early 1990s, were seriously disrupting the gate array market.[25]

Designers still wished for a way to create their own complex chips without the expense of full-custom design, and eventually, this wish was granted with the arrival of not only the FPGA, but complex programmable logic device (CPLD), metal configurable standard cells (MCSC), and structured ASICs. Whereas a gate array required a back-end semiconductor wafer foundry to deposit and etch the interconnections, the FPGA and CPLD had user-programmable interconnections. Today's approach is to make the prototypes by FPGAs, as the risk is low and the functionality can be verified quickly. For smaller devices, production costs are sufficiently low. But for large FPGAs, production is very expensive, power-hungry, and in many cases, do not reach the required speed. To address these issues, several ASIC companies like BaySand, Faraday, Gigoptics, and others offer FPGA to ASIC conversion services.

Decline

[edit]

While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling recessions during the 1980s that created a boom-bust cycle. The 1980 and 1981–1982 general recessions were followed by high-interest rates that curbed capital spending. This reduction played havoc on the semiconductor business, which at the time was highly dependent on capital spending. Manufacturers desperate to keep their fab plants full and afford constant modernization in a fast-moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on production revenues.[11]

As of the early 21st century, the gate array market was a remnant of its former self, driven by the FPGA conversions done for cost or performance reasons. IMI moved out of gate arrays into mixed-signal circuits and was later acquired by Cypress Semiconductor in 2001; CDI closed its doors in 1989; and LSI Logic abandoned the market in favor of standard products and was eventually acquired by Broadcom.[26]

Design

[edit]

A gate array is a prefabricated silicon chip with most transistors having no predetermined function. These transistors can be connected by metal layers to form standard NAND or NOR logic gates. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. The creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a printed circuit board.

The earliest gate arrays comprised bipolar transistors, usually configured as high-performance transistor–transistor logic, emitter-coupled logic, or current-mode logic logic configurations. CMOS (complementary metal–oxide–semiconductor) gate arrays were later developed and came to dominate the industry.

Gate array master slices with unfinished chips arrayed across a wafer are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than standard cell or full custom design. The gate array approach reduces the non-recurring engineering mask costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced — the same test fixtures can be used for all gate array products manufactured on the same die size. Gate arrays were the predecessor of the more complex structured ASIC; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.

An application circuit must be built on a gate array that has enough gates, wiring, and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a crossbar switch requires much more routing than a systolic array with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.

The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However, this style is often a viable approach for low production volumes.

Uses

[edit]

Gate arrays were used widely in the home computers in the early to mid 1980s, including in the ZX81, ZX Spectrum, BBC Micro, Acorn Electron, Advance 86, and Commodore Amiga.

In the 1980s, the Forth Novix N4016 and HP 3000 Series 37 CPUs, both stack machines were implemented by gate arrays as were some graphic terminal functions.[27][28] Some supporting hardware in at least 1990s DEC and HP servers was implemented by gate arrays.[29][30]

References

[edit]

Further reading

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Gate array

View on Grokipedia
from Grokipedia
A gate array is a type of (ASIC) that utilizes a prefabricated containing an array of unconnected transistors and basic logic gates, which are customized for specific functions through the addition of metal interconnect layers during the final manufacturing stages. This semi-custom approach allows for and reduced design costs compared to full-custom ICs, as only a few layers (typically 2-3) need customization rather than all layers. Gate arrays emerged as a key innovation in design, balancing efficiency, speed, and flexibility for digital logic implementation. The development of gate arrays began in the mid-1960s, driven by the need for faster ASIC production amid growing complexity in electronic systems. In 1967, Fairchild Semiconductor introduced the Micromatrix family, the first commercial bipolar gate arrays using diode-transistor logic (DTL) and transistor-transistor logic (TTL), which employed early computer-aided design (CAD) tools to enable interactive customization and reduce prototyping time from months to days. Early efforts also included "discretionary-wiring" techniques by IBM and Texas Instruments for military applications, while suppliers like Ferranti and Interdesign handled manual interconnect design. By 1974, the first CMOS gate array was designed by Robert Lipp at International Microcircuits, marking a shift toward lower-power, higher-density implementations, though CAD support for CMOS initially lagged. Gate arrays are classified into several types based on their architecture, primarily channeled gate arrays and channelless (sea-of-gates) arrays. Channeled gate arrays feature rows of pre-placed cells separated by dedicated channels for interconnects, providing predictable wiring paths but potentially lower due to fixed spacing. In contrast, sea-of-gates arrays arrange transistors in a uniform grid without predefined channels, allowing higher gate utilization and by treating the entire active area as customizable, though this increases complexity. A third variant, structured gate arrays, incorporates pre-designed (IP) blocks alongside the gate array for enhanced performance in specific applications. These designs offered gate delays as low as 85 picoseconds in advanced processes, such as Fujitsu's 0.35-μm CE61 series supporting up to 2000 kgates. The significance of gate arrays lies in their role as a foundational for modern VLSI design, enabling quicker adoption of emerging processes like and facilitating the transition to more advanced methodologies, including standard-cell libraries. While largely superseded by full-custom and standard-cell in high-volume production due to superior density and performance, gate arrays remain relevant in low-to-medium volume scenarios where turnaround time and cost are prioritized over optimization. Their legacy persists in influencing hybrid approaches and remains a staple in educational and prototyping contexts for understanding semi-custom IC fabrication.

Overview

Definition and Principles

A gate array is a prefabricated serving as a semi-custom (ASIC), featuring a fixed array of transistors—typically arranged in rows of n-channel and p-channel pairs—and customizable metal interconnect layers that enable the implementation of user-defined logic functions, such as gates and flip-flops. This structure allows the base die, known as the master slice, to be produced in advance without committing to a specific design, with personalization achieved through the patterning of metal layers to route signals between transistors. The fundamental principles of gate arrays revolve around uncommitted logic arrays (ULAs), where the master slice contains prefabricated rows of transistors and other active devices in a , leaving the interconnections undefined until the design phase. Customization occurs late in the fabrication process, often using two to three metal layers or a combination of metal and polysilicon, to connect the s into functional circuits; this approach minimizes risks by leveraging pre-verified base wafers. Routing channels—predefined horizontal and vertical spaces between transistor rows—facilitate these interconnections, ensuring efficient signal propagation without altering the underlying . As a semi-custom , gate arrays strike a balance between the low flexibility and quick availability of off-the-shelf logic chips and the high performance but lengthy development of full-custom , offering reduced cycles and costs through while allowing circuit-specific adaptations. Typical implementations support gate counts ranging from hundreds to thousands, such as 132 to 2,000 kilo-gates in advanced variants, making them suitable for medium- applications. The interconnection density in these is often estimated using Rent's rule, an empirical model expressed as T=aBpT = a B^p, where TT represents the number of terminals or pins, BB is the number of logic blocks or gates, aa is a constant, and pp (the Rent exponent) typically falls between 0.5 and 0.75; this relation aids in predicting channel requirements and overall wiring to ensure routability.

Key Components

The base forms the foundational layer of a gate array, consisting of prefabricated rows of complementary metal-oxide-semiconductor () transistors arranged in an array to enable the creation of standard logic cells. These transistors, initially fabricated using process nodes of 5–7.5 microns, include n-channel and p-channel devices formed in p-wells on an n-type substrate, allowing for the implementation of basic functions such as two- to five-input NAND gates (e.g., NA02 or NA03 cells) and D-type flip-flops (e.g., DF01 or DFOA cells with asynchronous reset/set capabilities). Interconnect layers provide the customizable wiring that connects these transistors into functional circuits, typically comprising two to three metal layers—often aluminum—for signal , with the first layer handling horizontal connections and subsequent layers supporting vertical runs and power distribution. Power and ground buses (VDD and VSS) are integrated across the chip via dedicated metal lines or diffusions, while input/output (I/O) pads incorporate drivers and buffers compatible with TTL or levels to interface with external systems. The master slice structure underpins the gate array's efficiency, featuring fixed diffusion areas (n+ and p+ regions for source/drain) and polysilicon gates pre-patterned over channels in a matrix of basic cells, separated by routing tracks typically 10–20 microns wide to accommodate interconnections without altering the base fabrication. This arrangement ensures high utilization of the area while reserving flexibility for user-specific wiring. Supporting elements embedded in the base die enhance reliability and performance, including clock distribution networks structured as inverter-based trees (e.g., using IL11 or IN01 drivers to support up to two flip-flops per stage) for synchronized logic operation and electrostatic discharge (ESD) protection via shunt diodes and series resistors on input pads to safeguard against voltage transients. These components collectively enable customization through targeted metal mask layers, allowing rapid adaptation of the prefabricated slice into application-specific integrated circuits.

Types

Bipolar Gate Arrays

Bipolar gate arrays, the foundational form of gate array technology, rely on bipolar junction transistors to implement logic functions, primarily through transistor-transistor logic (TTL) or families. These technologies leverage the high current-driving capability of bipolar transistors to achieve superior speed performance, with TTL offering moderate propagation delays and ECL providing even faster operation via non-saturating transistor configurations; however, both exhibit significantly higher power dissipation due to continuous current flow in bipolar devices. The architecture features prefabricated arrays of bipolar arranged in rows on a master slice, where the base diffusion, emitters, and collectors are pre-formed during initial fabrication. Customization is restricted to the deposition of one or more metal layers for interconnections, allowing users to configure , flip-flops, and other primitives without altering the underlying transistor structure; early devices typically supported gate counts of 100 to 1,000, balancing complexity with fabrication feasibility. These arrays deliver gate delays of 10–50 ns in TTL-based designs, enabling high-speed suitable for demanding environments, though the intricate bipolar fabrication process results in larger die areas and elevated costs relative to simpler MOS alternatives. A pioneering example is Ferranti's uncommitted logic arrays (ULAs), launched in 1972 as bipolar TTL gate arrays with up to several hundred gates, which found adoption in speed-critical applications like early consumer and computing .

CMOS and Advanced Variants

Complementary metal-oxide-semiconductor (CMOS) technology forms the foundation of modern gate arrays, utilizing pairs of p-type and n-type transistors to achieve low static power dissipation and high integration density. Introduced commercially around 1974, early CMOS gate arrays employed 7.5-micron processes with single-level metal interconnects, enabling gate counts from 50 to 400 in initial products developed by Robert Lipp for International Microcircuits, Inc. (IMI). This approach provided superior power efficiency compared to earlier technologies, as CMOS circuits consume negligible power when idle due to complementary operation, facilitating denser layouts without excessive heat generation. CMOS gate arrays evolved into two primary variants: channel-oriented designs, which reserve fixed routing channels between rows of logic cells for interconnections, and channel-less or "sea-of-gates" architectures, where wiring overlays the cell array directly. Channel-oriented variants dominated early implementations for their simpler routing but limited density due to pre-allocated channel space. In contrast, sea-of-gates designs eliminated dedicated channels to enable higher gate utilization and more efficient silicon use. Fujitsu's channel-less CMOS arrays, introduced commercially in the early 1980s, further exemplified this shift, achieving higher integration by treating the entire active area as a uniform grid of transistors. Advancements in the propelled CMOS gate arrays to sub-micron process nodes, such as 2-micron rules by mid-decade, enabling gate counts exceeding 10,000 and up to 20,000 in high-density masters. Later iterations integrated embedded RAM and ROM blocks directly into the master slice, enhancing functionality for complex logic without external components and supporting gate counts beyond 100,000 by the late . These developments prioritized scalability, with triple-layer metallization allowing finer routing pitches. Bipolar-CMOS (BiCMOS) gate arrays emerged in the mid-1980s as an advanced variant, combining the high-speed drive capability of bipolar transistors with the and low power of . This hybrid approach improved performance for mixed analog-digital applications, with delays reduced to 100-200 ps in later processes, though fabrication complexity increased costs compared to pure . Relative to bipolar gate arrays, variants offered improved noise immunity and fully static operation, eliminating the need for dynamic refresh and enabling reliable performance in noisy environments. However, delays ranged from 20 to 100 ns in early designs due to lower drive currents, prioritizing and power savings over the faster switching of bipolar circuits.

Design and Fabrication

Master Slice Fabrication

The fabrication of master slices for gate arrays involves standard wafer processing techniques, primarily using or bipolar technologies, to create a reusable base die with an array of uncommitted s and basic structures. This process produces identical slices in batches, where the undergoes fabrication up to the and polysilicon layers without any customer-specific customization. The resulting master slice features a fixed of transistor cells arranged in rows or channels, ready for later , enabling efficient production of multiple variants from the same prefabricated . Key steps in master slice fabrication mirror conventional integrated circuit processing but halt before metal layer deposition to allow for personalization. Photolithography patterns the transistor structures on the silicon wafer, defining active areas and gate locations with high precision using masks for repetitive features. Ion implantation introduces dopants to form n-type and p-type regions, establishing the necessary electrical properties for CMOS transistors (e.g., n-wells in p-substrate processes) or bipolar junctions. Etching then removes excess material to delineate base structures, such as isolation regions and contact areas, ensuring the uniformity of the transistor array across the die. These steps leverage mature, high-volume fabrication lines, resulting in master slices with consistent electrical characteristics. Economically, this approach amortizes the costs of the initial and polysilicon layers over numerous custom designs, reducing expenses and turnaround times compared to full-custom , making it viable for medium-volume applications. These slices incorporate a fixed ring of I/O pads around the periphery to standardize and interfaces across designs.

Interconnection and Customization

The interconnection and customization phase of gate array design represents the final personalization step, where user-specified logic is mapped onto the prefabricated master slice through targeted of interconnects. This begins with the placement of logic cells—predefined arrangements—onto the fixed base array using (CAD) tools. These tools employ automated place-and-route algorithms to position cells efficiently while minimizing wire lengths and congestion, often leveraging techniques like for iterative optimization. Once placed, the phase connects these cells via channels or over-the-cell areas, generating mask patterns specifically for the metal layers to define the wiring. For instance, tools such as integrate placement and detailed simultaneously, using graph-coloring representations to ensure routability constraints influence cell positioning from the outset. Customization relies on a limited number of metal layers, typically 2 to 3 aluminum layers, to form the interconnects, with vias providing vertical connections between layers and contact masks enabling links to the underlying or polysilicon regions. In channeled gate arrays, occurs within predefined channels using horizontal and vertical tracks on alternating metal layers (e.g., metal 1 for horizontal, metal 2 for vertical), while channelless variants allow over-cell for higher by customizing contact masks to connect transistors directly. Aluminum is favored for its low resistivity (around 50 mΩ/square for metal 2 in typical processes) and compatibility with standard fabrication, though it requires careful management of and (approximately 0.2 pF/mm). Vias, formed through etched layers, ensure reliable interlayer connections without altering the base patterns. This layered approach confines personalization to the upper interconnect strata, preserving the integrity of the pre-fabricated array. Following , verification ensures the customized meets and manufacturability requirements through a series of checks, including design rule checks (DRC) to detect layout violations, static timing to validate signal propagation delays, and logic to confirm functional behavior. DRC tools scan for spacing, width, and enclosure errors in the metal and via patterns, while timing accounts for delays and interconnect capacitances to prevent setup or hold violations. at the level verifies the against the original specifications, often using the same CAD environments that handled placement. The entire post- turnaround time, encompassing mask production and fabrication of the customized layers, typically ranges from a few days to a couple of weeks. A key economic advantage of this phase is the reduced mask count required for customization—generally 3 to 5 masks for metal, via, and contact layers—contrasted with over 20 masks in full-custom , which personalize nearly all layers. This minimization of custom masks substantially lowers non-recurring engineering (NRE) costs, historically to approximately $10,000 to $50,000 in the late , primarily covering CAD tool usage, mask fabrication, and limited wafer processing, making gate arrays viable for medium-volume production. Historical data from the and underscores this efficiency, with NRE often shared across base array inventories to further amortize expenses.

Historical Development

Early Development (1970s)

The development of gate arrays in the emerged as a response to the growing demand for semi-custom integrated circuits that could deliver tailored logic functionality for emerging applications, such as microcomputers and , without the prohibitive costs and long lead times of full-custom designs. Early efforts were heavily influenced by IBM's internal use of gate array-like structures in mainframe systems during the decade, which demonstrated the feasibility of pre-fabricated arrays customized via metal interconnect layers. This approach addressed the limitations of off-the-shelf logic chips like TTL, enabling more compact and efficient custom logic at reduced non-recurring engineering expenses. Pioneering commercial implementations began with bipolar technology. In 1972, Ferranti Electronics in the UK introduced uncommitted logic arrays (ULAs), starting with bipolar circuits offering 100 to 500 gates, which were first applied in a camera design. These ULAs utilized a simple collector-diffusion isolation process with approximately five masks, allowing rapid customization through metal personalization while keeping fabrication costs low compared to PMOS equivalents. Concurrently, variants appeared; in 1974, Robert Lipp developed the first gate arrays at International Microcircuits, Inc. (IMI), employing 7.5-micron single-level metal technology with capacities ranging from 50 to 400 gates. By 1975, the first widespread commercial ULAs were available, marking a key milestone in accessible semi-custom ICs. Gate densities progressed significantly through the decade, reaching up to 1,000 gates by the late 1970s, driven by refinements in bipolar and early processes. However, challenges persisted: bipolar arrays suffered from high power consumption due to their characteristics, limiting applications in battery-powered devices, while initial prototypes faced low yields from immature fabrication techniques and limited support. These hurdles underscored the trade-offs in early gate array adoption, prioritizing speed in bipolar over power efficiency in .

Commercialization and Innovations (1980s)

The commercialization of gate arrays accelerated in the early 1980s, driven by pioneering companies that scaled production and introduced -based designs for broader market adoption. LSI Logic, founded in 1981 by Wilfred Corrigan and colleagues, played a pivotal role by focusing on gate arrays derived from prefabricated masterslices, enabling faster customization and lower costs compared to full-custom ICs. This approach addressed the growing demand for application-specific integrated circuits () in and , with LSI Logic's products emphasizing high-density logic integration. Similarly, California Devices Inc. (CDI), established in the late 1970s, advanced gate array technology through channel-less designs in the 1980s, which eliminated fixed wiring channels to improve silicon utilization and boost usable gate density by approximately 40% over traditional channeled arrays. Key innovations in design tools and applications further propelled gate array adoption. In 1982, introduced the ULA Designer, a (CAD) software package that simplified the mapping of logic designs onto uncommitted logic arrays (ULAs), drastically reducing development costs to around £5,000 for prototypes and making the accessible to smaller firms. These ULAs found widespread use in , notably powering the logic circuitry in home computers such as the Sinclair ZX81 (launched 1981), (1982), and (1981), where a single ULA consolidated multiple discrete components into one chip for cost-effective production. Gate arrays also entered enterprise computing, as evidenced by their integration in the 3081 mainframe processor announced in 1981, which employed Schottky TTL-based gate arrays for enhanced performance in large-scale systems. Market expansion in the reflected the technology's maturity, with gate counts scaling from 4,000 to 10,000 usable gates per array, supporting more complex designs in emerging digital applications. The global ASIC market, dominated by gate arrays as a semi-custom solution, grew rapidly, reaching billions in annual revenues by the mid-1980s amid surging demand for customized logic in electronics. This growth was bolstered by the emergence of (EDA) software tailored for gate array workflows, including tools for and that streamlined the semi-custom ASIC paradigm and shifted the industry from discrete components toward integrated solutions.

Decline and Alternatives (1990s Onward)

The decline of gate arrays began in the 1990s as the shifted toward more flexible and cost-effective alternatives, particularly following their commercialization peak in the . A key driver was the introduction of field-programmable gate arrays (FPGAs) by in 1984, which provided reprogrammability for changes without requiring new fabrication runs. By the mid-1990s, advancing FPGA architectures and manufacturing economies reduced their costs below those of gate arrays for low- to medium-volume production, eroding the latter's market share in applications needing quick turnaround. This transition was accelerated by the limitations of gate arrays in achieving higher densities and performance as process nodes scaled below 1 micron, making them less competitive against emerging technologies. Market dynamics further contributed to the obsolescence of gate arrays, with major players exiting or pivoting away from the technology. International Microcircuits Inc. (IMI), an early pioneer in gate arrays, shifted focus to mixed-signal and timing circuits before its acquisition by in 2001 for approximately $125 million. LSI Logic, once a dominant gate array supplier, transitioned toward platform-based solutions like its RapidChip structured ASIC in the early , reflecting broader industry moves to hybrid approaches. By the early , the gate array market had contracted dramatically to a niche segment, primarily for specialized or low-volume custom needs, as demand consolidated around more versatile options. Despite their decline, gate arrays left a lasting legacy by influencing the development of structured , which adopted prefabricated base layers for faster customization while improving on gate array efficiency. In the post-2000 era, gate arrays were largely superseded by standard cell , which offered superior density and routability for high-performance applications through fully customizable layouts from the level. Today, as of 2025, gate arrays see rare use in maintaining legacy systems or very low-volume custom designs, with no significant market revival amid the dominance of FPGAs and integrated system-on-chip (SoC) solutions that prioritize and power efficiency.

Applications

Uses in Computing

Gate arrays played a pivotal role in the development of home computers during the early 1980s by enabling cost-effective custom logic integration. In the Sinclair ZX81, released in 1981, a Ferranti Uncommitted Logic Array (ULA), a type of gate array, handled video generation, timing logic, keyboard scanning, and memory interfacing, reducing the overall chip count to just four main components and facilitating affordable production for mass-market appeal. Similarly, the ZX Spectrum employed a ULA for glue logic, including interrupt handling, I/O control, and video timing, which streamlined the system's architecture and contributed to its widespread adoption in consumer computing. The Amiga series, starting with the Amiga 500 in 1987, utilized the "Gary" gate array chip for bus arbitration, memory management, and peripheral interfacing, providing essential glue logic that supported the system's advanced multimedia capabilities in a compact design. In mainframe and server environments, gate arrays supported high-performance custom processors during the 1980s. IBM's 3081 mainframe, introduced in 1981, incorporated Schottky TTL gate arrays within its thermal conduction modules to implement the CPU logic, enabling reliable operation in enterprise computing with improved density over discrete components. Hewlett-Packard's 3000 Series 37 minicomputer, launched in 1984, featured a single CMOS gate array chip comprising nearly 8,000 gates for the core CPU functions, including microprogrammed control and register operations, which enhanced performance and reduced power consumption in server-like applications. Digital Equipment Corporation also employed gate arrays for custom logic in its VAX-based servers, optimizing interconnects and control functions to meet the demands of multi-user computing environments. Gate arrays were instrumental in peripherals for 1980s computing systems, particularly for graphics and memory handling. The , introduced in 1981, integrated custom ULAs as gate arrays to manage video output, including RGB signal generation and attribute handling from the CRTC, as well as memory refresh and I/O decoding, which supported its role as an educational and hobbyist platform. The adoption of gate arrays in the 1980s significantly boosted the boom by allowing manufacturers to produce low-cost, semi-custom chips at scale, with millions of home computers like the and benefiting from reduced design times and component costs compared to full-custom .

Industrial and Other Applications

Gate arrays, particularly in the form of uncommitted logic arrays (ULAs), saw early adoption in for control logic. In 1972, implemented a ULA in a camera, providing custom digital functions for exposure and shutter control, which represented one of the first commercial applications of semi-custom chips in equipment. This innovation allowed manufacturers to integrate tailored logic without the expense of full-custom designs, paving the way for broader use in devices during the 1970s. By the 1980s, gate arrays expanded into and automotive sectors. In telecom switches, they enabled efficient custom logic for signal routing and , supporting the transition to digital communication networks. Similarly, in automotive electronic control units (ECUs), gate arrays handled dedicated tasks such as engine timing and sensor interfacing, improving reliability in vehicle systems amid growing electronic integration. In industrial applications, gate arrays have been employed in custom controllers for machinery, where they provide fixed logic for and process control in manufacturing equipment. In medical devices, standard gate arrays facilitate for tasks like in diagnostic tools, ensuring precise and compact implementations. Radiation-hardened variants leveraging technologies have been used in and applications to withstand in space environments, though deployment has been limited due to elevated fabrication costs compared to commercial grades. Legacy gate array systems persist in select and legacy platforms as of 2025, valued for their proven reliability in fixed-configuration scenarios. In niche low-volume custom logic needs, gate arrays continue to serve where FPGAs introduce unnecessary reprogrammability overhead, offering a more economical fixed alternative for production runs in the thousands.

Comparisons

Versus Full-Custom ASICs

Gate arrays represent a semi-custom approach to , utilizing a prefabricated master slice with fixed arrays that are customized solely through metal interconnect layers. In contrast, full-custom involve optimization across all layers, including placement and layout, to achieve maximum density and performance tailored to the specific application. This fixed-base structure in gate arrays simplifies the fabrication process but limits flexibility compared to the transistor-level customization possible in full-custom designs. Gate arrays offer significant advantages in cost and time-to-market over full-custom , making them suitable for scenarios where rapid development is prioritized. (NRE) costs for gate arrays typically range from $80,000 to $150,000, far lower than the $1 million or more required for full-custom designs due to reduced mask sets and fabrication steps. Development timelines for gate arrays span weeks, often 1 to 2 weeks for fabrication after design, versus several months for full-custom , which demand extensive layout and verification efforts. However, these benefits come at the expense of and ; gate arrays exhibit 20–50% lower logic density and operating speeds than full-custom equivalents because of the constraints imposed by the predefined grid. In practice, gate arrays are favored for medium-volume production runs and prototyping, where cost savings and quicker iteration outweigh the need for peak optimization, such as in peripheral I/O circuits or chips. Full-custom , conversely, dominate high-volume applications like microprocessors and central processing units, where the amortized NRE costs enable superior per-unit through minimized die size and enhanced performance. This delineation reflects the between upfront and long-term in ASIC selection. Key metrics highlight these differences: gate arrays typically achieve high silicon utilization (often 70-90% in practice) due to inefficiencies on the fixed base, while full-custom designs approach 100% through precise transistor-level optimization. Such utilization gaps underscore why gate arrays, despite their accessibility, cannot match the compactness and speed of fully circuits.

Versus FPGAs and Structured ASICs

Gate arrays, which rely on a prefabricated array of transistors customized solely through metal interconnect layers, differ fundamentally from field-programmable gate arrays (FPGAs) in terms of flexibility and customization approach. FPGAs, first commercialized by with the XC2064 device in , employ an of configurable logic blocks containing lookup tables (LUTs) for implementing arbitrary logic functions and programmable interconnects for routing signals. This reprogrammable nature allows FPGAs to be configured post-manufacturing via software, enabling and iterative design changes with zero non-recurring engineering () costs for modifications, unlike gate arrays that become fixed after a single metal-layer fabrication step. However, FPGAs incur higher unit costs and exhibit lower logic density compared to gate arrays, with typical utilization efficiencies of 50–70% due to overhead from programmable and LUT structures, versus gate arrays' higher efficiency from their more compact, fixed base. Gate arrays offer medium NRE costs and faster initial turnaround for low-to-medium volumes but lack reprogrammability, making them less suitable for designs requiring field updates, where FPGAs—available in volatile SRAM-based or non-volatile flash/anti-fuse variants—provide ongoing adaptability. Structured ASICs, emerging in the early as a hybrid technology, extend the array concept by pre-fabricating not only arrays but also additional fixed elements such as embedded memory blocks, I/O pads, and initial metal/via layers, with customization limited to the final one or two metal layers. This structured base enhances area efficiency over traditional arrays' unstructured "sea-of-gates" layout while bridging the gap to full-custom by reducing design complexity and to 4–13 weeks, compared to arrays' 1–2 weeks. Structured ASICs thus provide lower NRE and faster time-to-market than full-custom designs but offer even less flexibility than arrays, as their predefined blocks limit architectural tweaks. In modern contexts, gate arrays have become largely obsolete for new designs, supplanted by FPGAs for prototyping and low-volume applications where reprogrammability is key, and by structured for mid-volume production needing ASIC-like performance without full-custom overhead. Legacy gate array use persists in some maintained systems, but the shift reflects FPGAs' dominance in iterative development and structured ASICs' role in cost-effective scaling.

References

  1. https://www.computerhistory.org/siliconengine/application-specific-integrated-circuits-employ-computer-aided-design/
  2. https://www.sciencedirect.com/topics/computer-science/gate-array
  3. https://www.sciencedirect.com/science/article/pii/B9780750657358500291
  4. https://personal.utdallas.edu/~zhoud/EE6306/lecture%20slides/ASIC%202011%20chapter%202%20flow%20and%20perspective.pdf
  5. https://www.sciencedirect.com/science/article/pii/B0122274105007961
  6. https://www.sciencedirect.com/science/article/pii/B978012734530750012X
  7. https://dl.acm.org/doi/10.1145/74382.74478
  8. http://www.bitsavers.org/components/ami/_dataBooks/1985_AMI_Gate_Array_Data_Book.pdf
  9. https://hardwarebee.com/introduction-to-gate-array/
  10. https://patents.google.com/patent/US4837461A/en
  11. https://learninglink.oup.com/protected/files/content/file/1581691164795-Sedra8e_BonusTextTopics-x8.pdf
  12. https://secwww.jhuapl.edu/techdigest/content/techdigest/pdf/V07-N03/07-03-Charles.pdf
  13. https://www.edn.com/uncommitted-ic-logic/
  14. https://www.computerhistory.org/siliconengine/people/
  15. https://ieeexplore.ieee.org/document/5468867
  16. http://www.bitsavers.org/components/fujitsu/_dataBooks/1990_Fujitsu_Channelless_Gate_Arrays.pdf
  17. https://ntrs.nasa.gov/api/citations/19830028087/downloads/19830028087.pdf
  18. https://pg024ec.wordpress.com/wp-content/uploads/2013/09/01_asic-book-by-michael-smith.pdf
  19. https://ieeexplore.ieee.org/document/1051997
  20. https://www.renesas.com/en/document/bro/asic-technology-handbook-gate-array-cellbased-co
  21. https://www.researchgate.net/publication/220760150_Gambit_A_Tool_for_the_Simultaneous_Placement_and_Detailed_Routing_of_Gate-Arrays
  22. https://www.cad-journal.net/files/vol_5/CAD_5%281-4%29_2008_325-337.pdf
  23. https://www.tce.edu/sites/default/files/PDF/14EC770-ASIC-DESIGN-K-Kalyani.pdf
  24. https://www.southampton.ac.uk/~bim/notes/cga/cga_des.html
  25. https://parts.jpl.nasa.gov/asic/Sect.2.3.html
  26. https://www.tekmos.com/about/blog/explaining-nre-s
  27. https://www.eetimes.com/convert-an-fpga-to-a-gate-array-at-project-start/
  28. https://people.eecs.berkeley.edu/~randy/Courses/CS150.S01/Lectures/11-FPGAsa.pdf
  29. https://aresluna.org/ic-at-fifty-booklet.pdf
  30. https://www.pearsonhighered.com/assets/samplechapter/0/1/3/0/0130321621.pdf
  31. https://semiengineering.com/entities/lsi-logic/
  32. http://archive.computerhistory.org/resources/access/text/2013/04/102723451-05-01-acc.pdf
  33. https://archive.computerhistory.org/resources/access/text/2012/04/102746194-05-01-acc.pdf
  34. https://apps.dtic.mil/sti/pdfs/ADA364980.pdf
  35. https://engx.theiet.org/b/blogs/posts/remarkable-what-can-be-done-when-the-price-is-right
  36. https://www.vintage-radio.net/forum/showthread.php?p=1396228
  37. http://ftpmirror.your.org/pub/misc/bitsavers/pdf/datapro/datapro_reports_70s-90s/IBM/70C-491-07_8103_IBM_3081.pdf
  38. http://archive.computerhistory.org/resources/access/text/2013/04/102723227-05-01-acc.pdf
  39. https://www.shmj.or.jp/english/integredcircuits/ic80s.html
  40. https://www.amd.com/content/dam/amd/en/documents/corporate/cr/xilinx-overview.pdf
  41. https://www.eetimes.com/fpgas-as-asic-alternatives-past-future/
  42. https://www.monolithic3d.com/blog/fpga-as-asic-alternative-past-and-future
  43. https://www.computerhistory.org/siliconengine/companies/
  44. https://www.edn.com/cypress-acquires-imi-for-125m-2/
  45. https://www.design-reuse.com/news/202505022--lsi-logic-announces-rapidchip-an-innovative-semiconductor-platform/
  46. https://www.eetimes.com/the-missing-link-of-soc-designplatform-and-structured-asics/
  47. https://www.dataweek.co.za/news.aspx?pklnewsid=7143
  48. http://www.breakintoprogram.co.uk/hardware/computers/zx81/hardware/ula
  49. https://www.spectrumforeveryone.com/technical/zx-spectrum-ula-types/
  50. https://www.amigawiki.org/doku.php?id=en:parts:custom_chips
  51. https://dl.acm.org/doi/pdf/10.5555/800263.809190
  52. https://lastin.dti.supsi.ch/VET/sys/HP/HP-3000-Serie-37/HPJournal1985Sep-3000Ser37-24pages.pdf
  53. https://archive.computerhistory.org/resources/access/text/2018/08/102740407-05-01-acc.pdf
  54. https://8bs.com/inbbcmapped.htm
  55. https://digital-library.theiet.org/doi/abs/10.1049/ep.1982.0108
  56. https://www.mddionline.com/components/choosing-semiconductor-components-for-medical-products
  57. https://www.einfochips.com/blog/asic-prototyping-and-asic-vs-fpga-which-one-to-consider/
  58. https://personal.utdallas.edu/~zhoud/Lecture1.pdf
  59. http://web.cecs.pdx.edu/~mperkows/temp/May13/lecture014.CPLD-FPGA.pdf
  60. https://www.eng.auburn.edu/~nelson/courses/elec5250_6250/slides/Lecture%202%20-%20ASIC%20Cost.pdf
  61. https://semiwiki.com/fpga/1596-a-brief-history-of-fpgas/
  62. https://www.ibm.com/think/topics/field-programmable-gate-arrays
  63. https://www.eecg.toronto.edu/~jayar/pubs/betz/DT98.pdf
  64. https://electronics.stackexchange.com/questions/150058/what-are-the-differences-and-similarities-between-fpga-asic-and-general-microco
  65. https://www.edn.com/structured-asics-allow-improved-design-flow/
  66. https://www.design-reuse.com/article/57904-structured-asic-based-soc-design/
  67. https://www.eetimes.com/how-hybrid-structured-asics-provide-low-cost-solutions-for-mid-range-applications/
  68. https://www.design-reuse.com/article/58475-all-about-fpgas/
Add your contribution
Related Hubs
Contribute something
User Avatar
No comments yet.