JEDEC
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The Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association is a consortium of the semiconductor industry headquartered in Arlington, United States. It has over 300 members and is focused on standardization of part numbers, defining an electrostatic discharge (ESD) standard, and leadership in the lead-free manufacturing transition.[1]
Key Information
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The origin of JEDEC traces back to 1944, when RMA (subsequently renamed EIA) and NEMA established the Joint Electron Tube Engineering Council (JETEC) to coordinate vacuum tube type numberings.
In 1958, with the advent of semiconductor technology, the joint JETEC-activity of EIA and NEMA was renamed into Joint Electron Device Engineering Council.[1] NEMA discontinued its involvement in 1979. In the fall of 1999, JEDEC became a separate trade association under the current name, but maintained an EIA alliance, until EIA ceased operations in 2011.
History
[edit]
The origin of JEDEC can be traced back to 1944, when the Radio Manufacturers Association (RMA), and the National Electrical Manufacturers Association (NEMA) established the Joint Electron Tube Engineering Council (JETEC) to coordinate vacuum tube type numberings. The expansion of the radio industry caused JETEC to expand its scope to include solid-state devices and develop standards for semiconductor devices. Eventually, the joint JETEC activity of EIA and NEMA was renamed into Joint Electron Device Engineering Council (JEDEC) in 1958.[1] NEMA discontinued its involvement in 1979.
Earlier in the 20th century, the organization was known as JETEC, the Joint Electron Tube Engineering Council, and was responsible for assigning and coordinating RETMA tube designations to electron tubes (also called valves). The type 6L6, still to be found in electric-guitar amplifiers, typically has a type number that was assigned by JETEC.
In the fall of 1999, JEDEC became a separate trade association under the current name, but maintained an EIA alliance.
Standards policies
[edit]JEDEC has adopted the principle of open standards, which permit any and all interested companies to freely manufacture in compliance with adopted standards. This serves several vital functions for the advancement of electronic technologies. First and foremost, such standards allow for interoperability between different electrical components. JEDEC standards do not protect members from normal patent obligations. The designated representatives of JEDEC member companies are required to disclose patents and patent applications of which they are aware, assuming that this information is not considered proprietary. JEDEC patent policy requires that standards found to contain patented technology, whose owners do not sign a standard JEDEC patent letter, be withdrawn. Thus the penalty for a failure to disclose patents is retraction of the standard. Typically, standards are not adopted to cover technology that are subject to patent protection. In rare circumstances, standards covered by a patent may be adopted, but only on the understanding that the patent owner will not enforce such patent rights or, at a minimum, that the patent owner will provide a reasonable and non-discriminatory license to the patented technology.[2]
Part numbers
[edit]JEDEC's early work began as a part numbering system for devices which became popular in the 1960s. The first semiconductor devices, such as the 1N23 silicon point contact diode, were still designated in the old RMA tube designation system, where the "1" stood for "No filament/heater" and the "N" stood for "crystal rectifier". The first RMA digit thus was re-allocated from "heater power" to "p-n junction count" to form the new EIA/JEDEC EIA-370 standard; for example, the 1N4001 rectifier diode and 2N2222 transistor part numbers came from EIA-370. They are still popular today. In February 1982, JEDEC issued JESD370B, superseding the original EIA-370 and introducing a new letter symbol "C" that denotes the die version, as opposed to "N", now meaning the packaged version. The Japanese JIS semiconductor designation system employs a similar pattern. JEDEC later developed a numbering system for integrated circuits, but this did not gain acceptance in the semiconductor industry. The European Pro Electron semiconductor numbering system originated in a similar way from the older Mullard–Philips tube designation.
Test methods and product standards
[edit]This early work was followed by a number of test methods, JESD22, and product standards. For example, the ESD caution symbol, which is the hand with the line drawn through it, was published by JEDEC and is used worldwide. JEDEC also has a dictionary of semiconductor terms. All of JEDEC standards are free on the Web for downloading after a free registration.
JEDEC has issued widely used standards for device interfaces, such as the JEDEC memory standards for computer memory (RAM), including the DDR SDRAM standards.
Semiconductor package drawings
[edit]JEDEC also developed a number of popular package drawings for semiconductors such as TO-3, TO-5, etc. These are on the web under JEP-95. One hot issue is the development of lead-free packages that do not suffer from the tin whiskers problem that reappeared since the recent ban on lead content. JEDEC is working with iNEMI on a joint interest group on lead-free issues.
Members
[edit]As of 2023, JEDEC has 365 members in total. Among them are large companies, which include the following:[3]
- ABB
- Alibaba
- AMD
- Apple
- Arm
- Buffalo
- Canon
- Foxconn
- Fujitsu
- Kioxia – formerly Toshiba Memory Corporation
- LG
- Marvell
- Micron
- Microsoft
- NEC
- Nokia
- Nvidia
- NXP
- Hewlett Packard Enterprise
- HP Inc.
- Huawei
- IBM
- Infineon
- Intel
- Panasonic
- Qualcomm
- Realtek
- Samsung Electronics
- SK Hynix
- Sony
- Texas Instruments
- TSMC
- Western Digital
References
[edit]- ^ a b c "JEDEC History". jedec.org. JEDEC. Retrieved 1 May 2017.
- ^ "JEDEC Manual of Organization and Procedure JM21-L (§8.2)" (PDF). JEDEC Solid State Technology Association. July 2002. Archived from the original (PDF) on 2006-03-08.
- ^ "Member List | JEDEC". jedec.org. Archived from the original on 2023-08-02. Retrieved 2023-10-08.
External links
[edit]
- Official website
- List of JEDEC member companies
- JEP95, the master JEDEC package list (free registration required)
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JEDEC
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Overview
Purpose and Scope
JEDEC Solid State Technology Association is a U.S.-based non-profit trade association dedicated to developing open standards for the microelectronics industry. Headquartered in Arlington, Virginia, it serves as a global leader in creating, publishing, and promoting voluntary standards that ensure product interoperability, reduce time-to-market, and lower development costs across diverse technical needs. With over 360 member companies and more than 3,000 volunteers, JEDEC fosters cooperative activities to support the solid state technology sector.[1][4][5] The primary scope of JEDEC focuses on standardizing microelectronics components, including memory interfaces, device reliability, and packaging, to enable seamless global interoperability in semiconductor design, manufacturing, and application. Key activities involve collaborative development of standards for discrete solid state devices, integrated circuits, electronic modules, and related manufacturing support functions through more than 50 committees and subcommittees. These efforts utilize an electronic voting process with a "one company, one vote" policy, resulting in widely adopted publications that address industry-wide needs without mandating compliance.[1] JEDEC now prioritizes standards that enable high-performance computing and AI-driven innovations. For example, its development of the DDR5 memory standard underscores ongoing contributions to advanced data processing and storage solutions.[3][6]Organizational Framework
JEDEC is governed by a Board of Directors elected by its member companies, which approves finalized standards and oversees organizational policies. As of 2025, the Board is chaired by Mian Quddus of Samsung Semiconductor, with executive leadership provided by President John J. Kelly.[7][8] A dedicated technical staff supports the publication and maintenance of standards, ensuring compliance with ANSI accreditation and global liaison activities.[1] The organization's key components consist of over 50 technical committees and subcommittees, organized by technology areas including memory devices, packaging, and reliability testing, complemented by task groups, with more than 100 committees, subcommittees, and task groups in total, for specialized work. These bodies draw on thousands of volunteers from over 360 member companies to address industry needs in solid-state technology.[1][9] JEDEC's operational model is member-driven and consensus-based, with decisions made through electronic balloting under a "one company, one vote" policy. Committees and working groups draft standards during regular meetings held several times annually, both in-person and virtually, fostering collaborative development. Member involvement includes mandatory patent disclosure policies to promote open standards without intellectual property encumbrances.[1][10] Funding is primarily sourced from membership dues, structured by the Board to support operations and committee activities. Most published standards are accessible for free upon registration, though selected documents require purchase for non-members; members gain exclusive early access to pre-publication proposals and drafts.[11][12] JEDEC functions as an independent incorporated association, having become a separate entity from the Electronic Industries Alliance (EIA) in 1999, with full autonomy following the EIA's dissolution in 2011.[13]Historical Development
Formation and Early History
The Joint Electron Tube Engineering Council (JETEC) was established in 1944 by the Radio Manufacturers Association (RMA) and the National Electronic Manufacturers Association (NEMA) to standardize electron tube specifications, including those used in memory applications, amid the demands of World War II for reliable radio and electronic equipment.[14][15] This organization, comprising primarily U.S.-based electronics manufacturers, aimed to replace fragmented proprietary systems with uniform standards to facilitate production and interoperability in the burgeoning radio industry.[14] The invention of the transistor at Bell Laboratories in 1947 marked a pivotal shift toward semiconductor technology, spurring rapid growth in solid-state devices and necessitating updated standardization efforts beyond vacuum tubes.[16] In response, JETEC transitioned and was renamed the Joint Electron Device Engineering Council (JEDEC) in 1958 under the Electronic Industries Association (EIA), reflecting the industry's pivot to transistors, diodes, and other discrete semiconductor components.[14][17] Early JEDEC activities focused on standardizing these discrete devices to ensure compatibility and reliability, particularly in defense applications where military needs drove adoption.[14] A key early achievement was the development of a unified part numbering system for electron devices in the late 1950s and 1960s, which eliminated proprietary designations and promoted interchangeability among manufacturers. This foundational work laid the groundwork for JEDEC's expansion into broader semiconductor standards in subsequent decades.[3]Major Milestones and Transitions
During the 1980s, JEDEC expanded its scope amid rapid growth in the integrated circuits sector, developing key standards for memory devices including early dynamic random-access memory (DRAM) specifications that supported the burgeoning personal computer industry.[18] The committee JC-42, responsible for motherboard and memory, published packaging standards for DRAM components and the emerging single in-line memory modules (SIMMs), enabling interchangeable upgrades and contributing to transistor density increases aligned with Moore's Law, as chip sales surged from $10 billion in 1979 to over $100 billion by the early 1990s.[18] A pivotal transition occurred in 1999, when JEDEC achieved independence from the EIA, incorporating as the JEDEC Solid State Technology Association to operate as a standalone entity with enhanced flexibility for global collaboration.[19] This name change underscored an evolution from a specialized engineering council embedded within a broader trade group to a dedicated technology association, fostering wider industry participation beyond U.S.-centric affiliations.[19] In the late 1990s and early 2000s, JEDEC faced challenges from patent disputes, notably with Rambus, leading to enhanced intellectual property policies to ensure fair standards development. The formal dissolution of the EIA in February 2011 further solidified JEDEC's autonomy, eliminating lingering alliance constraints and permitting more agile operations, including strengthened international partnerships that have since supported membership growth to over 360 companies worldwide (as of 2025).[20][21] A landmark achievement bridging the 1990s and 2000s was the release of the JESD79 standard in June 2000, which defined Double Data Rate Synchronous DRAM (DDR SDRAM) specifications for 64 Mb to 1 Gb devices, doubling effective data transfer rates over prior SDRAM and transforming PC memory performance by enabling higher bandwidth at lower costs.[22]Standards Creation Process
Policy Guidelines
JEDEC operates under the principle of open standards, ensuring that all its specifications are voluntary, publicly available without charge, and engineered to promote interoperability among products from diverse vendors in the microelectronics industry.[23] This approach fosters widespread adoption and innovation by eliminating barriers to implementation, allowing manufacturers to integrate JEDEC standards into their designs without mandatory compliance or licensing fees for the standards themselves.[1] Central to JEDEC's policy framework is its intellectual property regime, which mandates the disclosure of any known potentially essential patent claims by participating members during standards development.[24] Essential patents must be licensed on reasonable and non-discriminatory (RAND) terms to all implementers, with assurances binding successors in interest; failure to disclose or commit to RAND licensing can result in the withdrawal of the standard or the member's exclusion from further participation.[24] This policy safeguards against intellectual property hold-ups while encouraging broad collaboration. Standards approval at JEDEC requires a consensus-driven process, culminating in a 75% affirmative vote from the members of the Board of Directors, with each member company entitled to only one vote regardless of size to prevent dominance by any single entity.[25][1] JEDEC's scope is strictly limited to technical specifications for solid-state devices and related technologies, explicitly prohibiting discussions or inclusions related to commercial, marketing, or pricing matters to comply with antitrust laws and maintain focus on interoperability.[10][26] JEDEC standards are subject to periodic revisions to reflect technological advancements, with updates tracked through versioning in document identifiers such as the JESD prefix followed by a number and revision letter (e.g., JESD47I). This process ensures ongoing relevance without altering the core open and consensus-based principles.Committee Operations
JEDEC maintains a robust committee structure comprising over 50 standing committees and sub-working groups, each dedicated to specific aspects of semiconductor technology standardization.[27] For instance, JC-11 focuses on mechanical standardization and packaging outlines, while JC-42 addresses solid state memories, including subcommittees like JC-42.3 for DRAM parametrics.[28][29] These committees are led by elected chairpersons serving two-year terms and form task groups for targeted topics, ensuring focused development on emerging technologies.[30] The standards development workflow begins with proposal submission, where committee members present ideas and motions during meetings, often assigned item numbers for tracking.[30] These proposals undergo deliberation, requiring a second for a motion before ballot voting, typically needing a two-thirds majority via electronic voting systems.[30] Successful ballots advance to board-level review by the JEDEC Board of Directors, followed by a public review period for broader input, culminating in final publication.[31] The entire process generally spans 1-3 years per standard, as exemplified by the SDRAM specification, which took approximately two years from initial proposals in 1991 to finalization in 1993.[30] Participation in committee operations is primarily reserved for JEDEC member companies, who propose changes through formal documents and motions during quarterly meetings.[1] Non-members may attend as guests or contribute comments during the public review phase but lack voting rights.[31] This structure fosters collaborative input from over 3,000 volunteers representing more than 380 member companies, as of 2025.[32] Approved standards are published as JESD documents, available through the JEDEC website. Most are free to download after free registration, while selected standards are available only to members or for a fee to non-members to support detailed implementation.[33][34] The registry of standards, including updates to device outlines and specifications, receives annual revisions to reflect ongoing industry needs.[35] To facilitate operations, JEDEC employs online portals, such as the members-only area, for secure document sharing and proposal management.[31] Following 2020, virtual meetings via platforms like Webex have become integral, enabling continued collaboration amid global disruptions while maintaining in-person sessions for complex discussions.[36]Key Standard Categories
Device Part Numbering System
The JEDEC device part numbering system originated in the 1950s under the EIA-370 standard, established by the Electronic Industries Association (EIA) to provide a uniform identification scheme for early semiconductor devices such as transistors and diodes.[37] This initial framework addressed the proliferation of proprietary naming conventions that hindered interoperability among manufacturers, focusing primarily on discrete components.[38] In February 1982, JEDEC updated and expanded the system through JESD370B, which superseded EIA-370 and introduced enhancements like a new letter symbol "C" for chip-level designations.[37] This revision broadened applicability to integrated circuits at the chip level, accommodating the growing complexity of semiconductor technology.[37] The core structure of JESD370B uses alphanumeric prefixes to denote device type and performance grade, followed by sequential numeric identifiers and optional suffixes for variants like temperature range or packaging.[35] For instance, the prefix 1N indicates diodes (typically two-lead devices), while 2N signifies transistors (three-lead devices), with the system deliberately avoiding manufacturer-specific codes to ensure neutrality.[38] Registration occurs through JEDEC's type designation process, where manufacturers submit device data for assignment, promoting standardized global communication.[35] Key advantages of the system include enabling seamless global sourcing, minimizing procurement errors, and facilitating cross-manufacturer compatibility, as it eliminates ambiguities in device identification.[39] The system has supported the registration of numerous unique device numbers, reflecting its enduring role in the industry.[35] The standard undergoes periodic revisions to incorporate emerging device classes; for example, updates have added support for optoelectronics using prefixes like 5Nxxxx for photo-sensitive devices.[38] These numbered designations are briefly referenced in JEDEC reliability testing protocols and linked to corresponding packaging outlines for complete device specification.[35]Testing and Reliability Protocols
JEDEC's JESD22 series establishes standardized environmental stress tests for evaluating the reliability of solid-state devices, including conditions such as temperature extremes, humidity, and mechanical stresses to assess potential failure mechanisms.[40] For instance, JESD22-A104 outlines temperature cycling protocols using single-, dual-, or triple-chamber methods in air or gaseous environments, subjecting components to rapid thermal transitions—typically 1 to 3 cycles per hour—to qualify devices and subassemblies for operational durability.[41] Similarly, JESD22-A108 defines high-temperature operating life testing, applying bias conditions at elevated temperatures (often 125°C or higher for 1000 hours) to accelerate and observe time-dependent degradation in solid-state devices under simulated use scenarios.[42] Electrostatic discharge (ESD) protocols within JEDEC focus on protecting sensitive devices during handling and manufacturing, with JESD625 specifying comprehensive requirements for ESD control programs applicable to devices vulnerable to discharges exceeding 100 volts in the human body model (HBM).[43] This includes guidelines for grounding, packaging, and personnel practices to minimize risks. Complementing this, JESD/AE-105 standardizes the ESD susceptibility symbol for marking devices and related materials, ensuring clear identification of electrostatic-sensitive components.[44] For ESD testing, the JS-001 standard details the HBM methodology, simulating human-induced discharges with peak currents up to those corresponding to 2 kV, enabling repeatable classification of device robustness (e.g., Class 2 for 1500–2000 V tolerance).[45] Reliability assessments in JEDEC protocols incorporate acceleration factors to extrapolate failure rates from accelerated tests to normal operating conditions, facilitating mean time between failures (MTBF) calculations for semiconductors. These factors quantify how stress levels, particularly thermal, hasten failure mechanisms, with MTBF derived inversely from failure rates adjusted via such models. Central to thermal reliability is the Arrhenius equation, which models temperature-dependent acceleration:
Here, $ AF $ is the acceleration factor, $ E_a $ the activation energy (typically 0.3–1.0 eV for common mechanisms), $ k $ Boltzmann's constant (8.617 × 10^{-5} eV/K), and $ T_{use} $, $ T_{stress} $ the use and stress temperatures in Kelvin, respectively; this enables prediction of field reliability from lab data.[46][47]
JESD47 provides a stress-test-driven framework for qualifying integrated circuits, mandating a suite of environmental and electrical stresses to verify compliance with reliability targets before market release. This includes tests for unbiased high-temperature storage, temperature-humidity bias (e.g., 85°C/85% RH for 96–1000 hours to induce corrosion or electromigration), and mechanical vibration (e.g., random vibration up to 2000 Hz to simulate shipping or operational shocks).[48] These protocols ensure devices withstand combined stresses without exceeding specified failure rates, often integrating with JESD22 methods for detailed execution.
In response to the lead-free transition, JESD22-A121 addresses board-level reliability challenges in Pb-free assemblies by standardizing tests for tin whisker growth on finishes like pure Sn or Sn alloys, which can cause short circuits in high-density electronics. The method involves accelerated aging (e.g., 4000 hours at 60°C/93% RH) followed by microscopic measurement of whisker lengths (no growth exceeding 40 μm permitted), mitigating risks from the shift away from SnPb solders since the early 2000s.[49] These protocols apply broadly to JEDEC-numbered semiconductor parts, including memory devices, to ensure consistent qualification across product families.