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Parallel ATA
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Two ATA motherboard sockets above, with an ATA connector below | |||
| Type | Internal storage device connector | ||
|---|---|---|---|
| Production history | |||
| Designer |
Western Digital and Compaq, subsequently enhanced by many others | ||
| Designed | 1986 | ||
| Superseded by | Serial ATA (2003) | ||
| General specifications | |||
| Hot pluggable | No | ||
| External | No | ||
| Cable | 40 or 80 conductor ribbon cable | ||
| Pins | 40 | ||
| Data | |||
| Width | 16 bits | ||
| Bitrate |
Half-duplex: 8.3 MB/s per ATA channel originally later 33, 66, 100 and 133 MB/s per ATA channel | ||
| Max. devices | Two[a] | ||
| Protocol | Parallel | ||
| Pinout | |||
|
| |||
| Pin 1 | Reset | ||
| Pin 2 | Ground | ||
| Pin 3 | Data 7 | ||
| Pin 4 | Data 8 | ||
| Pin 5 | Data 6 | ||
| Pin 6 | Data 9 | ||
| Pin 7 | Data 5 | ||
| Pin 8 | Data 10 | ||
| Pin 9 | Data 4 | ||
| Pin 10 | Data 11 | ||
| Pin 11 | Data 3 | ||
| Pin 12 | Data 12 | ||
| Pin 13 | Data 2 | ||
| Pin 14 | Data 13 | ||
| Pin 15 | Data 1 | ||
| Pin 16 | Data 14 | ||
| Pin 17 | Data 0 | ||
| Pin 18 | Data 15 | ||
| Pin 19 | Ground | ||
| Pin 20 | Key or VCC_in | ||
| Pin 21 | DDRQ | ||
| Pin 22 | Ground | ||
| Pin 23 | I/O write | ||
| Pin 24 | Ground | ||
| Pin 25 | I/O read | ||
| Pin 26 | Ground | ||
| Pin 27 | IOCHRDY | ||
| Pin 28 | Cable select | ||
| Pin 29 | DDACK | ||
| Pin 30 | Ground | ||
| Pin 31 | IRQ | ||
| Pin 32 | No connect | ||
| Pin 33 | Addr 1 | ||
| Pin 34 | GPIO_DMA66_Detect | ||
| Pin 35 | Addr 0 | ||
| Pin 36 | Addr 2 | ||
| Pin 37 | Chip select 1P | ||
| Pin 38 | Chip select 3P | ||
| Pin 39 | Activity | ||
| Pin 40 | Ground | ||
Parallel ATA (PATA), originally AT Attachment, also known as Integrated Drive Electronics (IDE), is a standard interface designed for IBM PC-compatible computers. It was first developed by Western Digital and Compaq in 1986 for compatible hard drives and CD or DVD drives. The connection is used for computer storage such as hard disk, floppy disk,[citation needed][not verified in body][1][2][3][improper synthesis?] optical disk, and tape.
The standard is maintained by the X3/INCITS committee.[4] It uses the underlying AT Attachment (ATA) and AT Attachment Packet Interface (ATAPI) standards.
The Parallel ATA standard is the result of a long history of incremental technical development, which began with the original AT Attachment interface, developed for use in early PC AT equipment. The ATA interface itself evolved in several stages from Western Digital's original Integrated Drive Electronics (IDE) interface. As a result, many near-synonyms for ATA/ATAPI and its previous incarnations are still in common informal use, in particular Extended IDE (EIDE) and Ultra ATA (UATA). After the introduction of SATA in 2003, the original ATA was renamed to Parallel ATA, or PATA for short.
Parallel ATA cables have a maximum allowable length of 18 in (457 mm).[5][6] Because of this limit, the technology normally appears as an internal computer storage interface. For many years, ATA provided the most common and the least expensive interface for this application. It has largely been replaced by SATA in newer systems.
History and terminology
[edit]The standard was originally conceived as the "AT Bus Attachment", officially called "AT Attachment" and abbreviated "ATA"[7][8] because its primary feature was a direct connection to the 16-bit ISA bus introduced with the IBM PC/AT.[9] The original ATA specifications published by the standards committees use the name "AT Attachment".[10][11][12] The "AT" in the IBM PC/AT referred to "Advanced Technology" so ATA has also been referred to as "Advanced Technology Attachment".[13][7][14][15] When a newer Serial ATA (SATA) was introduced in 2003, the original ATA was renamed to Parallel ATA, or PATA for short.[16]
Physical ATA interfaces became a standard component in PCs, initially on host bus adapters, sometimes on a sound card but ultimately as two physical interfaces embedded in a Southbridge chip on a motherboard. Called the "primary" and "secondary" ATA interfaces, they were assigned to I/O base addresses 0x1F0-0x1F7 and 0x170-0x177 on ISA bus systems. They were replaced by SATA interfaces.
IDE and ATA-1
[edit]
The first version of what is now called the ATA/ATAPI interface was developed by Western Digital under the name Integrated Drive Electronics (IDE). Together with Compaq (the initial customer), they worked with various disk drive manufacturers to develop and ship early products with the goal of remaining software compatible with the existing IBM PC hard drive interface.[17] The first such drives appeared internally in Compaq PCs in 1986[18][19] and were first separately offered by Conner Peripherals as the CP342 in June 1987.[20]
The term Integrated Drive Electronics refers to the drive controller being integrated into the drive, as opposed to a separate controller situated at the other side of the connection cable to the drive. On an IBM PC compatible, CP/M machine, or similar, this was typically a card installed on a motherboard. The interface cards used to connect a parallel ATA drive to, for example, an ISA Slot, are not drive controllers: they are merely bridges between the host bus and the ATA interface. Since the original ATA interface is essentially just a 16-bit ISA bus, the bridge was especially simple in case of an ATA connector being located on an ISA interface card. The integrated controller presented the drive to the host computer as an array of 512-byte blocks with a relatively simple command interface. This relieved the mainboard and interface cards in the host computer of the chores of stepping the disk head arm, moving the head arm in and out, and so on, as had to be done with earlier ST-506 and ESDI hard drives. All of these low-level details of the mechanical operation of the drive were now handled by the controller on the drive itself. This also eliminated the need to design a single controller that could handle many different types of drives, since the controller could be unique for the drive. The host need only to ask for a particular sector, or block, to be read or written, and either accept the data from the drive or send the data to it.
The interface used by these drives was standardized in 1994 as ANSI standard X3.221-1994, AT Attachment Interface for Disk Drives. After later versions of the standard were developed, this became known as "ATA-1".[21][22]
A short-lived, seldom-used implementation of ATA was created for the IBM XT and similar machines that used the 8-bit version of the ISA bus. It has been referred to as "XT-IDE", "XTA" or "XT Attachment".[23]
EIDE and ATA-2
[edit]In 1994, about the same time that the ATA-1 standard was adopted, Western Digital introduced drives under a newer name, Enhanced IDE (EIDE). These included most of the features of the forthcoming ATA-2 specification and several additional enhancements. Other manufacturers introduced their own variations of ATA-1 such as "Fast ATA" and "Fast ATA-2".
The new version of the ANSI standard, AT Attachment Interface with Extensions ATA-2 (X3.279-1996), was approved in 1996. It included most of the features of the manufacturer-specific variants.[24][25]
ATA-2 also was the first to note that devices other than hard drives could be attached to the interface:
3.1.7 Device: Device is a storage peripheral. Traditionally, a device on the ATA interface has been a hard disk drive, but any form of storage device may be placed on the ATA interface provided it adheres to this standard.
— AT Attachment Interface with Extensions (ATA-2), page 2[25]
ATAPI
[edit]ATA was originally designed for, and worked only with, hard disk drives and devices that could emulate them. The introduction of ATAPI (ATA Packet Interface) by the Small Form Factor Committee (SFF) allowed ATA to be used for a variety of other devices that require functions beyond those necessary for hard disk drives. For example, any removable media device needs a "media eject" command, and a way for the host to determine whether the media is present, and these were not provided in the ATA protocol.
ATAPI is a protocol allowing the ATA interface to carry SCSI commands and responses; therefore, all ATAPI devices are actually "speaking SCSI" other than at the electrical interface. The SCSI commands and responses are embedded in "packets" (hence "ATA Packet Interface") for transmission on the ATA cable. This allows any device class for which a SCSI command set has been defined to be interfaced via ATA/ATAPI.
ATAPI devices are also "speaking ATA", as the ATA physical interface and protocol are still being used to send the packets. On the other hand, ATA hard drives and solid state drives do not use ATAPI.
ATAPI devices include CD-ROM and DVD-ROM drives, tape drives, and high-capacity floppy drives such as the Zip drive and SuperDisk drive. Some early ATAPI devices were simply SCSI devices with an ATA/ATAPI to SCSI protocol converter added on.[citation needed]
The SCSI commands and responses used by each class of ATAPI device (CD-ROM, tape, etc.) are described in other documents or specifications specific to those device classes and are not within ATA/ATAPI or the T13 committee's purview. One commonly used set is defined in the MMC SCSI command set.
ATAPI was adopted as part of ATA in INCITS 317-1998, AT Attachment with Packet Interface Extension (ATA/ATAPI-4).[26][27][28]
UDMA and ATA-4
[edit]The ATA/ATAPI-4 standard also introduced several "Ultra DMA" transfer modes. These initially supported speeds from 16 to 33 MB/s. In later versions, faster Ultra DMA modes were added, requiring new 80-wire cables to reduce crosstalk. The latest versions of Parallel ATA support up to 133 MB/s.
Ultra ATA
[edit]Ultra ATA, abbreviated UATA, is a designation that has been primarily used by Western Digital for different speed enhancements to the ATA/ATAPI standards. For example, in 2000 Western Digital published a document describing "Ultra ATA/100", which brought performance improvements for the then-current ATA/ATAPI-5 standard by improving maximum speed of the Parallel ATA interface from 66 to 100 MB/s.[29] Most of Western Digital's changes, along with others, were included in the ATA/ATAPI-6 standard (2002).
x86 BIOS size limitations
[edit]Initially, the size of an ATA drive was stored in the system x86 BIOS using a type number (1 through 45) that predefined the C/H/S parameters[30] and also often the landing zone, in which the drive heads are parked while not in use. Later, a "user definable" format[30] called C/H/S or cylinders, heads, sectors was made available. These numbers were important for the earlier ST-506 interface, but were generally meaningless for ATA—the CHS parameters for later ATA large drives often specified impossibly high numbers of heads or sectors that did not actually define the internal physical layout of the drive at all. From the start, and up to ATA-2, every user had to specify explicitly how large every attached drive was. From ATA-2 on, an "identify drive" command was implemented that can be sent and which will return all drive parameters.
Owing to a lack of foresight by motherboard manufacturers, the system BIOS was often hobbled by artificial C/H/S size limitations due to the manufacturer assuming certain values would never exceed a particular numerical maximum.
The first of these BIOS limits occurred when ATA drives reached sizes in excess of 504 MiB, because some motherboard BIOSes would not allow C/H/S values above 1024 cylinders, 16 heads, and 63 sectors. Multiplied by 512 bytes per sector, this totals 528482304 bytes which, divided by 1048576 bytes per MiB, equals 504 MiB (528 MB).
The second of these BIOS limitations occurred at 1024 cylinders, 256 heads, and 63 sectors, and a problem in MS-DOS limited the number of heads to 255. This totals to 8422686720 bytes (8032.5 MiB), commonly referred to as the 8.4 gigabyte barrier. This is again a limit imposed by x86 BIOSes, and not a limit imposed by the ATA interface.
It was eventually determined that these size limitations could be overridden with a small program loaded at startup from a hard drive's boot sector. Some hard drive manufacturers, such as Western Digital, started including these override utilities with large hard drives to help overcome these problems. However, if the computer was booted in some other manner without loading the special utility, the invalid BIOS settings would be used and the drive could either be inaccessible or appear to the operating system to be damaged.
Later, an extension to the x86 BIOS disk services called the "Enhanced Disk Drive" (EDD) was made available, which makes it possible to address drives as large as 264 sectors.[31]
Interface size limitations
[edit]The first drive interface used 22-bit addressing mode which resulted in a maximum drive capacity of two gigabytes. Later, the first formalized ATA specification used a 28-bit addressing mode through LBA28, allowing for the addressing of 228 (268435456) sectors (blocks) of 512 bytes each, resulting in a maximum capacity of 128 GiB (137 GB).
ATA-6 introduced 48-bit addressing, increasing the limit to 128 PiB (144 PB). As a consequence, any ATA drive of capacity larger than about 137 GB must be an ATA-6 or later drive. Connecting such a drive to a host with an ATA-5 or earlier interface will limit the usable capacity to the maximum of the interface.
Some operating systems, including Windows XP pre-SP1, and Windows 2000 pre-SP3, disable LBA48 by default, requiring the user to take extra steps to use the entire capacity of an ATA drive larger than about 137 gigabytes.[32]
Older operating systems, such as Windows 98, do not support 48-bit LBA at all. However, members of the third-party group MSFN[33] have modified the Windows 98 disk drivers to add unofficial support for 48-bit LBA to Windows 95 OSR2, Windows 98, Windows 98 SE and Windows ME.
Some 16-bit and 32-bit operating systems supporting LBA48 may still not support disks larger than 2 TiB due to using 32-bit arithmetic only; a limitation also applying to many boot sectors.
Primacy and obsolescence
[edit]Parallel ATA (then simply called ATA or IDE) became the primary storage device interface for PCs soon after its introduction. In some systems, a third and fourth motherboard interface was provided, allowing up to eight ATA devices to be attached to the motherboard. Often, these additional connectors were implemented by inexpensive RAID controllers.
Soon after the introduction of Serial ATA (SATA) in 2003, use of Parallel ATA declined. Some PCs and laptops of the era have a SATA hard disk and an optical drive connected to PATA.
As of 2007, some PC chipsets, for example the Intel ICH10, had removed support for PATA. Motherboard vendors still wishing to offer Parallel ATA with those chipsets must include an additional interface chip. In more recent computers, the Parallel ATA interface is rarely used even if present, as four or more Serial ATA connectors are usually provided on the motherboard and SATA devices of all types are common.
With Western Digital's withdrawal from the PATA market, hard disk drives with the PATA interface were no longer in production after December 2013 for other than specialty applications.[34]
Interface
[edit]Parallel ATA cables transfer data 16 bits at a time. The traditional cable uses 40-pin female insulation displacement connectors (IDC) attached to a 40- or 80-conductor ribbon cable. Each cable has two or three connectors, one of which plugs into a host adapter interfacing with the rest of the computer system. The remaining connector(s) plug into storage devices, most commonly hard disk drives or optical drives. Each connector has 39 physical pins arranged into two rows (2.54 mm, 1⁄10-inch pitch), with a gap or key at pin 20. Earlier connectors may not have that gap, with all 40 pins available. Thus, later cables with the gap filled in are incompatible with earlier connectors, although earlier cables are compatible with later connectors.
Round parallel ATA cables (as opposed to ribbon cables) were eventually made available for 'case modders' for cosmetic reasons, as well as claims of improved computer cooling and were easier to handle; however, only ribbon cables are supported by the ATA specifications.
- Pin 20
- In the ATA standard, pin 20 is defined as a mechanical key and is not used. The pin's socket on the female connector is often blocked, requiring pin 20 to be omitted from the male cable or drive connector; it is thus impossible to plug it in the wrong way round. However, some flash memory drives can use pin 20 as VCC_in to power the drive without requiring a special power cable; this feature can only be used if the equipment supports this use of pin 20.[35]
- Pin 28
- Pin 28 of the gray (slave/middle) connector of an 80-conductor cable is not attached to any conductor of the cable. It is attached normally on the black (master drive end) and blue (motherboard end) connectors. This enables cable select functionality.
- Pin 34
- Pin 34 is connected to ground inside the blue connector of an 80-conductor cable but not attached to any conductor of the cable, allowing for detection of such a cable. It is attached normally on the gray and black connectors.[36]
44-pin variant
[edit]A 44-pin variant PATA connector is used for 2.5 inch drives inside laptops. The pins are closer together (2.0 mm pitch) and the connector is physically smaller than the 40-pin connector. The extra pins carry power.
80-conductor variant
[edit]

ATA's cables have had 40 conductors for most of its history (44 conductors for the smaller form-factor version used for 2.5" drives—the extra four for power), but an 80-conductor version appeared with the introduction of the UDMA/66 mode. All of the additional conductors in the new cable are grounds, interleaved with the signal conductors to reduce the effects of capacitive coupling between neighboring signal conductors, reducing crosstalk. Capacitive coupling is more of a problem at higher transfer rates, and this change was necessary to enable the 66 megabytes per second (MB/s) transfer rate of UDMA4 to work reliably. The faster UDMA5 and UDMA6 modes also require 80-conductor cables.
Though the number of conductors doubled, the number of connector pins and the pinout remain the same as 40-conductor cables, and the external appearance of the connectors is identical. Internally, the connectors are different; the connectors for the 80-conductor cable connect a larger number of ground conductors to the ground pins, while the connectors for the 40-conductor cable connect ground conductors to ground pins one-to-one. 80-conductor cables usually come with three differently colored connectors (blue, black, and gray for controller, master drive, and slave drive respectively) as opposed to uniformly colored 40-conductor cable's connectors (commonly all gray). The gray connector on 80-conductor cables has pin 28 CSEL not connected, making it the slave position for drives configured cable select.
Multiple devices on a cable
[edit]If two devices are attached to a single cable, one must be designated as Device 0 (in the past, commonly designated master) and the other as Device 1 (in the past, commonly designated as slave).[37] This distinction is necessary to allow both drives to share the cable without conflict. The Device 0 drive is the drive that usually appears "first" to the computer's BIOS and/or operating system. In most personal computers the drives are often designated as "C:" for the Device 0 and "D:" for the Device 1 referring to one active primary partitions on each.
The mode that a device must use is often set by a jumper setting on the device itself, which must be manually set to Device 0 (Master) or Device 1 (Slave). If there is a single device on a cable, it should be configured as Device 0. However, some certain era drives have a special setting called Single for this configuration (Western Digital, in particular). Also, depending on the hardware and software available, a Single drive on a cable will often work reliably even though configured as the Device 1 drive (most often seen where an optical drive is the only device on the secondary ATA interface).
The words primary and secondary typically refers to the two IDE cables, which can have two drives each (primary master, primary slave, secondary master, secondary slave).
There are many debates about how much a slow device can impact the performance of a faster device on the same cable. On early ATA host adapters, both devices' data transfers can be constrained to the speed of the slower device, if two devices of different speed capabilities are on the same cable. For all modern ATA host adapters, this is not true, as modern ATA host adapters support independent device timing. This allows each device on the cable to transfer data at its own best speed. Even with earlier adapters without independent timing, this effect applies only to the data transfer phase of a read or write operation.[38] This is caused by the omission of both overlapped and queued feature sets from most parallel ATA products. Only one device on a cable can perform a read or write operation at one time; therefore, a fast device on the same cable as a slow device under heavy use will find it has to wait for the slow device to complete its task first. However, most modern devices will report write operations as complete once the data is stored in their onboard cache memory, before the data is written to the (slow) magnetic storage. This allows commands to be sent to the other device on the cable, reducing the impact of the "one operation at a time" limit. The impact of this on a system's performance depends on the application. For example, when copying data from an optical drive to a hard drive (such as during software installation), this effect probably will not matter. Such jobs are necessarily limited by the speed of the optical drive no matter where it is. But if the hard drive in question is also expected to provide good throughput for other tasks at the same time, it probably should not be on the same cable as the optical drive.
Cable select
[edit]A drive mode called cable select was described as optional in ATA-1 and has come into fairly widespread use with ATA-5 and later. A drive set to "cable select" automatically configures itself as Device 0 or Device 1, according to its position on the cable. Cable select is controlled by pin 28. The host adapter grounds this pin; if a device sees that the pin is grounded, it becomes the Device 0 (master) device; if it sees that pin 28 is open, the device becomes the Device 1 (slave) device.
This setting is usually chosen by a jumper setting on the drive called "cable select", usually marked CS, which is separate from the Device 0/1 setting.
If two drives are configured as Device 0 and Device 1 manually, this configuration does not need to correspond to their position on the cable. Pin 28 is only used to let the drives know their position on the cable; it is not used by the host when communicating with the drives. In other words, the manual master/slave setting using jumpers on the drives takes precedence and allows them to be freely placed on either connector of the ribbon cable.
With the 40-conductor cable, it was very common to implement cable select by simply cutting the pin 28 wire between the two device connectors; putting the slave Device 1 device at the end of the cable, and the master Device 0 on the middle connector. This arrangement eventually was standardized in later versions. However, it had one drawback: if there is just one master device on a 2-drive cable, using the middle connector, this results in an unused stub of cable, which is undesirable for physical convenience and electrical reasons. The stub causes signal reflections, particularly at higher transfer rates.
Starting with the 80-conductor cable defined for use in ATAPI5/UDMA4, the master Device 0 device goes at the far-from-the-host end of the 18-inch (460 mm) cable on the black connector, the slave Device 1 goes on the grey middle connector, and the blue connector goes to the host (e.g. motherboard IDE connector, or IDE card). So, if there is only one (Device 0) device on a two-drive cable, using the black connector, there is no cable stub to cause reflections (the unused connector is now in the middle of the ribbon). Also, cable select is now implemented in the grey middle device connector, usually simply by omitting the pin 28 contact from the connector body.
Serialized, overlapped, and queued operations
[edit]The parallel ATA protocols up through ATA-3 require that once a command has been given on an ATA interface, it must complete before any subsequent command may be given. Operations on the devices must be serialized—with only one operation in progress at a time—with respect to the ATA host interface. A useful mental model is that the host ATA interface is busy with the first request for its entire duration, and therefore can not be told about another request until the first one is complete. The function of serializing requests to the interface is usually performed by a device driver in the host operating system.
The ATA-4 and subsequent versions of the specification have included an "overlapped feature set" and a "queued feature set" as optional features, both being given the name "Tagged Command Queuing" (TCQ), a reference to a set of features from SCSI which the ATA version attempts to emulate. However, support for these is extremely rare in actual parallel ATA products and device drivers because these feature sets were implemented in such a way as to maintain software compatibility with its heritage as originally an extension of the ISA bus. This implementation resulted in excessive CPU utilization which largely negated the advantages of command queuing. By contrast, overlapped and queued operations have been common in other storage buses; in particular, SCSI's version of tagged command queuing had no need to be compatible with APIs designed for ISA, allowing it to attain high performance with low overhead on buses which supported first party DMA like PCI. This has long been seen as a major advantage of SCSI.
The Serial ATA standard has supported native command queueing (NCQ) since its first release, but it is an optional feature for both host adapters and target devices. Many obsolete PC motherboards do not support NCQ, but modern SATA hard disk drives and SATA solid-state drives usually support NCQ, which is not the case for removable (CD/DVD) drives because the ATAPI command set used to control them prohibits queued operations.
HDD passwords and security
[edit]ATA devices may support an optional security feature which is defined in an ATA specification, and thus not specific to any brand or device. The security feature can be enabled and disabled by sending special ATA commands to the drive. If a device is locked, it will refuse all access until it is unlocked. A device can have two passwords: A User Password and a Master Password; either or both may be set. There is a Master Password identifier feature which, if supported and used, can identify the current Master Password (without disclosing it). The master password, if set, can used by the administrator to reset user password, if the end user forgot the user password. On some laptops and some business computers, their BIOS can control the ATA passwords.[39]
A device can be locked in two modes: High security mode or Maximum security mode. Bit 8 in word 128 of the IDENTIFY response shows which mode the disk is in: 0 = High, 1 = Maximum. In High security mode, the device can be unlocked with either the User or Master password, using the "SECURITY UNLOCK DEVICE" ATA command. There is an attempt limit, normally set to 5, after which the disk must be power cycled or hard-reset before unlocking can be attempted again. Also in High security mode, the SECURITY ERASE UNIT command can be used with either the User or Master password. In Maximum security mode, the device can be unlocked only with the User password. If the User password is not available, the only remaining way to get at least the bare hardware back to a usable state is to issue the SECURITY ERASE PREPARE command, immediately followed by SECURITY ERASE UNIT. In Maximum security mode, the SECURITY ERASE UNIT command requires the Master password and will completely erase all data on the disk. Word 89 in the IDENTIFY response indicates how long the operation will take.[40] While the ATA lock is intended to be impossible to defeat without a valid password, there are purported workarounds to unlock a device.[citation needed]
For NVMe drives, the security features, including lock passwords, were defined in the OPAL standard.[41]
For sanitizing entire disks, the built-in Secure Erase command is effective when implemented correctly.[42] There have been a few reported instances of failures to erase some or all data.[43][44][42] On some laptops and some business computers, their BIOS can utilize Secure Erase to erase all data of the disk.
External parallel ATA devices
[edit]
Due to a short cable length specification and shielding issues it is extremely uncommon to find external PATA devices that directly use PATA for connection to a computer. A device connected externally needs additional cable length to form a U-shaped bend so that the external device may be placed alongside, or on top of the computer case, and the standard cable length is too short to permit this. For ease of reach from motherboard to device, the connectors tend to be positioned towards the front edge of motherboards, for connection to devices protruding from the front of the computer case. This front-edge position makes extension out the back to an external device even more difficult. Ribbon cables are poorly shielded, and the standard relies upon the cabling to be installed inside a shielded computer case to meet RF emissions limits.
External hard disk drives or optical disk drives that have an internal PATA interface, use some other interface technology to bridge the distance between the external device and the computer. USB is the most common external interface, followed by Firewire. A bridge chip inside the external devices converts from the USB interface to PATA, and typically only supports a single external device without cable select or master/slave.
Specifications
[edit]The following table shows the names of the versions of the ATA standards and the transfer modes and rates supported by each. Note that the transfer rate for each mode (for example, 66.7 MB/s for UDMA4, commonly called "Ultra-DMA 66", defined by ATA-5) gives its maximum theoretical transfer rate on the cable. This is simply two bytes multiplied by the effective clock rate, and presumes that every clock cycle is used to transfer end-user data. In practice, of course, protocol overhead reduces this value.
Congestion on the host bus to which the ATA adapter is attached may also limit the maximum burst transfer rate. For example, the maximum data transfer rate for conventional PCI bus is 133 MB/s, and this is shared among all active devices on the bus.
In addition, no ATA hard drives existed in 2005 that were capable of measured sustained transfer rates of above 80 MB/s. Furthermore, sustained transfer rate tests do not give realistic throughput expectations for most workloads: They use I/O loads specifically designed to encounter almost no delays from seek time or rotational latency. Hard drive performance under most workloads is limited first and second by those two factors; the transfer rate on the bus is a distant third in importance. Therefore, transfer speed limits above 66 MB/s really affect performance only when the hard drive can satisfy all I/O requests by reading from its internal cache—a very unusual situation, especially considering that such data is usually already buffered by the operating system.
As of July 2021[update], mechanical hard disk drives can transfer data at up to 524 MB/s,[45] which is far beyond the capabilities of the PATA/133 specification. High-performance solid state drives can transfer data at up to 7000–7500 MB/s.[46]
Only the Ultra DMA modes use CRC to detect errors in data transfer between the controller and drive. This is a 16-bit CRC, and it is used for data blocks only. Transmission of command and status blocks do not use the fast signaling methods that would necessitate CRC. For comparison, in Serial ATA, 32-bit CRC is used for both commands and data.[47]
Features introduced with each ATA revision
[edit]| Standard | Other names | New transfer modes | Maximum disk size (512 byte sector) |
Other significant changes | ANSI reference |
|---|---|---|---|---|---|
| IDE (pre-ATA) | IDE | PIO 0 | 2 GiB (2.1 GB) | 22-bit logical block addressing (LBA) |
ANSI X379.2/90-143 ATA (AT Attachment) draft proposal August 15, 1990 |
| ATA-1 | ATA, IDE | PIO 0, 1, 2 Single-word DMA 0, 1, 2 Multi-word DMA 0 |
128 GiB (137 GB) | 28-bit logical block addressing (LBA) | X3.221-1994 Archived 2012-03-21 at the Wayback Machine (obsolete since 1999) |
| ATA-2 | EIDE, Fast ATA, Fast IDE, Ultra ATA | PIO 3, 4 Multi-word DMA 1, 2 |
44-pin Small Form Factor connector, for ≤2.5″ drives, and PCMCIA connector. Identify drive command.[48] Plug and play support. | X3.279-1996 Archived 2011-07-28 at the Wayback Machine (obsolete since 2001) | |
| ATA-3 | EIDE | Single-word DMA modes dropped[49] | S.M.A.R.T., Security | X3.298-1997 Archived 2014-07-22 at the Wayback Machine (obsolete since 2002) | |
| ATA/ATAPI-4 | ATA-4, Ultra ATA/33 | Ultra DMA 0, 1, 2, also known as UDMA/33 |
AT Attachment Packet Interface (ATAPI) (support for CD-ROM, tape drives etc.), Optional overlapped and queued command set features, Host Protected Area (HPA), CompactFlash Association (CFA) feature set for solid state drives | NCITS 317-1998 Archived 2014-07-22 at the Wayback Machine | |
| ATA/ATAPI-5 | ATA-5, Ultra ATA/66 | Ultra DMA 3, 4, also known as UDMA/66 |
80-wire cables; CompactFlash connector | NCITS 340-2000 Archived 2014-07-22 at the Wayback Machine | |
| ATA/ATAPI-6 | ATA-6, Ultra ATA/100 | UDMA 5, also known as UDMA/100 |
128 PiB (144 PB) | 48-bit LBA, Device Configuration Overlay (DCO), Automatic Acoustic Management (AAM) CHS method of addressing data obsolete |
NCITS 361-2002 Archived 2011-09-15 at the Wayback Machine |
| ATA/ATAPI-7 | ATA-7, Ultra ATA/133 | UDMA 6, also known as UDMA/133 SATA/150 |
SATA 1.0, Streaming feature set, long logical/physical sector feature set for non-packet devices | INCITS 397-2005 (vol 1) Archived 2020-08-06 at the Wayback Machine INCITS 397-2005 (vol 2) Archived 2020-06-16 at the Wayback Machine INCITS 397-2005 (vol 3) Archived 2020-06-15 at the Wayback Machine | |
| ATA/ATAPI-8 | ATA-8 | SATA/300 SATA/600 |
Hybrid drive featuring non-volatile cache to speed up critical OS files | INCITS 452-2008 Archived 2014-10-10 at the Wayback Machine | |
| ACS-2 | — | — | Data Set Management, Extended Power Conditions, CFast, additional stats., etc. | INCITS 482-2012 Archived 2016-07-01 at the Wayback Machine | |
| ACS-3 | — | — | |||
| ACS-4 | — | — | Zoned ATA Command |
Speed of defined transfer modes
[edit]| Mode | # | Maximum transfer rate(MB/s) |
Cycle time |
|---|---|---|---|
| PIO | 0 | 3.3 | 600 ns |
| 1 | 5.2 | 383 ns | |
| 2 | 8.3 | 240 ns | |
| 3 | 11.1 | 180 ns | |
| 4 | 16.7 | 120 ns | |
| Single-word DMA | 0 | 2.1 | 960 ns |
| 1 | 4.2 | 480 ns | |
| 2 | 8.3 | 240 ns | |
| Multi-word DMA | 0 | 4.2 | 480 ns |
| 1 | 13.3 | 150 ns | |
| 2 | 16.7 | 120 ns | |
| 3[50] | 20 | 100 ns | |
| 4[50] | 25 | 80 ns | |
| Ultra DMA | 0 | 16.7 | 240 ns ÷ 2 |
| 1 | 25.0 | 160 ns ÷ 2 | |
| 2 (Ultra ATA/33) | 33.3 | 120 ns ÷ 2 | |
| 3 | 44.4 | 90 ns ÷ 2 | |
| 4 (Ultra ATA/66) | 66.7 | 60 ns ÷ 2 | |
| 5 (Ultra ATA/100) | 100 | 40 ns ÷ 2 | |
| 6 (Ultra ATA/133) | 133 | 30 ns ÷ 2 | |
| 7 (Ultra ATA/167)[51] | 167 | 24 ns ÷ 2 |
Related standards, features, and proposals
[edit]ATAPI Removable Media Device (ARMD)
[edit]ATAPI devices with removable media, other than CD and DVD drives, are classified as ARMD (ATAPI Removable Media Device) and can appear as either a super-floppy (non-partitioned media) or a hard drive (partitioned media) to the operating system. These can be supported as bootable devices by a BIOS complying with the ATAPI Removable Media Device BIOS Specification,[52] originally developed by Compaq Computer Corporation and Phoenix Technologies. It specifies provisions in the BIOS of a personal computer to allow the computer to be bootstrapped from devices such as Zip drives, Jaz drives, SuperDisk (LS-120) drives, and similar devices.
These devices have removable media like floppy disk drives, but capacities more commensurate with hard drives, and programming requirements unlike either. Due to limitations in the floppy controller interface most of these devices were ATAPI devices, connected to one of the host computer's ATA interfaces, similarly to a hard drive or CD-ROM device. However, existing BIOS standards did not support these devices. An ARMD-compliant BIOS allows these devices to be booted from and used under the operating system without requiring device-specific code in the OS.
A BIOS implementing ARMD allows the user to include ARMD devices in the boot search order. Usually an ARMD device is configured earlier in the boot order than the hard drive. Similarly to a floppy drive, if bootable media is present in the ARMD drive, the BIOS will boot from it; if not, the BIOS will continue in the search order, usually with the hard drive last.
There are two variants of ARMD, ARMD-FDD and ARMD-HDD. Originally ARMD caused the devices to appear as a sort of very large floppy drive, either the primary floppy drive device 00h or the secondary device 01h. Some operating systems required code changes to support floppy disks with capacities far larger than any standard floppy disk drive. Also, standard-floppy disk drive emulation proved to be unsuitable for certain high-capacity floppy disk drives such as Iomega Zip drives. Later the ARMD-HDD, ARMD-"Hard disk device", variant was developed to address these issues. Under ARMD-HDD, an ARMD device appears to the BIOS and the operating system as a hard drive.
ATA over Ethernet
[edit]In August 2004, Sam Hopkins and Brantley Coile of Coraid specified a lightweight ATA over Ethernet protocol to carry ATA commands over Ethernet instead of directly connecting them to a PATA host adapter. This permitted the established block protocol to be reused in storage area network (SAN) applications.
Compact Flash
[edit]
Compact Flash (CF) in its IDE mode is essentially a miniaturized ATA interface, intended for use on devices that use flash memory storage. No interfacing chips or circuitry are required, other than to directly adapt the smaller CF socket onto the larger ATA connector. (Although most CF cards only support IDE mode up to PIO4, making them much slower in IDE mode than their CF capable speed[53])
The ATA connector specification does not include pins for supplying power to a CF device, so power is inserted into the connector from a separate source. The exception to this is when the CF device is connected to a 44-pin ATA bus designed for 2.5-inch hard disk drives, commonly found in notebook computers, as this bus implementation must provide power to a standard hard disk drive.
CF devices can be designated as devices 0 or 1 on an ATA interface, though since most CF devices offer only a single socket, it is not necessary to offer this selection to end users. Although CF can be hot-pluggable with additional design methods, by default when wired directly to an ATA interface, it is not intended to be hot-pluggable.
See also
[edit]- Advanced Host Controller Interface – Computer standard for SATA host controllers
- Compact Flash – Memory card format
- CE-ATA – Interface for small hard drives
- FATA (hard drive)
- INT 13H – BIOS interrupt call for disk access
- IT8212
- Master/slave (technology) – Relationship between devices in which one controls the other
- List of device bandwidths
Notes
[edit]- ^ A single PATA bus is limited to two devices, although a computer can, and often does, have more than one PATA bus.
References
[edit]- ^ Veitch, Martin. "Five years ago: 120MB floppy gets mobile". zdnet.com. ZDNET. Retrieved 24 July 2025.
- ^ James, Porter (October 1998). "HIGH CAPACITY FLEXIBLE DISK DRIVE SPECIFICATIONS". 1998 DISK/TREND REPORT, REMOVABLE DATA STORAGE. pp. HFSPEC-4 thru HFSPEC-9.
- ^ Imation SuperDisk Internal IDE Drive User's Guide (52-0000-5717-5 Rev. A 3/99 ed.). Imation. 1999.
- ^ "t13.org".
- ^ "Serial ATA: A Comparison with Ultra ATA Technology" (PDF). Seagate Technology. Archived from the original (PDF) on 2012-01-05. Retrieved 23 January 2012.
- ^ Frawley, Lucas. "Parallel vs. Serial ATA". What Is? The Information for Your Computer Questions. Directron.com. Archived from the original on 1 August 2003. Retrieved 23 January 2012.
- ^ a b David A. Deming, The Essential Guide to Serial ATA and SATA Express, CRC Press – 2014, page 32
- ^ Common Access Method AT Bus Attachment, Rev 1, April 1, 1989, CAM/89-002, CAM Committee
- ^ Kozierok, Charles M. "Overview of the IDE/ATA Interface". The PC Guide. Archived from the original on 2001-04-18. Retrieved 2013-06-14.
- ^ Lamers, Lawrence J., ed. (1994). AT Attachment Interface for Disk Drives (PDF) (Technical report). ANSI ASC X3. X3.221-1994. Archived from the original (PDF) on 2012-03-21. Retrieved 2014-08-28.
- ^ Finch, Stephen G., ed. (March 18, 1996). AT Attachment Interface with Extensions (ATA-2) revision 4c (PDF) (Technical report). ANSI ASC X3T10. X3.279-1996. Archived from the original (PDF) on July 28, 2011. Retrieved August 28, 2014.
- ^ Stevens, Curtis E., ed. (September 6, 2008). AT Attachment 8 – ATA/ATAPI Command Set (ATA8-ACS) revision 6a (PDF) (Technical report). ANSI ASC T13. INCITS 452-2008. Archived from the original (PDF) on October 10, 2014. Retrieved June 21, 2016.
- ^ William Rothwell, LPIC-2 Cert Guide: (201-400 and 202-400 exams), Pearson IT Certification – 2016, page 150
- ^ Nitin Vengurlekar, Murali Vallath, Rich Long, Oracle Automatic Storage Management: Under-the-Hood & Practical Deployment Guide, McGraw Hill Professional – 2007, page 6
- ^ Simon Collin, Dictionary of Computing: Over 10,000 Terms Clearly Defined, A&C Black, 2009, page 67
- ^ Scott Mueller, Upgrading and Repairing PCs – Chapter 7. The ATA/IDE Interface, Que Publishing, Jun 22, 2015
- ^ "System Architecture: a look at hard drives". Archived from the original on 2006-05-08. Retrieved 2008-07-25.
- ^ Kozierok, Charles M. (2001-04-17). "Overview and History of the IDE/ATA Interface". The PC Guide. Archived from the original on 2001-04-18. Retrieved 2008-08-23.
- ^ Gene Milligan (2005-12-18). "The History of CAM ATA". Archived from the original on 2008-10-04. Retrieved 2008-08-27.
- ^ Burniece, Tom (July 21, 2011). "Conner CP341 Drive (ATA/IDE)". Wikifoundry. Computer History Museum Storage Special Interest Group. Archived from the original on February 24, 2021. Retrieved January 10, 2020.
- ^ Kozierok, Charles M. (2001-04-17). "ATA (ATA-1)". The PC Guide. Archived from the original on 2019-02-13. Retrieved 2008-08-23.
- ^ Technical Committee T13 AT Attachment (1994). AT Attachment Interface for Disk Drives (ATA-1). Global Engineering Documents.
{{cite book}}: CS1 maint: numeric names: authors list (link) - ^ Independent Technology Service (2008). "Data Recovery and Hard Disk Drive Glossary of Terms". Archived from the original on 2012-07-11. Retrieved 2012-07-11.
- ^ Kozierok, Charles M. (2001-04-17). "ATA (ATA-2)". The PC Guide. Archived from the original on 2019-02-13. Retrieved 2008-08-23.
- ^ a b Technical Committee T13 AT Attachment (1996). AT Attachment Interface with Extensions (ATA-2). Global Engineering Documents.
{{cite book}}: CS1 maint: numeric names: authors list (link) - ^ Kozierok, Charles M. (2001-04-17). "SFF-8020 / ATA Packet Interface (ATAPI)". The PC Guide. Archived from the original on 2019-01-30. Retrieved 2008-08-23.
- ^ Kozierok, Charles M. (2001-04-17). "ATA/ATAPI-4". The PC Guide. Archived from the original on 2019-01-30. Retrieved 2008-08-23.
- ^ Technical Committee T13 AT Attachment (1998). AT Attachment with Packet Interface Extension (ATA/ATAPI-4). Global Engineering Documents.
{{cite book}}: CS1 maint: numeric names: authors list (link) - ^ Western Digital Corporation. "Ultra ATA/100 Extends Existing Technology While Increasing Performance and Data Integrity" (PDF). Archived (PDF) from the original on 2022-10-09.
- ^ a b "kursk.ru – Standard CMOS Setup". Archived from the original on 2018-10-04. Retrieved 2011-05-27.
- ^ "teleport.com – Interrupts Page". Archived from the original on 2 November 2001.
- ^ FryeWare (2005). "EnableBigLba Registry Setting in Windows 2000 and XP". Retrieved 2011-12-29.
The setting is
HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Services\atapi\Parameters\EnableBigLba = 1 - ^ LLXX (2006-07-12). "Enable48BitLBA – Break the 137 GB barrier!". 1.1. Archived from the original on 2013-12-12. Retrieved 2013-09-03.
- ^ "Western Digital stops sales of PATA drives". Myce.com. 2013-12-20. Retrieved 2013-12-25.
- ^ "Welcome to Transcend website". Archived from the original on 2011-09-27. Retrieved 2007-02-01.
- ^ "Information Technology – AT Attachment with Packet Interface – 5 (ATA/ATAPI-5) – Working Draft" (PDF). 2000-02-29. p. 315. Archived from the original (PDF) on 2006-05-27. Retrieved 2013-08-25.
- ^ "An Introduction to Parallel ATA (PATA) – Definition and History". MiniTool. 2020-05-12. Retrieved 2023-12-12.
- ^ Kozierok, Charles M. (2001-04-17). "Independent Master/Slave Device Timing". The PC Guide. IDE/ATA Configuration and Cabling. Archived from the original on 2019-01-17. Retrieved 2008-08-08.
- ^ "Security User Guide" (third ed.). US: HP. June 2008. 463798-003.
- ^ "Rockbox – Unlocking a password protected harddisk".
- ^ "TCG Storage, Opal, and NVMe".
- ^ a b Michael Wei; Laura M. Grupp; Frederick E. Spada; Steven Swanson (2011). "Reliably Erasing Data From Flash-Based Solid State Drives" (PDF). FAST'11: Proceedings of the 9th USENIX conference on File and storage technologies. Wikidata Q115346857. Retrieved 2018-01-08.
- ^ "Beware – When SECURE ERASE doesn't erase at all". The HDD Oracle. 2015-11-15. Retrieved 2018-01-08.
- ^ "ATA Secure Erase (SE) and hdparm". 2016-11-06. Retrieved 2018-01-08.
- ^ Anton Shilov (2021-05-21). "Seagate Lists the Mach.2: The World's Fastest HDD". tomshardware.com. Archived from the original on 2021-07-20. Retrieved 2021-07-20.
- ^ Sean Webster (2021-07-02). "Intel Optane SSD DC P5800X Review: The Fastest SSD Ever Made". tomshardware.com. Archived from the original on 2021-07-20. Retrieved 2021-07-20.
- ^ "Serial ATA—A Comparison with Ultra ATA Technology" (PDF). Archived from the original (PDF) on 2007-12-03. www.serialata.org
- ^ "mpcclub.com – Em8550datasheet.pdf" (PDF). Archived from the original (PDF) on 2011-07-25. Retrieved 2011-05-18.
- ^ "Direct Memory Access (DMA) Modes and Bus Mastering DMA".
- ^ a b CompactFlash 2.1
- ^ "CompactFlash 6.0". Archived from the original on 21 November 2010.
- ^ Curtis E. Stevens; Paul J. Broyles (1997-01-30). "ATAPI Removable Media Device BIOS Specification, Version 1.0" (PDF). phoenix.com. Archived from the original (PDF) on 2010-01-02. Retrieved 2015-08-25.
- ^ Rysanek, Frank. "CompactFlash cards and DMA/UDMA support in True IDE (tm) mode". Czechoslovakia: FCC PS. Retrieved 2019-06-17.
External links
[edit]Parallel ATA
View on GrokipediaHistory and Development
Origins as IDE and ATA-1
Integrated Drive Electronics (IDE) was developed as a cost-effective interface that integrated the disk controller directly onto the hard drive itself, eliminating the need for a separate host adapter card and simplifying system design for personal computers. This approach reduced hardware costs and complexity compared to earlier interfaces like ST-506, which required dedicated controllers and detailed configuration of drive parameters such as cylinders, heads, and sectors.[5][6] The integration allowed for easier installation and broader compatibility in IBM PC-compatible systems, marking a significant shift toward self-contained storage devices. The origins of IDE trace back to 1984 when Compaq Computer Corporation initiated the concept to streamline hard disk integration, collaborating with Western Digital to adapt an ST-506 controller for on-drive implementation. In 1985, Imprimis (the disk drive division of Control Data Corporation) produced the first drives with this integrated design for Compaq systems, and by 1986, Western Digital's controllers were incorporated into the Compaq Deskpro 386, the first personal computer to ship with IDE support. This development directly addressed the limitations of the ST-506 interface, which had been standard since the IBM PC/AT in 1984 but was cumbersome due to its reliance on external controllers and manual BIOS setup.[5][7][8] The IDE interface was formalized as the AT Attachment (ATA) standard, with ATA-1 approved by the American National Standards Institute (ANSI) as X3.221-1994, defining a 16-bit parallel data transfer protocol for hard disk drives. It supported Programmed Input/Output (PIO) modes 0 through 2, achieving transfer rates up to 8.3 MB/s in PIO mode 2, and used Cylinder-Head-Sector (CHS) addressing, limited by BIOS compatibility to 1024 cylinders, 16 heads, and 63 sectors per track, supporting drives up to approximately 528 MB in capacity. While ATA is the official technical designation, IDE became the prevalent marketing term, particularly in the context of early adoption within the IBM PC-compatible market.[5][7][9] The initial physical interface featured a 40-pin Insulation Displacement Connector (IDC) ribbon cable for data and control signals, with power supplied separately via a 4-pin Molex connector providing +5V and +12V rails to operate the drive's electronics and spindle motor. This design enabled direct connection to the host's expansion bus, fostering widespread use in consumer PCs during the late 1980s.[5][10]Evolution through ATA-2 and EIDE
The ATA-2 specification, formally known as AT Attachment Interface with Extensions (ANSI X3.279-1996), was approved in 1996 and built upon the foundational ATA-1 standard by introducing enhanced data transfer capabilities and addressing early capacity constraints.[9] It added support for PIO modes 3 and 4, which achieved theoretical transfer rates of up to 16.7 MB/s, and multi-word DMA modes 0 through 2, also reaching up to 16.7 MB/s in mode 2, enabling more efficient direct memory access without CPU intervention.[9] Additionally, ATA-2 standardized 28-bit logical block addressing (LBA), which bypassed the 528 MB limitation imposed by the original cylinder-head-sector (CHS) addressing scheme in ATA-1, allowing access to drives up to 137 GB in capacity.[11] In parallel with the ATA-2 development, Western Digital introduced Enhanced IDE (EIDE) in 1994 as a marketing term to promote drives incorporating these advanced features, emphasizing improved performance and compatibility for consumer systems.[12] EIDE highlighted the ability to support two devices per ATA channel—typically a master and slave configuration—while integrating input/output capabilities that facilitated connections for additional peripherals like CD-ROM drives on the same interface.[13] This branding helped differentiate EIDE-equipped drives from earlier IDE models, promoting broader adoption in personal computers. EIDE and ATA-2 features saw rapid historical uptake starting around 1994-1995, coinciding with the rise of Intel Pentium processors in mainstream PCs, where they became the de facto standard for storage interfaces.[9] The 28-bit LBA addressing proved particularly vital during this era, resolving size limitations that had previously capped usable drive capacity at 528 MB under legacy CHS systems and enabling the integration of larger hard drives into desktop configurations.[11] ATA-2 also introduced power management features to optimize energy use and drive longevity, including Standby mode—which spins down the drive while keeping it responsive to commands—and Sleep mode, which powers down the drive more completely for extended inactivity.[14] These modes, along with basic acoustic management options to reduce operational noise, were designed to balance performance with efficiency in always-on computing environments.[14]Introduction of ATAPI
ATAPI, or ATA Packet Interface, is a protocol extension to the ATA standard that enables the connection of non-hard disk storage devices, such as CD-ROM drives and tape drives, to the ATA bus using SCSI-like command packets.[15] Developed by the ANSI X3T10 committee's ATA/ATAPI ad hoc working group during 1994-1995, with initial drafts emerging in early 1994 and standardization progressing through revisions up to publication as part of ANSI X3.298-1997, ATAPI addressed the growing need for affordable multimedia device support in personal computers.[16] This extension built on ATA-2's multi-device capabilities by introducing a packet-based command mechanism, allowing diverse peripherals to share the same interface without dedicated SCSI controllers.[17] The core of ATAPI is the Packet Command feature set, which uses the ATA command code A0h to initiate transfers of device-specific command packets over the bus.[16] These packets are typically 12 bytes long but can extend to 16 bytes if the high byte of the cylinder low register is set during the command issuance, enabling flexible encoding of operations akin to SCSI commands while utilizing ATA's task file registers and signaling.[15] This design bridges the ATA and SCSI paradigms, permitting non-disk devices to issue complex, vendor-defined instructions for tasks like media reading or audio control without altering the underlying electrical interface.[18] In historical context, ATAPI's development by the X3T10 committee, in collaboration with the Small Form Factor (SFF) Committee, facilitated the integration of emerging multimedia technologies into Enhanced IDE (EIDE) systems, reducing costs by eliminating the need for separate SCSI hardware in consumer PCs.[17] ATAPI devices are identified through the IDENTIFY PACKET DEVICE command (A1h), which returns a 256-word parameter block detailing capabilities, distinct from the standard ATA IDENTIFY DEVICE command (ECh) used for hard drives.[16] This ensures backward compatibility, as ATAPI peripherals respond appropriately to ATA hosts while ignoring non-applicable commands, allowing seamless coexistence on the same cable with traditional ATA disks.[15]Advancements in UDMA and Later Revisions
The ATA-3 specification, published in 1997 as ANSI X3.298-1997, refined error correction mechanisms and introduced support for overlapped commands, allowing multiple devices on the same channel to process commands concurrently without halting the bus.[16] These enhancements built on prior PIO and DMA modes from ATA-2, improving reliability and efficiency in multi-device configurations.[9] In 1998, the ATA-4 standard (ANSI NCITS 317-1998) marked a significant leap with the introduction of Ultra DMA (UDMA) modes, starting with UDMA/33, which achieved transfer rates of 33 MB/s through double data rate signaling that synchronized data transitions on both rising and falling clock edges.[9] This innovation, often branded as Ultra ATA by Quantum and Intel, doubled the effective bandwidth over previous DMA modes while maintaining backward compatibility.[19] The ATA-5 specification, ratified in 2000 as ANSI NCITS 340-2000, extended UDMA capabilities to UDMA/66 at 66 MB/s, but required 80-conductor cables to minimize crosstalk and signal noise at higher frequencies.[20] These cables added ground wires between signal lines, ensuring stable performance for drives exceeding 33 MB/s without necessitating changes to the 40-pin connector.[21] Advancing further, ATA-6 in 2002 (ANSI NCITS 361-2002) introduced UDMA/100 at 100 MB/s and implemented 48-bit Logical Block Addressing (LBA), enabling support for drives larger than 128 GB by expanding the addressable space to a theoretical maximum of 144 petabytes.[9] This addressing scheme used additional register bits for higher-capacity storage, addressing the limitations of 28-bit LBA in earlier revisions. The final major revision, ATA-7 in 2004 (INCITS 397-2005), added UDMA/133 at 133 MB/s and Native Command Queuing (NCQ), permitting up to 32 outstanding commands to be queued and reordered by the drive for optimized seek patterns and reduced latency. The Ultra ATA branding, originating from Quantum's initiatives, became synonymous with these UDMA modes and saw peak adoption in personal computers during the early 2000s, powering mainstream storage until the transition to serial interfaces.[19][22]Limitations and Obsolescence
One significant limitation of Parallel ATA stemmed from early BIOS implementations in x86 systems, which relied on the INT 13h interrupt and Cylinder-Head-Sector (CHS) addressing scheme, capping addressable storage at approximately 8.4 GB due to restrictions like 1024 cylinders, 255 heads, and 63 sectors per track.[23] This constraint was partially mitigated by the introduction of Logical Block Addressing (LBA) in ATA-2, which translated CHS to linear sector addressing, though it remained software-dependent on BIOS support for larger drives.[23] Further complicating capacity scaling, the 28-bit LBA addressing in pre-ATA-6 implementations limited drives to 137 GB (268,435,455 sectors × 512 bytes per sector), affecting operating systems like pre-2002 Microsoft Windows and older BIOS versions until ATA-6 introduced 48-bit LBA in 2002.[24] The parallel signaling nature of the interface also imposed inherent bottlenecks, including crosstalk and electromagnetic interference (EMI) from the multi-wire ribbon cables, which degraded signal integrity and effectively capped reliable transfer speeds at Ultra DMA mode 5 (UDMA/133) of 133 MB/s.[25] Additionally, the maximum cable length was restricted to 18 inches (46 cm) to minimize noise and timing issues, complicating installation in larger chassis or systems with multiple devices.[26] Parallel ATA dominated personal computer storage interfaces from its origins in 1988 with ATA-1 until around 2005, serving as the standard for hard drives and optical devices during that period.[27] Its obsolescence accelerated with the introduction of Serial ATA (SATA) 1.0 in 2003, which offered 1.5 Gb/s (150 MB/s) serial transfer rates, thinner 7-conductor cables for easier routing, and native hot-swapping support, addressing PATA's physical and performance constraints while maintaining backward compatibility.[28] No substantive developments occurred after ATA-8 in 2007, which focused on command set refinements amid the full transition to SATA.[29] By 2025, Parallel ATA is rare in new consumer systems but persists in legacy embedded and industrial applications, often via adapters converting to SATA or USB interfaces to interface with modern hardware.[30]Physical and Electrical Interface
Standard 40-Pin Connector and Cable
The standard Parallel ATA interface employs a 40-pin Insulation Displacement Connector (IDC) header for the task file interface between the host adapter and storage devices. This connector facilitates parallel data transfer over 16 data lines (D0 through D15), which are assigned to pins 3 through 18 in an interleaved arrangement to alternate signal and ground traces for reduced crosstalk.[31] The interface also includes provisions for 10 address bits (A0 through A9) in the register addressing space, with the physical connector carrying address lines A0 (pin 35), A1 (pin 33), and A2 (pin 36), alongside chip select signals CS0 (pin 38) and CS1 (pin 37) to decode the full address range for command, status, and data registers.[31] Key control signals, such as IORDY (I/O Ready on pin 27) for synchronizing data transfers and DMACK (DMA Acknowledge on pin 29) for DMA operations, are routed through dedicated pins, while multiple ground pins (e.g., pins 2, 19, 22, 24, 26, 30, 40) provide shielding and return paths to maintain signal integrity.[31] Power for Parallel ATA devices is delivered separately via a 4-pin Molex (Mini-Fit Jr. or equivalent) connector, supplying +5 V DC for logic circuits (typically on pin 4) and +12 V DC for spindle motors and actuators (on pin 1), with ground connections on pins 2 and 3; this separation from the signal connector allows for robust power delivery without interference.[32] The recommended mating connector for the power interface is AMP part 1-480424-0 housing with 60619-4 contacts, ensuring reliable connections under varying load conditions.[32] The associated cable is a 40-wire ribbon cable, typically constructed with 28 AWG stranded conductors, featuring IDC connectors at both ends for easy attachment to host and device headers; its maximum recommended length is 18 inches (457 mm) to minimize signal skew, attenuation, and noise induced by capacitance and inductance in longer runs.[32][33] This length constraint is critical for maintaining timing margins in parallel signaling, where even small delays between traces can degrade performance. Electrically, the interface uses TTL-compatible open-drain or tri-state signaling with 5 V logic levels, where a logic high is defined as 2.4 V to 5.25 V and a logic low as 0 V to 0.6 V for outputs, with input thresholds at 2.0 V minimum for high and 0.8 V maximum for low.[31] Rise and fall times for signals in PIO modes are constrained to ensure reliable edge detection, typically ranging from 5 ns minimum to 70 ns maximum depending on the mode (e.g., slower for PIO Mode 0 at 70 ns to support legacy compatibility), measured under loaded conditions with pull-up resistors and capacitive loads up to 56 pF.[32] In terms of system integration, the host controller manages primary and secondary channels independently, with each channel supporting daisy-chaining of up to two devices on a single cable—one at the host end and the other at the cable's midpoint or far end—to enable cost-effective expansion without additional host adapters.[32] Later evolutions of the standard introduced 80-conductor variants to further mitigate crosstalk at higher speeds.[32]44-Pin and 80-Conductor Variants
The 44-pin variant of the Parallel ATA interface was developed specifically for 2.5-inch form factor hard drives commonly used in laptop computers, providing a more compact connector suitable for space-constrained mobile devices.[34] This variant maintains the same electrical signaling as the standard 40-pin connector but incorporates four additional pins dedicated to ground and power, which improve signal integrity by reducing electromagnetic interference (EMI).[34] Introduced in the mid-1990s alongside early 2.5-inch ATA drives, it features a finer pin pitch of 2.0 mm compared to the 2.54 mm pitch of the 40-pin design, enabling tighter integration within laptop chassis.[34] In contrast, the 80-conductor cable variant was introduced with the ATA/ATAPI-5 specification to support Ultra DMA mode 4 (UDMA/66), which achieves transfer rates up to 66.7 MB/s.[35] This cable adds 40 dedicated ground wires interleaved between the 40 signal wires of the original 40-pin design, significantly reducing crosstalk and noise to enable reliable operation at higher strobe rates.[36] It remains backward compatible with 40-pin devices through a keyed connector mechanism that detects cable type via the CBLID pin, preventing unintended high-speed operation on incompatible setups.[35] Mechanically, the 80-conductor cable is thicker and less flexible than its 40-conductor predecessor due to the doubled number of wires, with a maximum recommended length of 18 inches (457 mm) to preserve signal quality and minimize attenuation.[36] The 44-pin variant, optimized for portability, employs even finer wiring and connectors to fit mobile form factors without compromising the core ATA protocol.[34] Adoption of the 80-conductor cable became mandatory for UDMA/66 and faster modes to comply with FCC Class B EMI emission standards, ensuring reduced electromagnetic radiation in certified systems.[36] This requirement helped maintain overall system electromagnetic compatibility while enabling the performance gains of later ATA revisions.[35]Device Addressing and Multiple Devices
Parallel ATA employs a master/slave architecture to connect up to two storage devices on a single channel, with the master device designated as position 0 and the slave as position 1.[37] The master is typically positioned at the end of the daisy-chained cable closest to the host controller, while the slave is connected in the middle to ensure proper signal integrity and termination.[38] Device roles are configured using jumpers or DIP switches on the drives themselves, where the master drive has specific pins shorted (e.g., pins 7-8 on Seagate models), and the slave either has no jumpers or a different configuration.[38] This setup allows the host to distinguish and address devices via the DEV bit in the Device register, where a value of 0 selects the master and 1 selects the slave.[37] Each ATA channel supports a maximum of two devices due to the shared bus architecture and signal constraints, such as the Device Active/Slave Present (DASP-) line used for detection during power-on or reset.[37] Standard controllers provide two channels—primary and secondary—enabling up to four devices total across the system.[39] During initialization, the master device (Device 0) interrogates the slave (Device 1) via the DASP- signal to confirm presence, and the slave reports its diagnostic status back through the Passed Diagnostics (PDIAG-) line.[37] Commands are issued to both devices simultaneously, but only the selected one executes them, except for the EXECUTE DEVICE DIAGNOSTIC command, which runs on both.[37] Configuration rules permit mixing device types (e.g., hard disk drives with optical drives) in master/slave pairs, provided they adhere to ATA/ATAPI standards.[37] However, the transfer speed for the entire cable is limited to the capabilities of the slowest device, as the shared bus requires uniform mode negotiation to avoid signal errors.[37] In early implementations under the original IDE (ATA-1) standard, BIOS support was restricted to a single channel, limiting systems to two drives total via INT 13h interrupts.[40] The introduction of Enhanced IDE (EIDE) with ATA-2 expanded this by adding a secondary channel and updating BIOS firmware to support four drives, enabling broader multi-device configurations in PCs from the mid-1990s onward.[39]Cable Select Mechanism
The Cable Select (CSEL) mechanism provides an automated method for configuring Parallel ATA devices as master or slave without requiring manual jumper adjustments on the drives. Standardized in the ATA-2 specification (ANSI X3.279-1996), it relies on a specially wired cable to signal device positions electrically.[41] In operation, the CSEL signal uses pin 28 of the 40-pin ATA connector. The cable grounds pin 28 at the host adapter end and maintains the connection to the master device connector (typically color-coded black or blue), while the slave device connector (often gray) has pin 28 intentionally blocked or open-circuited, preventing the signal from reaching the slave device. Upon power-up, each drive samples its CSEL pin: a grounded state configures the drive as master (Device 0), while an open state configures it as slave (Device 1). This auto-detection occurs independently on each drive, ensuring proper addressing on the shared bus.[42][43] CSEL requires a dedicated 40-conductor ribbon cable with the modified pin 28 wiring at the slave end and keyed or color-coded connectors to prevent incorrect installation, such as swapping master and slave positions, which could lead to detection failures. These cables, limited to a maximum length of 18 inches (0.46 meters) for signal integrity, became common with ATA-2-compliant hardware.[42][44] The primary advantages of CSEL include simplified user installation by eliminating jumper configuration errors and compatibility with Plug and Play systems, as it automates device role assignment. It gained widespread support on ATA drives manufactured after 1995, making it a standard feature in most consumer hardware by the late 1990s.[41][45] However, CSEL has limitations: early ATA-1 drives prior to 1995 often lack support, requiring fallback to manual master/slave jumper settings if used with CSEL cables. Additionally, improper cabling or incompatible host adapters can result in both drives defaulting to master mode, causing bus conflicts and preventing recognition.[42][43] This approach contrasts with the traditional manual jumper method for master/slave selection but serves as an alternative for automated setups.[44]Data Transfer Protocols
PIO and DMA Transfer Modes
In Parallel ATA, data transfers can occur using either Programmed Input/Output (PIO) or Direct Memory Access (DMA) modes, which define how data is moved between the host system and the storage device. PIO modes rely on the host CPU to directly manage each data transfer by repeatedly reading from or writing to the device's data register, making it a simple but processor-intensive method suitable for early implementations. These modes were progressively defined across ATA revisions, with PIO 0 introduced in the original ATA specification and higher modes added in ATA-2 and later, ensuring compatibility with legacy systems.[37] The PIO modes range from 0 to 4, each characterized by a specific minimum cycle time that determines the transfer rate for 16-bit words. PIO mode 0 has a cycle time of 600 ns, yielding a maximum transfer rate of approximately 3.3 MB/s, while PIO mode 4 achieves a cycle time of 120 ns for up to 16.6 MB/s. Higher modes, such as PIO 3 and 4, mandate the use of the IORDY signal for flow control to handle timing variations, allowing devices to pause transfers if needed. These rates represent theoretical maxima based on the interface width and cycle duration, though actual performance depends on drive capabilities and system overhead.[37][21] In contrast, DMA modes offload data transfer from the CPU to a dedicated DMA controller, which handles the movement of data blocks using dedicated signals like DMARQ and DMACK, thereby reducing processor involvement and improving overall system efficiency. Single-word DMA modes, defined in ATA-1 and ATA-2, transfer one 16-bit word per cycle and support up to mode 2 with a 240 ns cycle time, achieving a maximum of 8.3 MB/s. Multi-word DMA modes, introduced in ATA-2, enable burst transfers of multiple words, reaching up to 16.6 MB/s in mode 2 with a 120 ns cycle time, making them more suitable for larger data operations.[37][21][21] Transfer modes are selected through negotiation using the SET FEATURES command (opcode EFh, subcommand 03h), where the host specifies the desired mode in the sector count register—encoding the transfer type in the upper bits (e.g., 00000b for PIO) and the mode number in the lower bits—allowing the device to confirm support via its IDENTIFY DEVICE response. This process ensures backward compatibility, as devices must implement all lower modes if a higher one is supported, enabling fallback to slower PIO modes if DMA is unavailable. UDMA represents an advanced variant of DMA with enhanced signaling for higher speeds. In performance contexts, PIO modes prioritize broad compatibility in resource-constrained environments, while DMA modes enhance efficiency in multitasking scenarios by minimizing CPU utilization during transfers.[37][37][46]Serialized, Overlapped, and Queued Operations
In Parallel ATA, command execution follows a serialized model by default, where the device sets the BSY (Busy) bit in the status register upon receiving a command and remains busy until the operation completes, preventing the host from issuing subsequent commands to that device until the DRDY (Device Ready) bit is asserted. This ensures orderly processing but limits efficiency for multi-device or multi-command workloads.[37] The Overlapped Feature Set, introduced in ATA-3, enables improved concurrency by allowing the host to issue a new command to the master device while the slave device is still processing its prior command, provided both devices support the feature and it is enabled via the SET FEATURES command. Arbitration occurs through the DMACK- (DMA Acknowledge) signal, which the host negates to pause transfers, and DSACK- (DMA Slave Acknowledge) or equivalent signals from the device to manage bus release and resumption, with the device clearing BSY and DRQ (Data Request) bits to free the bus during extended operations like DMA transfers. These overlaps rely on DMA modes to handle data movement without full serialization. Devices indicate support via bit 7 in word 82 of the IDENTIFY DEVICE response.[37][47] Queued operations, added in ATA-4 as part of the Queued Feature Set, extend overlaps to allow multiple commands to the same device, using tagged command queuing (TCQ) where each command is assigned a unique tag (0-255) stored in the Sector Count register to identify and reorder operations for optimal execution, such as minimizing seek times on hard disks. The maximum queue depth is reported in bits 7-0 of word 75 in the IDENTIFY DEVICE command (0 indicates 1 command, 255 indicates 256 commands), though implementations typically support up to 32 tags. Commands like READ DMA QUEUED and WRITE DMA QUEUED EXT are used, with the device managing the queue internally and interrupting via the SERV (Service) bit in the status register when a tagged command completes or requires attention. In ATA-7, TCQ was further optimized, limiting tags to 32 in common implementations and enabling drive-level reordering to reduce latency in random access patterns. However, TCQ saw limited adoption in PATA due to high CPU overhead and complex interrupt handling in contemporary operating systems and drivers.[37][48] The SERVICE command (opcode A2h), mandatory for devices supporting the Overlapped or Queued Feature Sets, facilitates queue management by allowing the host to query and select the next ready command from the queue without aborting others; upon execution, it returns the tag of the command requiring service in the Sector Number register or sets the ABRT (Abort) bit if no commands are pending.[37][48] Error handling in overlapped and queued operations prioritizes recovery without disrupting the entire queue; for instance, an invalid tag or unsupported command sets the ABRT bit in the Error register to abort only the affected command, while a device RESET (via the hardware or SOFTWARE RESET command) clears all queued commands and restores serialized mode. If a queued device encounters a fatal error, it may assert the ERR (Error) bit and interrupt, requiring the host to issue SERVICE commands to drain the queue before re-enabling overlaps.[37]Security and Password Features
The ATA Security Feature Set, introduced in the ATA-3 specification in 1997, provides an optional mechanism for password-based access control on ATA devices to protect user data from unauthorized access.[49][3] This feature set allows devices to enter a locked state upon power-on or hardware reset, requiring authentication before read or write operations can proceed, and supports secure erasure options to render data irrecoverable.[3] It has remained largely unchanged across subsequent ATA revisions, serving as a foundational access control method prior to the development of more advanced standards like self-encrypting drives (SEDs).[49] The feature set employs two passwords: a user password, which is required for normal unlocking and access, and a master password, typically set by the manufacturer or administrator for recovery purposes.[3][49] Each password is limited to 32 bytes in length and is set or modified using the SET PASSWORD command (opcode F1h), which also enables the security mode and specifies the security level.[49][3] Two primary security levels are defined: High, where the master password can unlock the device and disable security after authenticating with the user password; and Maximum, a stricter variant where the master password cannot unlock the device but can initiate erasure.[3] To unlock a locked device, the SECURITY UNLOCK command (opcode F2h) must be issued with the correct password, clearing the locked state; failure after five attempts typically requires a power cycle.[3][49] The SECURITY FREEZE LOCK command (opcode F5h) can then be used to prevent further password changes or security modifications until a power-on reset occurs, enhancing protection against tampering.[3] For data protection, the SECURITY ERASE UNIT command (opcode F4h), preceded by SECURITY ERASE PREPARE (opcode F3h), allows authenticated erasure of all user data in normal or enhanced modes, disabling security afterward; the enhanced mode provides a more thorough wipe using drive-specific methods.[3] These features were commonly implemented in enterprise environments during the late 1990s and early 2000s to safeguard sensitive data on laptops and servers, often integrated via BIOS settings for boot-time enforcement, before the shift to hardware-encrypted solutions.[49][50] Despite its utility, the ATA Security Feature Set has significant limitations, as passwords are stored in plaintext within the device's non-volatile memory, making them vulnerable to extraction through physical access, firmware analysis, or specialized recovery tools.[3][49] It provides no data encryption, functioning solely as an access control layer that prevents logical reads and writes but leaves data readable if the drive is physically removed or the password bypassed.[3] Additionally, there is no built-in password recovery mechanism beyond the master password, and security can be frozen or interrupted only by hardware resets, potentially complicating administration in locked scenarios.[3] These weaknesses have led to its obsolescence in favor of standards like TCG Opal for modern SEDs.[49]Specifications and Performance
Features by ATA Revision
The ATA (AT Attachment) standard underwent several revisions under the auspices of the INCITS T13 technical committee, with ANSI approvals spanning from 1994 to 2005, progressively enhancing command sets, addressing modes, and device capabilities for parallel interfaces. Each revision built upon the previous ones while maintaining backward compatibility, introducing specific features to support evolving storage needs such as larger capacities, better efficiency, and broader device support. ATA-1, approved by ANSI as X3.221-1994 on May 12, 1994, established the foundational command set for parallel ATA, including core operations like READ SECTORS and WRITE SECTORS for data access, as well as the IDENTIFY DEVICE command to retrieve drive parameters. It also defined support for both Cylinder-Head-Sector (CHS) addressing, which mapped logical addresses to physical disk geometry, and Logical Block Addressing (LBA) modes for simplified sector-based access independent of geometry.[51] ATA-2, approved by ANSI as X3.279-1996, expanded power management capabilities with commands for entering low-power states like idle, standby, and sleep to reduce energy consumption in inactive drives. It introduced status reporting for removable media, enabling hosts to detect media presence and ejection, and added acoustic management features to control drive noise levels through seek speed adjustments.[52] ATA-3, a T13 committee working draft from 1997, introduced S.M.A.R.T. for drive health monitoring and predictive failure analysis, enhanced security features including master password support and freezing lock, and made DMA commands mandatory for better performance. ATA-4, approved in 1998, refined packet commands for ATAPI devices and introduced Ultra DMA (UDMA) mode 2, enabling faster synchronous transfers while maintaining signal integrity through cycle timing optimizations. These updates focused on bridging parallel ATA with emerging optical and multimedia drives. ATA-5, standardized in 2000, mandated support for 80-conductor cables to reduce crosstalk and enable higher-speed UDMA modes. ATA-6, approved in 2002, extended addressing to 48-bit LBA to accommodate disk capacities beyond the 137 GB limit of 28-bit addressing, supporting up to 144 petabytes theoretically. It also added the streaming feature set, optimizing commands for continuous data flows in applications like video recording and playback. ATA-7, finalized with ANSI approval in 2005, incorporated Native Command Queuing (NCQ) to allow up to 32 commands to be queued and reordered by the drive for optimal execution, reducing latency in random access scenarios. It further included hints for trusted computing environments, providing subcommands to support hardware-based security modules and encryption key management. It also introduced free-fall detection for mobile devices, allowing drives to park heads preemptively upon sensing sudden drops to prevent damage.[53]Defined Transfer Speeds and Capacities
Parallel ATA defines several transfer modes with specified maximum burst rates, calculated based on cycle times and data width. These rates represent theoretical peak performance during data bursts, such as from the drive's buffer to the host.[54] Programmed Input/Output (PIO) modes rely on CPU intervention for each data transfer, with speeds increasing across modes due to reduced cycle times. PIO Mode 0 operates at 3.3 MB/s with a 600 ns cycle time, while PIO Mode 4 achieves 16.6 MB/s at 120 ns.[54] The full PIO mode specifications are as follows:| Mode | Cycle Time (ns) | Transfer Rate (MB/s) |
|---|---|---|
| 0 | 600 | 3.3 |
| 1 | 383 | 5.2 |
| 2 | 240 | 8.3 |
| 3 | 180 | 11.1 |
| 4 | 120 | 16.6 |
| Mode | Cycle Time (ns) | Transfer Rate (MB/s) |
|---|---|---|
| 0 | 240 | 16.6 |
| 1 | 160 | 25 |
| 2 | 120 | 33.3 |
| 3 | 90 | 44.4 |
| 4 | 60 | 66.7 |
| 5 | 40 | 100 |
| 6 | 30 | 133 |