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Closeup of the pins of a pin grid array
The pin grid array at the bottom of prototype Motorola 68020 microprocessor
The pin grid array on the bottom of an AMD Phenom X4 9750 processor that uses the AMD AM2+ socket

A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,[1] and may or may not cover the entire underside of the package. 1.27 mm (0.05") is commonly used with higher pin count PGAs.

PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package (DIP).

Chip mounting

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Underside of an 80486 with lid removed shows die and wire bonded connections.

The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by wire bonding or through flip chip mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example Zen 2 and Zen 3 Ryzen CPUs for the AM4 socket.

Flip chip

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The underside of a FC-PGA package (The die is on the other side.)

A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the heatsink or other cooling mechanism.

FC-PGA CPUs were introduced by Intel in 1999, for Coppermine core Pentium III and Celeron[2] processors based on Socket 370, and were produced until Socket G3 in 2013. FC-PGA processors fit into zero insertion force (ZIF) motherboard sockets; similar packages were also used by AMD.

Material

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Ceramic

[edit]

A ceramic pin grid array (CPGA) is a type of packaging used by integrated circuits. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some CPUs that use CPGA packaging are the AMD Socket A Athlons and the Duron.

A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on Socket AM2 and Socket AM2+. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a ceramic substrate with pins arranged in an array.

  • A 1.2 GHz VIA C3 microprocessor in a ceramic package
    A 1.2 GHz VIA C3 microprocessor in a ceramic package
  • 133 MHz Pentium chip in a ceramic package
    133 MHz Pentium chip in a ceramic package

Organic

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Demonstration of a PGA-ZIF socket (AMD 754)

An organic pin grid array (OPGA) is a type of connection for integrated circuits, and especially CPUs, where the silicon die is attached to a plate made out of an organic plastic which is pierced by an array of pins which make the requisite connections to the socket.

  • The underside of a Celeron-400 in a PPGA
    The underside of a Celeron-400 in a PPGA
  • An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat sink.
    An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat sink.

Plastic

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The topside of a Celeron-400 in a PPGA packing

Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core Celeron processors based on Socket 370.[3] Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.

Underside of a Pentium 4 in a PGA package

Pin layout

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Staggered pin

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The staggered pin grid array (SPGA) is used by Intel processors based on Socket 5 and Socket 7. Socket 8 used a partial SPGA layout on half the processor.

An example of a socket for a staggered pin grid array package
View of the socket 7 321-pin connectors of a CPU

It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square lattice. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as microprocessors.

Stud

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A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in surface-mount technology. The polymer stud grid array or plastic stud grid array was developed jointly by the Interuniversity Microelectronics Centre (IMEC) and Laboratory for Production Technology, Siemens.[4][5]

rPGA

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The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1 mm,[6] as opposed to the 1.27 mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the G1, G2, and G3 sockets.

See also

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References

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Sources

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[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Pin grid array

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from Grokipedia
A pin grid array (PGA) is a type of integrated circuit (IC) packaging in which the package body is typically square or rectangular, and numerous pins are arranged in a uniform grid pattern on the underside to enable electrical connections via insertion into a matching socket on a printed circuit board.[1] These pins, often staggered for ease of insertion, provide a high number of input/output (I/O) connections compared to earlier dual in-line package (DIP) formats, supporting up to several hundred pins in advanced configurations.[2] PGA packages are commonly constructed from materials like ceramic (CPGA) or plastic (PPGA), with the die mounted via wire bonding or flip-chip methods, and often include a heat spreader or slug for improved thermal management.[3] The PGA packaging technology emerged in the late 1980s and early 1990s as a response to the growing complexity of microprocessors requiring more I/O pins and better performance than traditional packages could offer.[4] Intel pioneered early ceramic PGA implementations for processors like the 80386 and 80486 in the 1980s, transitioning to plastic variants by 1993 to reduce costs and enhance manufacturability while maintaining socket compatibility for easier upgrades.[3] This evolution addressed limitations in power distribution and signal integrity, with features like multi-layer organic substrates and nickel-plated copper heat slugs enabling lower thermal resistance (typically 0.30–0.50 °C/W) and reduced propagation delays.[3] PGA packages have been widely applied in desktop, server, and mobile computing, particularly for Intel microprocessors such as the 80386, 80486, and Pentium series, as well as early AMD Athlon models, with pin counts ranging from 168 to over 600.[1] Key advantages include socketability for non-soldered installation, facilitating processor upgrades, and high pin density for complex ICs, though they have largely been supplanted by ball grid array (BGA) and land grid array (LGA) formats in modern designs due to the latter's smaller footprint and better suitability for surface-mount assembly.[2] Variants like flip-chip PGA (FC-PGA) and micro-PGA (μPGA) further optimize electrical and thermal performance for high-speed applications, including embedded systems and testing environments.[5]

Overview

Definition and Characteristics

A pin grid array (PGA) is a type of integrated circuit (IC) packaging characterized by a square or rectangular package body from which an array of pins protrudes perpendicularly from the bottom surface in a uniform grid pattern, facilitating direct insertion into sockets or soldering onto printed circuit boards (PCBs).[1] The pins are typically arranged with a standard pitch of 2.54 mm (0.1 inch), though finer pitches such as 1.27 mm (0.05 inch) may be used for higher-density configurations, enabling reliable electrical interfacing while maintaining mechanical stability.[6] The package body encases the semiconductor die mounted on a multi-layer substrate, which serves as an interconnect platform between the die and the external pins. These pins, often constructed from materials like Kovar with gold plating for corrosion resistance and conductivity, fulfill electrical signal transmission, mechanical support, and thermal dissipation roles by conducting heat away from the die. Typical pin counts range from 68 for smaller logic ICs to over 1,000 for complex microprocessors, with package dimensions varying from approximately 14 × 14 mm for compact devices to 50 × 50 mm or larger to accommodate high pin densities.[1] In a basic cross-sectional view, the structure reveals the die bonded to the substrate (often via wirebonding), surrounded by the package lid or heat spreader, with pins extending downward from the substrate's underside to form the grid array, providing a clear path for I/O signals, power, and ground.[7] Functionally, the PGA design supports high-density input/output (I/O) connections in a compact footprint, allowing for greater integration of circuitry compared to earlier packages like dual in-line (DIP), while its protruding pins enable easy removable installation through zero-insertion-force (ZIF) or low-insertion-force (LIF) sockets on the PCB.[1] This socket compatibility distinguishes PGAs from permanent surface-mount alternatives, such as ball grid arrays (BGAs), by permitting field-upgradable or testable installations without reflow soldering, which is particularly advantageous for performance-critical applications like processors.

Historical Development

The pin grid array (PGA) packaging technology originated in the mid-1970s as a solution to accommodate higher pin counts in large-scale integrated circuits, evolving from earlier dual in-line and flat package designs. In 1975, Hitachi developed the world's first PGA using laminated ceramic technology, introducing a 52-pin configuration for logic LSI in mainframe computers using ECL technology, where pins were silver-brazed to a ceramic substrate in a grid pattern to support expanding I/O requirements up to 100 pins or more.[8] This innovation addressed the limitations of linear pin arrangements in high-density systems, laying the groundwork for grid-based packaging amid the rapid growth in transistor integration driven by Moore's Law. PGA saw its first widespread commercial adoption in microprocessors during the 1980s, coinciding with the demand for 32-bit architectures and increased I/O pins. Intel introduced the 132-pin ceramic PGA with the 80386 microprocessor in 1985, enabling a 32-bit address bus and improved performance over prior 16-bit designs while maintaining compatibility.[9] Adoption accelerated with the 80486 in 1989, which utilized a 168-pin PGA to incorporate additional signals like cache control and power/ground pins, standardizing the format through JEDEC specifications for pin spacing (typically 0.1 inches or 2.54 mm) and layouts to ensure interoperability.[10] By 1993, the original Pentium processor employed a 273-pin staggered PGA, further boosting pin density for superscalar processing and marking a key milestone in desktop computing.[11] In the 1990s, PGA evolved toward cost-effective materials, with Intel initiating development of plastic pin grid array (PPGA) packages in 1993 to replace ceramics, reducing manufacturing expenses while supporting higher volumes for consumer processors; by the late 1990s, PPGA variants exceeded 500 pins in some high-end designs for servers and workstations.[12] The removable PGA (rPGA) emerged in the early 2000s for mobile applications, debuting prominently in 2009 with Intel's first-generation mobile Core i7 series using rPGA 988A (Socket G1) to facilitate upgradability in laptops.[13] However, post-2000s miniaturization and thermal demands led to a decline in PGA favor for mainstream consumer CPUs, as Intel transitioned to land grid array (LGA) sockets starting in 2004 with Socket 775 for Pentium 4 processors, and ball grid array (BGA) for soldered mobile chips; PGA persists in niche high-reliability sectors like aerospace and some legacy computing applications as of 2025, benefiting from JEDEC-standardized robustness.[2]

Package Construction

Substrate Materials

The substrate in a pin grid array (PGA) package serves as a multi-layer board, typically comprising 2 to 10 layers, that interconnects the semiconductor die to the protruding pins while providing electrical routing pathways, thermal dissipation capabilities, and mechanical support for the overall package structure.[14][15] Ceramic substrates, primarily composed of alumina (Al₂O₃) or aluminum nitride (AlN), are favored for their superior thermal and electrical properties in demanding environments. Alumina-based substrates offer a thermal conductivity of approximately 20-30 W/m·K, enabling effective heat spreading, while AlN variants achieve significantly higher values of 170-230 W/m·K, making them suitable for applications requiring rapid heat dissipation.[16][17] These materials also provide hermetic sealing to protect against moisture and contaminants, along with a coefficient of thermal expansion (CTE) of 3-5 ppm/°C for AlN and 6-8 ppm/°C for alumina, which closely matches silicon's CTE of about 2.6-4 ppm/°C to minimize thermomechanical stress.[18][19][16] Ceramic substrates are commonly employed in high-power or military applications, such as multi-chip modules, where reliability under extreme conditions is critical.[20] However, their higher manufacturing cost and inherent brittleness limit widespread adoption in cost-sensitive designs.[21] Organic substrates, typically laminates of epoxy resin reinforced with glass fiber (similar to FR-4), represent a more economical alternative with a thermal conductivity of around 0.3 W/m·K, sufficient for moderate heat loads but reliant on additional thermal vias or heat spreaders for enhanced dissipation.[22] These substrates are lighter in weight and exhibit a CTE of 15-20 ppm/°C, which, while mismatched with silicon, is better aligned with printed circuit boards to reduce assembly stresses.[23] Often using bismaleimide-triazine (BT) resin for improved performance, organic substrates are prevalent in consumer electronics due to their low cost and compatibility with high-volume production.[24][25] Plastic substrates, such as those in plastic pin grid array (PPGA) packages, build on organic bases through injection molding or encapsulation processes, incorporating epoxy or similar polymers to form a protective outer body while retaining the laminate core for interconnections.[24] This approach balances the cost-effectiveness and lightweight nature of organics with added mechanical durability against impacts and handling stresses, making plastic substrates suitable for mid-range applications where full ceramic robustness is unnecessary.[12] Selection of substrate materials for PGA packages hinges on specific thermal requirements, budgetary constraints, reliability needs, and manufacturing yield considerations. High-thermal-conductivity ceramics like AlN are prioritized for power-intensive uses to prevent overheating, whereas organics or plastics suffice for lower-power scenarios to optimize cost.[20] Reliability is enhanced by CTE matching to avoid cracking during thermal cycling, with ceramics offering better silicon compatibility than organics.[19] Additionally, manufacturing yield favors organics and plastics due to simpler processing, though ceramics excel in yield for precision multilayer routing in specialized cases.[21]

Pin Configurations

Pin grid array (PGA) packages typically feature a standard uniform rectangular array of pins arranged in rows and columns on the underside of the package, providing a reliable interface for socketed or soldered connections. The most common pitch for these pins is 2.54 mm (0.1 inch), though finer pitches of 1.27 mm (0.05 inch) are used in higher-density variants to accommodate increased input/output requirements. Power and ground pins are frequently positioned along the periphery of the array to simplify routing and improve electrical performance by leveraging outer-layer traces for distribution.[3] Staggered pin configurations, also known as staggered pin grid arrays (SPGA), offset alternate rows of pins to enhance pin density compared to a uniform grid at equivalent pitches, enabling higher I/O counts in the same footprint. This offset arrangement, often implemented with a 1.27 mm pitch, is particularly suited for high-I/O applications such as processors exceeding 600 pins, where it facilitates tighter packing while necessitating precise socket alignment to avoid insertion issues.[3][26] Stud pins represent a variant of PGA pins designed as short, collared cylindrical stubs protruding minimally from the package base, which reduces overall package height and minimizes fragility during handling and assembly. These stubs are commonly employed in modern low-profile PGA packages to maintain electrical connectivity while enabling surface-mount compatibility and lower profiles suitable for compact electronics.[27] Mechanically, PGA pins are engineered with lengths typically ranging from 3.0 to 3.3 mm for standard full-length designs, though some variants like micro-PGA have shorter pins at 1.2–1.3 mm, while stud pins have a mounting length of around 3.5 mm. Pin diameters generally fall between 0.4 and 0.6 mm, with precise tolerances such as 0.40–0.51 mm for plastic PGA (PPGA) types, ensuring compatibility with socket contacts. The tips of PGA pins are typically domed or rounded, featuring a conical taper and round chamfer (rather than flat), to ensure reliable electrical contact with the socket, center the pin during insertion, and prevent damage to socket contacts. Materials consist of alloys like Kovar or copper-based (e.g., CuZn37), finished with gold plating over nickel underlayers for corrosion resistance and reliable conductivity; these features, combined with controlled bending radii, help mitigate warping and maintain coplanarity during thermal cycling.[3][27] Pin density in PGA packages is determined by the grid dimensions, where a square n × n array theoretically supports up to n² pins, though practical counts are reduced by depopulated sites reserved for internal routing or thermal vias—for instance, certain FC-PGA designs achieve 370 pins within a footprint supporting up to a 19 × 19 grid, through optimized layouts including depopulation for routing. This approach balances I/O capacity with manufacturability, with higher counts like 615 pins achieved in micro-PGA (μPGA) using finer 1.27 mm staggered grids.[3]

Variants

Ceramic and Organic Packages

Ceramic Pin Grid Array (CPGA) packages feature a fully ceramic construction, providing hermetic sealing essential for high-reliability environments. These packages utilize multilayer cofired ceramics, manufactured through processes such as tape casting for green sheets, screen printing of conductive pastes, lamination, and high-temperature sintering to form a dense substrate with integrated vias and traces. The die is mounted centrally, wire-bonded, and enclosed with a metal or ceramic lid brazed for hermeticity, ensuring protection against moisture and contaminants in demanding applications like aerospace and military systems, including radiation-hardened integrated circuits.[28][7] Organic Pin Grid Array (OPGA) packages employ multilayer organic laminates, typically bismaleimide-triazine (BT) resin with copper traces, connected via solder-filled vias to protruding pins. Manufacturing involves standard printed circuit board techniques, including core preparation, laser drilling for vias, electroless copper plating, patterning, and pin insertion or soldering, followed by surface finishing for solderability. These packages are suited for commercial electronics requiring moderate reliability, offering a balance of performance and affordability, though they are non-hermetic and susceptible to moisture absorption, necessitating preconditioning per moisture sensitivity level (MSL) classifications during assembly. Enhanced signal integrity is achieved through build-up layers with finer line widths and controlled impedance.[29][30] A prominent example of an organic-based variant is the Plastic Pin Grid Array (PPGA), introduced by Intel in 1997 for the Pentium MMX processor using a 296-pin configuration. This package consists of a plastic-encapsulated organic substrate with a metal lid or heat slug for thermal spreading, manufactured via lamination of BT resin layers, via formation, pin press-fit or solder attachment, die attachment with epoxy, gold wire bonding, and overmolding for environmental protection. The 296-pin PPGA measures approximately 49.5 mm square with a 3.0 mm body thickness (including heat slug) and supports Socket 5 interfacing for consumer CPUs in the 1990s and early 2000s.[24][12][31] Comparatively, CPGA packages are roughly twice the weight of OPGA or PPGA equivalents (e.g., 29 g versus 18 g for a 296-pin configuration) due to the denser ceramic materials, and they incur significantly higher manufacturing costs from custom tooling and sintering processes. Reliability for CPGA includes hermetic sealing that withstands extreme conditions, such as 1000 thermal cycles from -55°C to 125°C, while organic packages like OPGA and PPGA undergo MSL testing (typically Level 3) to mitigate risks from humidity and reflow soldering, with lower overall lifecycle costs for non-critical applications.[24][28][32]

Specialized Layouts

The Reversible Pin Grid Array (rPGA) is a specialized variant of the PGA package optimized for mobile computing applications, featuring pins arranged on the substrate to facilitate zero insertion force (ZIF) socket mating. Introduced by Intel for its first-generation Core i7 mobile processors in 2009, the rPGA-989 socket (compatible with rPGA-988A processors) supports up to 988 pins at a 1 mm pitch, enabling higher pin density in compact form factors while minimizing assembly risks through symmetric pin layouts that reduce the need for precise orientation during insertion. This design has been widely adopted in laptop processors, such as those in the Nehalem architecture series, to balance thermal performance and electrical connectivity in thin profiles.[33] Staggered pin variants of the PGA, known as Staggered Pin Grid Array (SPGA), incorporate offset pin rows to achieve greater pin density without increasing overall package size, making them suitable for high-performance computing environments. In SPGA layouts, pins are arranged in alternating positions within the grid, allowing closer spacing compared to standard aligned PGAs while maintaining mechanical stability. A prominent example is the AMD Opteron server processor's 940-pin configuration, which utilizes a staggered 1.27 mm pitch grid to support multi-core architectures with extensive I/O requirements, as specified in AMD's socket design guidelines. This approach enhances signal integrity and routing flexibility in dense server boards.[34][35] Stud and low-profile PGA variants employ shortened pins or stud-like protrusions to minimize vertical height, typically achieving total package Z-heights around 5 mm, which is critical for space-constrained embedded systems. These designs use selective plating techniques, such as gold-over-nickel deposition on pin tips, to ensure reliable electrical contact and corrosion resistance during manufacturing. For instance, low-profile PGA sockets with 0.60 mm pin protrusion above the PCB are common in industrial embedded applications, where they interface with microcontrollers requiring robust yet compact connectivity. Manufacturing involves precision turning of short pins followed by selective electroplating to target only the contact areas, reducing material costs and improving yield.[36][37] Other specialized PGA layouts include hybrids combining elements of Land Grid Array (LGA) contacts with pin structures for enhanced thermal and electrical performance in niche high-speed applications during the 2020s. Fine-pitch PGAs with pitches below 1 mm, such as 0.8 mm variants, enable integration in advanced networking and AI accelerators, though they remain less common due to pin fragility concerns. These evolutions often adhere to JEDEC outline standards adapted for PGA families, ensuring interoperability in evolving semiconductor ecosystems.[38][39]

Integration and Assembly

Chip Mounting Techniques

The primary methods for mounting the semiconductor die to the pin grid array (PGA) substrate involve wire bonding and flip-chip techniques, each offering distinct advantages in electrical connectivity, thermal management, and manufacturing yield. Wire bonding remains the most common approach for PGA packages due to its reliability and cost-effectiveness in connecting peripheral die pads to substrate traces. In contrast, flip-chip mounting enables higher I/O density and shorter interconnect paths, reducing signal inductance, particularly in high-performance applications. Other specialized techniques, such as tape-automated bonding (TAB), are employed for fine-pitch requirements, while adhesive die attachment suits low-power scenarios. Wire bonding connects the die's bond pads to the substrate's traces using fine metallic wires, typically gold or aluminum with diameters ranging from 25 to 50 µm. Gold wires, often 18 to 40 µm in diameter, are preferred for their corrosion resistance and ductility, while aluminum wires provide a cost-effective alternative for less demanding applications. The process employs ultrasonic or thermosonic methods: ultrasonic bonding uses high-frequency vibrations (around 60-120 kHz) combined with pressure to form wedge or ball bonds without heat, whereas thermosonic bonding adds moderate heat (150-200°C) to enhance intermetallic formation and bond strength. Wire loops typically exhibit heights of 0.2 to 0.5 mm to accommodate substrate topography and prevent shorts, with the die first secured to the substrate using silver-filled epoxy adhesive for mechanical stability. This method ensures robust electrical connections but introduces higher inductance compared to direct attachment approaches. Flip-chip mounting inverts the die and attaches it face-down to the substrate via solder bumps, such as in IBM's Controlled Collapse Chip Connection (C4) process using Pb/Sn alloys. Solder bumps, formed on the die pads through electroplating or evaporation followed by reflow, collapse under controlled heat and pressure during attachment, creating reliable metallurgical joints with heights of 50-100 µm. To enhance mechanical reliability and mitigate thermal expansion mismatches between the die (CTE ~3 ppm/°C) and organic substrates (CTE ~15-20 ppm/°C), an epoxy underfill is dispensed around the bumps and cured, filling voids to prevent delamination and fatigue. This technique significantly shortens electrical paths, reducing inductance by up to 50% relative to wire bonding, and has been widely adopted in high-performance PGAs, such as Intel's FC-PGA for Pentium processors. Alignment precision is critical, with tolerances below 5 µm—often achieving 3 µm in production—to ensure bump-to-trace registration and high yield. Alternative techniques include tape-automated bonding (TAB) for fine-pitch applications in high-pin-count ceramic PGAs, where the die bonds to a flexible polyimide tape with copper leads (pitch as low as 50 µm) before outer lead attachment to the substrate, enabling up to 820 I/O connections. For low-power devices, adhesive die attach uses non-conductive epoxies to simply secure the die without electrical interconnects, minimizing thermal stress in applications with power dissipation under 1 W. Thermal considerations across methods emphasize void-free underfill or encapsulation to avoid hotspots and delamination, with cure temperatures controlled below 150°C to preserve substrate integrity. The overall process sequence begins with die placement on the substrate using automated pick-and-place tools for precise positioning (accuracy ~10 µm). Bonding follows—wire formation or solder reflow—monitored for parameters like bond pull strength (>5 g for 25 µm wires) and joint integrity. Encapsulation with silica-filled epoxy molding compound protects the assembly, followed by curing and inspection. Yield is influenced by factors such as alignment tolerance (<5 µm for flip-chip to achieve >99% first-pass yield) and process controls to minimize defects like non-stick bumps or wire sweeps.

Socket and Board Interfacing

Pin grid array (PGA) packages interface with printed circuit boards (PCBs) primarily through specialized sockets that accommodate the array of pins on the package underside. Common socket types include zero insertion force (ZIF) designs, which employ a lever or cam mechanism to gently clamp the pins without applying pressure during insertion or removal, facilitating easy installation and replacement of processors. For instance, the Intel PGA370 socket, used for 370-pin packages in Pentium III and Celeron processors, features a single-lever ZIF actuation for reliable connectivity in desktop and server applications. Low-insertion-force (LIF) sockets, often equipped with spring-loaded or multi-finger contacts, provide an alternative for testing scenarios where minimal force—typically 12.5 g per pin or less—is required to avoid stressing high-pin-count arrays exceeding 250 pins.[1][40] The interfacing process begins with aligning the PGA package pins with the socket's contact holes, followed by insertion using the actuation mechanism to secure the connection. Pin insertion tolerances are tightly controlled, typically at ±0.05 mm, to ensure precise mating and prevent misalignment in high-density grids spaced at 1.27 mm or 2.54 mm. Socket designs incorporate features such as tapered entries and precision-machined contacts to guide pins smoothly. The tips of PGA pins are typically domed or rounded, featuring a conical taper and round chamfer. This pin tip design, combined with the socket's tapered entries, facilitates smooth alignment, self-centering of the pin within the contact, reliable electrical contact, and protection of the socket contacts from damage during insertion, while package and socket geometries, including beveled corners on the package, aid in orientation to avoid rotation during mating. Post-assembly, burn-in testing is commonly performed using dedicated ZIF sockets to stress the interface under elevated temperatures and voltages, identifying potential defects before full deployment.[26][40][41][42][43] On the board side, sockets are attached to the PCB via surface-mount technology (SMT) soldering for ZIF types or through-hole soldering for LIF variants, with socket pins or tails connecting directly to PCB vias for electrical routing. To maintain signal integrity in high-speed applications, PCB traces linked to these vias are designed with controlled impedance, typically 50–100 Ω, to minimize reflections and crosstalk in microprocessor interfaces. Thermal management is enhanced by placing thermal vias beneath key socket pins, particularly ground or power pins, to conduct heat from the package to inner PCB layers or external sinks, improving dissipation in power-intensive setups.[1][44][45] Reliability in socket-board interfacing is ensured through design features that limit pin deflection to a maximum of 10° during handling or insertion, reducing bending risks in arrays with delicate leads. Sockets are rated for a minimum lifecycle of 100 insertion/extraction cycles, with low-force contacts maintaining contact resistance below 10 mΩ throughout. Qualification follows standards such as EIA-364, which outlines environmental and mechanical tests including thermal shock, vibration (10–500 Hz at 10 g), and shock (50 g), to verify performance under operational stresses.[46][47][48]

Applications and Performance

Typical Uses

Pin grid array (PGA) packages find their primary application in microprocessors for desktop and server environments, where the socketed design facilitates upgradability and maintenance. The Intel 80486, introduced in 1989, exemplifies this use with its 168-pin PGA configuration for 5-volt designs, enabling high-performance computing in early personal computers.[10] Similarly, AMD's K6 family of processors, launched in the late 1990s, utilized 321-pin ceramic PGA packages compatible with Socket 7 motherboards, supporting speeds up to 550 MHz in consumer and embedded computing setups.[49] In embedded systems, PGA packages support industrial controls and networking equipment, providing robust I/O connectivity for complex signal routing.[38] The removable pin grid array (rPGA) variant extends this to mobile computing, particularly in laptops, where socketed designs like Intel's rPGA 988B allow processor upgrades in models supporting dual-core Intel Core i3 series chips.[50] Ceramic PGA packages are favored in high-reliability sectors due to their hermetic sealing and durability, including aerospace, military, and telecommunications applications. These packages house radiation-tolerant integrated circuits for satellites and defense systems, ensuring performance in harsh radiation environments.[51][38] As of 2025, PGA persists in niche modern roles, such as legacy server maintenance, custom application-specific integrated circuits (ASICs), repairable systems in medical devices, and high-reliability applications in aerospace and defense.[38][51]

Advantages and Limitations

One key advantage of Pin Grid Array (PGA) packages is their ability to support high pin counts, typically ranging from 28 to over 800 pins in advanced designs, enabling dense I/O connectivity for complex integrated circuits.[52] This configuration facilitates socketability, allowing easy installation, removal, and upgrades of components without soldering, which enhances maintainability in systems requiring frequent processor changes.[53] Additionally, the protruding pins provide effective thermal paths from the die to the board or heatsink, improving heat dissipation compared to surface-mount alternatives in certain applications.[54] PGA packages also offer mechanical robustness in the Z-direction due to the pin structure, which absorbs shocks and vibrations better than flat-pad designs, reducing stress on solder joints.[26] Furthermore, in configurations with short pins or optimized layouts, PGA can exhibit lower inductance than traditional wire bonding, aiding signal integrity in moderate-speed operations.[55] Despite these benefits, PGA packages have notable limitations, including a taller profile of approximately 5-10 mm due to pin length, compared to about 1 mm for Ball Grid Array (BGA) packages, which increases overall system height and limits use in compact devices.[56] The pins are prone to fragility, with risks of bending or breaking during handling or insertion, potentially leading to connection failures.[57] Socket-based implementations add higher costs, as specialized PGA sockets are more expensive than direct soldering methods used in BGA.[58] Moreover, PGA requires a larger PCB footprint to accommodate through-hole pins, complicating board layout compared to surface-mount options.[59] In terms of signal integrity, PGA's longer pins introduce higher inductance, approximately 1-3 nH per pin, which can cause issues at frequencies above 1 GHz by increasing crosstalk and reflections.[55] Compared to BGA, PGA offers lower I/O density, around 15-60 pins/cm² depending on pitch, versus over 200 pins/cm² for fine-pitch BGA, making it less suitable for ultra-high-density applications.[38] Relative to Land Grid Array (LGA), PGA is similar in socketability but uses protruding pins instead of flat pads, resulting in bulkier assemblies, while LGA avoids pin fragility at the cost of more precise alignment needs.[26] BGA, being soldered, provides a smaller form factor and better high-frequency performance but lacks the easy replaceability of PGA.[60] To mitigate these drawbacks, variants like removable PGA (rPGA) are employed in mobile systems, offering socketed upgradability in thinner profiles suitable for laptops.[61] As of 2025, PGA remains relevant in upgradable desktop and server systems, even as soldered packages like BGA dominate consumer electronics for their compactness and cost efficiency.[38]

References

  1. Pin Grid Array (PGA) Sockets - TE Connectivity
  2. Package Type Guide for Intel® Desktop Processors
  3. [PDF] Pinned Packaging - Intel
  4. The Evolution of IC Packaging | Advanced PCB Design Blog
  5. https://ieeexplore.ieee.org/document/906346
  6. [PDF] EIAJ EDR-7323A - 1 -
  7. [PDF] Designing Pin Grid Array Ceramic Packages For High Performance ...
  8. [PDF] Introduction to the 80386
  9. [PDF] 80486DX2-66-Intel-datasheet-7086155.pdf - Octopart
  10. [PDF] Volume 1: Pentium Processor Data Book - Bitsavers.org
  11. [PDF] An Introduction to Plastic Pin Grid Array (PPGA) Packaging
  12. [PDF] Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel ...
  13. [PDF] PACKAGING
  14. What is PGA Package Substrate?
  15. Alumina | CoorsTek Technical Ceramics
  16. Aluminum Nitride (AlN) Substrates | Products | MARUWA CO., LTD.
  17. What Are "Ceramic Packages"? - Kyocera
  18. https://ieeexplore.ieee.org/document/626950/
  19. Thermal conductivity of Aluminum nitride: Things to know
  20. PCB Substrates Ceramic or Organic? Printed Circuit Board ... - ACDi
  21. What is the Thermal Conductivity of Different PCBs [Solved]
  22. Impact of temperature-dependent die warpage on TIM1 thermal ...
  23. [PDF] An Introduction to Plastic Pin Grid Array (PPGA) Packaging
  24. A Comprehensive Guide to BGA Substrates - Highleap Electronic
  25. PGA Vs LGA: Types, Keyfeatures and Advantage - ELEPCB
  26. [PDF] MOULDED, PLASTIC PGA PACKAGES - Periodica Polytechnica
  27. [PDF] Packaging Influences Microprocessor Cost: 9/13/93 - CECS
  28. None
  29. [PDF] Comparison Between Multilayer Ceramic and Organic Package ...
  30. [PDF] thermo-mechanical reliability models for life ... - Auburn University
  31. Reversed pin grid array socket for the Intel Core-i7 processors - EE Times
  32. [PDF] AMD Socket 940 Design Specification
  33. The Big Processor Guide - Sockets - 10stripe
  34. PGA Pin Grid Array Super Low Profile - E-tec Interconnect
  35. Selective Gold Plating: Precision Solutions - Electro-Spec
  36. Pin-Grid Array | Advanced PCB Design Blog | Cadence
  37. Plastic Chip Carrier (PCC) Family .050 inch Lead Spacing ... - JEDEC
  38. [PDF] PIN GRID ARRAY SOCKETS - Mill-Max
  39. US6431878B1 - Socket for PGA package - Google Patents
  40. PGA ZIF Test & Burn-in Socket for Any Footprint on Std 8x8 to 21x21 ...
  41. How Thermal Vias Enhance Heat Dissipation in PCBs - Sierra Circuits
  42. Controlled Impedance Routing for Signal Integrity | Cadence
  43. Why aren't components in DIP package shipped with straight pins?
  44. [PDF] PGA / BGA / PLCC SOCKETS - March Electronics
  45. EIA-364: Electrical Connector Performance Test Standards
  46. [PDF] AMD-K6-2E Embedded Processor Data Sheet
  47. [PDF] PowerPC 601 and Alpha 21064: a tale of two RISCs - Computer
  48. How to Identify Either my Laptop Socket is BGA or rPGA?
  49. Pin Grid Array (PGA) - Find TI packages - Texas Instruments
  50. Fine pitch TAB assembly technology for 820 pin count ceramic PGA ...
  51. LGA vs. PGA: What's the Difference and Which is Better? - PCBasic
  52. Ceramic Pin Grid Array | Evergreen Semiconductor Materials, Inc.
  53. [PDF] ECE 546 Lecture 04 Resistance, Capacitance, Inductance
  54. Pin Grid Array (PGA) vs Ball Grid Array (BGA) Guide - PCBASAIL
  55. LGA vs. PGA: What's the Difference and Which is Better? - PCBA Store
  56. LGA vs PGA - What's the Difference - IBE Electronics
  57. BGA, PGA, LGA - What do the different grid arrays mean? - spo-comm
  58. Benefits of Using Ball Grid Arrays | Creative Hi-Tech Ltd
  59. LGA vs. PGA vs. BGA - PCBX
  60. US6803650B2 - Semiconductor die package having mesh power and ground planes
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