Hubbry Logo
Platform Controller HubPlatform Controller HubMain
Open search
Platform Controller Hub
Community hub
Platform Controller Hub
logo
8 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
Platform Controller Hub
Platform Controller Hub
Platform Controller Hub
View on Wikipedia
from Wikipedia
Block diagram of the Platform Controller Hub–based chipset architecture, including an Integrated Memory Controller (IMC) in the CPU
An Intel DH82H81 PCH with its die exposed

The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips–a northbridge and southbridge, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I⁠/⁠O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset since the release of the Zen architecture in 2017.[1] AMD no longer uses its equivalent for the PCH, the Fusion controller hub (FCH).

Overview

[edit]
Intel Cannon Lake Platform Controller Hub die

The PCH architecture supersedes Intel's previous Hub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and the motherboard. Under the Hub Architecture, a motherboard would have a two-piece chipset consisting of a northbridge chip and a southbridge chip. Over time, the speed of CPUs kept increasing but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.[2]

As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge and its functions are now eliminated completely: The memory controller, PCI Express lanes for expansion cards and other northbridge functions are now incorporated into the CPU die as a system agent (Intel) or packaged in the processor on an I⁠/⁠O die (AMD Zen 2).

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions, replacing it. The system clock was previously a connection to a dedicated chip but is now incorporated into the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is used only when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets. AMD's chipsets instead use several PCIe lanes to connect with the CPU while also providing their own PCIe lanes, which are also provided by the processor itself.[3][4] The chipset also contains the Nonvolatile BIOS memory.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

This style began in Nehalem and will remain for the foreseeable future, through Cannon Lake.

Phase-out

[edit]

Beginning with ultra-low-power Haswells and continuing with mobile Skylake processors, Intel incorporated the southbridge IO controllers into the CPU package, eliminating the PCH for a system in package (SOP) design with two dies; the larger die being the CPU die, the smaller die being the PCH die.[5] Rather than DMI, these SOPs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.[needs update]

AMD's FCH has been discontinued since the release of the Carrizo series of CPUs as it has been integrated into the same die as the rest of the CPU.[6] However, since the release of the Zen architecture, there's still a component called a chipset which only handles relatively low speed I⁠/⁠O such as USB and SATA ports and connects to the CPU with a PCIe connection. In these systems all PCIe connections are routed directly to the CPU.[7] The UMI interface previously used by AMD for communicating with the FCH is replaced with a PCIe connection. Technically the processor can operate without a chipset; it only continues to be present for interfacing with low speed I⁠/⁠O.[8] AMD server and laptop CPUs adopt a self contained system on chip (SoC) design instead which doesn't require a chipset.[9][10][11]

Ibex Peak

[edit]
"Ibex Peak" redirects here. For the mountain in Canada, see Ibex Peak (British Columbia). For the mountain in Montana, see Ibex Peak (Montana).

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations:

Issues

[edit]
  • Bogus USB ports will be detected by desktop PCHs equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Applying AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
  • Bogus USB ports will be detected by mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Applying AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
  • Reading the HPET comparator timer immediately after a write returns the old value (erratum 14)
  • SATA 6 Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

Langwell

[edit]

Langwell is the codename of a PCH in the Moorestown MID/smartphone platform.[12][13] for Atom Lincroft microprocessors.

This has the following variations:

  • AF82MP20 (PCH MP20)
  • AF82MP30 (PCH MP30)

Tiger Point

[edit]
Intel CG82NM10

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations:

Topcliff

[edit]

Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCIe (vs. DMI as other PCHs do).

This has the following variations:

Cougar Point

[edit]
See also: LGA 1155 § Original Sandy Bridge chipsets, and List of Intel chipsets § LGA 1155

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, workstation, and server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:

Issues

[edit]

In the first month after Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and optical drives. The bug was present in revision B2 of the chipsets, and was fixed with B3. Z68 did not have this bug, since the B2 revision for it was never released. 6 Gbit/s ports were not affected. This bug was especially a problem with the H61 chipset, which only had 3 Gbit/s SATA ports. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[14][15]

Nearly all produced motherboards using Cougar Point chipsets were designed to handle Sandy Bridge, and later Ivy Bridge, processors. ASRock produced one motherboard for LGA 1156 processors, based on P67 chipset, the P67 Transformer. It exclusively supports Lynnfield Core i5/i7 and Xeon processors, using LGA 1156 socket. After revision B2 of Cougar Point chipsets was recalled, ASRock decided not to update the P67 Transformer motherboard, and was discontinued. Some small Chinese manufacturers are producing LGA 1156 motherboards with H61 chipset.

Whitney Point

[edit]

Whitney Point is the codename of a PCH in the Oak Trail tablet platform for Atom Lincroft microprocessors.

This has the following variations:

Panther Point

[edit]
See also: LGA 1155 § Ivy Bridge chipsets
intel BD82HM77 PCH Panther Point

Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets (except PCH HM75) have integrated USB 3.0.[16]

This has the following variations:

Cave Creek

[edit]

Cave Creek is the codename of the PCH most closely associated with Crystal Forest platforms and Gladden[17] or Sandy Bridge-EP/EN[18] processors.

  • DH8900 (PCH 8900) Communications
  • DH8903 (PCH 8903) Communications
  • DH8910 (PCH 8910) Communications
  • DH8920 (PCH 8920) Communications

Patsburg

[edit]

Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation using the LGA 2011 socket. It was initially launched in 2011 as part of Intel X79 for the desktop enthusiast Sandy Bridge-E processors in Waimea Bay platforms.[19] Patsburg was then used for the Sandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded as Xeon E5-2600 series) launched in early 2012.[20]

Launched in the fall of 2013, the Ivy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.[21][22]

Patsburg has the following variations:

Coleto Creek

[edit]

Coleto Creek is the codename of the PCH most closely associated with Highland Forest platforms and Ivy Bridge-EP[23] processors.

  • DH8925 (PCH 8925) Communications
  • DH8926 (PCH 8926) Communications
  • DH8950 (PCH 8950) Communications
  • DH8955 (PCH 8955) Communications

Lynx Point

[edit]
See also: LGA 1150 § Haswell chipsets
"Lynx Point" redirects here. For the cat coloration, see Point coloration.

Lynx Point is the codename of a PCH in Intel 8 Series chipsets, most closely associated with Haswell processors with LGA 1150 socket.[24] The Lynx Point chipset connects to the processor primarily over the Direct Media Interface (DMI) interface.[25]

The following variants are available:[26]

In addition the following newer variants are available, additionally known as Wildcat Point, which also support Haswell Refresh processors:[27]

  • DH82H97 (PCH H97) Desktop Home
  • DH82Z97 (PCH Z97) Combined desktop base and home

Issues

[edit]

A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost.[28][29] This issue is corrected in C2 stepping level of the Lynx Point chipset.[30]

Wellsburg

[edit]

Wellsburg is the codename for the C610-series PCH, supporting the Haswell-E (Core i7 Extreme), Haswell-EP (Xeon E5-16xx v3 and Xeon E5-26xx v3), and Broadwell-EP (Xeon E5-26xx v4) processors. Generally similar to Patsburg, Wellsburg consumes only up to 7 W when fully loaded.[31]

Wellsburg has the following variations:

Sunrise Point

[edit]
See also: LGA 1151 § Skylake chipsets

Sunrise Point is the codename of a PCH in Intel 100 Series chipsets, most closely associated with Skylake processors with LGA 1151 socket.

The following variants are available:[32]

  • GL82C236 (PCH C236) Workstation/Server
  • GL82H110 (PCH H110) Desktop Home
  • GL82H170 (PCH H170) Desktop Home (Note the datasheet linked one that page is incorrect, see via PCH HM170 below)
  • GL82Z170 (PCH Z170) Combined desktop base and home
  • GL82B150 (PCH B150) Desktop Office
  • GL82Q150 (PCH Q150) Desktop Office
  • GL82Q170 (PCH Q170) Desktop Office
  • GL82HM170 (PCH HM170) Mobile Home
  • GL82CM236 (PCH CM236) Mobile Workstation
  • GL82QM170 (PCH QM170) Mobile Office

Union Point

[edit]
See also: LGA 1151 § Kaby Lake chipsets

Union Point is the codename of a PCH in Intel 200 Series chipsets, most closely associated with Kaby Lake processors with LGA 1151 socket.

The following variants are available:[33]

Lewisburg

[edit]

Lewisburg is the codename for the C620-series PCH, supporting LGA 2066 socketed Skylake-X/Kaby Lake-X processors ("Skylake-W" Xeon).

Lewisburg has the following variations:

  • EY82C621 (PCH C621), intended for servers and workstations
  • EY82C622 (PCH C622), intended for servers and workstations
  • EY82C624 (PCH C624), intended for servers and workstations
  • EY82C625 (PCH C625), intended for servers and workstations
  • EY82C626 (PCH C626), intended for servers and workstations
  • EY82C627 (PCH C627), intended for servers and workstations
  • EY82C628 (PCH C628), intended for servers and workstations

Basin Falls

[edit]

Basin Falls is the codename for the C400-series PCH, supporting Skylake-X/Kaby Lake-X processors (branded Core i9 Extreme and "Skylake-W" Xeon). Generally similar to Wellsburg, Basin Falls consumes only up to 6 W when fully loaded.

Basin Falls has the following variations:

Cannon Point

[edit]
See also: LGA 1151 § Coffee Lake chipsets (300 series)

Cannon Point is the codename of a PCH in Intel 300 Series chipsets, most closely associated with Coffee Lake processors with LGA 1151 socket.[34]

The following variants are available:[35]

Comet Lake PCH

[edit]

Rocket Lake PCH

[edit]

Alder Lake PCH

[edit]
See also: Alder Lake chipsets (600 series)

Raptor Lake PCH

[edit]
See also: Raptor Lake chipsets (700 series)

See also

[edit]

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Platform Controller Hub

View on Grokipedia
from Grokipedia
The Platform Controller Hub (PCH) is a family of single-chip components developed by that functions as the central I/O controller and system management unit in its chipset architectures for desktop, mobile, and server platforms, consolidating functions previously divided between Northbridge and Southbridge chips. It connects the processor to peripherals via the (DMI), a high-speed bidirectional link operating at up to 16 GT/s in recent implementations, while handling data paths, clocking, interrupt management, and power delivery. Introduced with the Intel 5 Series Chipset to support Core processor families, the PCH enables scalable connectivity through interfaces such as (up to 28 lanes, including up to 20 Gen 4, in modern variants), USB (up to 14 USB 2.0 ports and up to 14 USB 3.2 ports, including Gen 2x2 support), (up to 8 ports at 6 Gb/s), High Definition Audio, and legacy options like LPC and SMBus. It incorporates advanced power management compliant with standards (up to Revision 5.0a), supporting sleep states from S0 to S5 and Deep Sx low-power modes, along with thermal monitoring via on-die sensors ranging from -40°C to 110°C. The PCH integrates Intel-specific technologies for enhanced performance and security, including Rapid Storage Technology (RST) for AHCI/RAID storage, Virtualization Technology for Directed I/O (VT-d), Trusted Execution Technology (TXT), and the Management Engine (ME) for remote provisioning and firmware-based security. Across generations—from the 100 Series for Skylake processors to the 800 Series for Arrow Lake—the PCH has evolved to support emerging standards like eSPI for embedded controllers, for wireless connectivity, and Integrated Sensor Hubs for low-power sensor aggregation, ensuring compatibility with high-bandwidth peripherals and efficient platform operation.

Overview

Definition and Role

The Platform Controller Hub (PCH) is a centralized chipset component developed by that integrates multiple (I/O), connectivity, and power management functions into a single chip, serving as the primary I/O controller for Intel-based computing platforms. It acts as the successor to the earlier I/O Controller Hub (ICH), which functioned as a southbridge in traditional architectures, by consolidating these responsibilities to enhance and reduce hardware complexity. The PCH's core roles include managing a variety of peripheral interfaces and system resources, such as USB ports for device connectivity, for storage devices, PCIe for expansion cards and high-speed links, LPC for legacy peripherals, high-definition audio for multimedia output, for networking, and comprehensive features to optimize energy use across system states. These functions enable seamless communication between the (CPU) and external devices, ensuring reliable data transfer and support for modern platform requirements without relying on additional discrete chips. The PCH integrates with the CPU through the (DMI), a high-speed serial link that provides dedicated bandwidth for I/O traffic, distinct from the CPU's direct handling of memory control and graphics, which were previously managed by a separate northbridge component. Introduced in 2009 with the 5 Series chipsets (codenamed Ibex Peak), the PCH was designed to simplify design by minimizing the overall chip count and interconnects, thereby improving scalability, reducing costs, and facilitating more compact system layouts in desktops, laptops, and servers.

Historical Context and Introduction

The I/O Controller Hub (ICH), introduced by in the late as part of the company's Hub , served as the southbridge component in traditional designs, managing operations such as USB, , and PCI connections while interfacing with the northbridge via a dedicated hub link. This , which began evolving in the and persisted through the 2000s, addressed the growing complexity of PC peripherals but faced limitations as processor performance advanced, requiring higher inter-chip bandwidth to handle escalating demands from integrated , storage, and networking. In 2008, Intel transitioned to the Platform Controller Hub (PCH) as an evolution of the Hub Architecture, debuting it alongside the Nehalem-based Core i7 processors on November 17, with the high-end X58 chipset (codenamed Tylersburg). The X58 platform paired the Nehalem CPU—featuring an integrated —with an I/O Hub (IOH) that embodied the initial PCH concept, connected via the new (DMI) at up to 10 Gb/s to support the processor's QuickPath Interconnect (QPI) and offload peripheral management from the CPU die. This shift was driven by the need for greater bandwidth efficiency in multi-core systems, allowing the CPU to prioritize computational performance over I/O tasks. The full realization of the PCH as a single-chip solution arrived in 2009 with the rollout of the 5 Series chipsets (codenamed Ibex Peak), starting in , which eliminated the separate northbridge entirely for mainstream platforms and centralized I/O control in the PCH connected directly to the CPU via DMI. By consolidating functions like PCIe lanes, SATA ports, and USB controllers into one hub, the PCH enabled scalable platform designs that have underpinned Intel's x86 architectures ever since.

General Architecture

The Platform Controller Hub (PCH) serves as a centralized I/O controller in platforms, integrating multiple peripheral interfaces and system management functions into a single chip to offload tasks from the CPU. At its core, the PCH architecture features a block diagram centered around flexible high-speed I/O (HSIO) lanes that can be configured for various protocols, including multiple ports (up to 8 in recent variants) supporting 6 Gb/s speeds with AHCI mode, up to 14 USB 2.0 ports with additional high-speed USB 3.x/3.2 support via xHCI, numerous PCIe lanes (up to 28 Gen 3/4 in modern designs) distributed across root ports, and an integrated LAN controller compliant with for 10/100/1000 Mbit/s connectivity. These elements connect peripherals to the system while minimizing external components, enabling efficient data routing and resource sharing across the platform. The PCH also integrates the (ME) for firmware-based security, remote provisioning, and features like (TXT) and Virtualization Technology for Directed I/O (VT-d). Power management in the PCH is handled through support for Advanced Configuration and Power Interface () states, including S0 (full on), S3 (suspend-to-RAM), S4 (hibernate), and S5 (soft off), along with low-power modes like S0ix for rapid resume and Deep Sx for extended idle efficiency. Thermal monitoring is facilitated by the (PECI), a single-wire serial bus that allows real-time temperature reporting from the CPU and other components to the PCH, enabling proactive throttling and fan control to maintain system stability. These features ensure compliance with power standards while optimizing energy use in varying workloads. The PCH communicates with the CPU via the (DMI) protocol, specifically versions 2.0 and 3.0, which provide a point-to-point serial link with up to 8 GT/s bandwidth across x4 or x8 lanes, supporting bidirectional data transfer at rates up to approximately 8 GB/s in aggregate (3.94 GB/s per direction for DMI 3.0 x8). Additionally, the architecture incorporates integrated (GPIO) pins for flexible system signaling and wake events, a (SMBus) version 2.0 operating at 100 kHz for low-speed device communication compatible with , and (SPI) flash interfaces for secure storage and execution, typically supporting up to 33 MHz clock speeds and multiple flash devices. The PCH evolved from earlier I/O Controller Hub (ICH) designs by consolidating more functions into a root complex-like structure. The shift toward on-package and system-on-chip (SoC) integration of I/O functions began with Intel's processors in 2023, particularly in mobile platforms, where the traditional discrete Platform Controller Hub (PCH) was replaced by an integrated I/O tile within the package. This I/O tile serves as an extension of the SoC tile, handling physical layer interfaces such as USB, , and PCIe endpoints without requiring a separate motherboard-mounted PCH, thereby reducing latency, power consumption, and board space in thin-and-light laptops. In contrast, discrete PCH designs remain essential for desktop and server platforms to support expansive I/O configurations and upgradability. For instance, Intel's Arrow Lake processors, launched in 2024, pair with the 800 Series chipset family, which functions as a discrete PCH embedded on the to manage connectivity for peripherals, storage, and networking across , , and enterprise segments. This setup provides up to 34 PCIe lanes and enhanced USB support, ensuring robust performance in high-end desktop environments. As of November 2025, hybrid models continue to dominate Intel's portfolio, with integrated I/O tiles in mobile SoCs such as Lunar Lake (launched 2024) and the forthcoming Panther Lake (expected late 2025/early 2026), while discrete PCHs persist in desktop variants such as Arrow Lake (2024) and its anticipated refresh (expected 2026). However, Intel's broader roadmap prioritizes chiplet-based architectures that minimize reliance on separate I/O hubs by embedding more functions directly into CPU packages, aiming for greater efficiency and scalability in AI-driven computing. Looking ahead, Nova Lake platforms expected in 2026 represent a potential milestone in this evolution, with advanced designs likely absorbing traditional PCH functions into dedicated CPU tiles to streamline integration and reduce external dependencies in both desktop and mobile systems, according to Intel's roadmap as of October 2025. This approach aligns with Intel's emphasis on disaggregated for future AI PCs and applications.

Desktop PCH Variants

Ibex Peak

Ibex Peak represents the first implementation of Intel's Platform Controller Hub (PCH) architecture for desktop systems, introduced as part of the 5 Series chipset family. Launched in September 2009 with the P55 variant, followed by H55 and Q57 models in January 2010, it marked a shift from previous northbridge-southbridge designs by consolidating I/O functions into a single PCH chip connected to the CPU via (DMI) 2.0. Key features of the Ibex Peak PCH include support for six ports operating at 3 Gb/s speeds, enabling reliable storage connectivity for consumer and business applications. It also provides up to 12 USB 2.0 ports for peripheral expansion, integrated capabilities through an onboard MAC (typically paired with an external PHY like the 82577), and DMI 2.0 interface running at 2.5 GT/s for high-bandwidth communication between the PCH and processor. These elements allowed for a more streamlined layout compared to prior generations, reducing component count while maintaining essential I/O performance. The chipset was designed to support first-generation processors based on the Nehalem and Westmere microarchitectures, including the Core i7, i5, and i3 series on the socket. Specific variants like the P55 targeted enthusiast builds with discrete graphics, while H55 suited systems with integrated graphics, and Q57 focused on business stability with features like support. This compatibility enabled the transition to the Lynnfield (Nehalem) and Clarkdale (Westmere) CPUs, powering early 32nm desktop platforms. Early deployments of Ibex Peak encountered USB 2.0 controller instability, where ports could stall under bulk or control traffic loads, leading to system freezes or unresponsive devices. This issue stemmed from errata in the chipset's USB implementation and affected various 5 Series configurations. addressed it through updates released in 2010, which incorporated fixes to restore stability without requiring hardware replacement.

Cougar Point

The Cougar Point, codenamed for Intel's 6 Series chipsets, represents the second-generation desktop Platform Controller Hub (PCH), released in January 2011 alongside the family of processors. It was designed to interface with 2nd-generation i3, i5, and i7 processors via the socket and a (DMI) link operating at up to 20 Gb/s full duplex. Key desktop variants include the H67 (emphasizing integrated graphics without ) and Z68 (adding support, via , and flexible graphics switching between integrated and discrete GPUs). These chipsets marked a step forward in I/O capabilities, building on the prior Ibex Peak generation by enhancing storage and expansion options while maintaining compatibility with the evolving desktop ecosystem. A hallmark upgrade in Cougar Point was its storage configuration, featuring six SATA ports: two at 6 Gb/s (SATA 600) for high-speed SSDs and four at 3 Gb/s (SATA 300), with support for AHCI mode, hot-plug, and optional RAID on Z68 variants. For connectivity, it provided up to 14 USB 2.0 ports (configurable to 10-14 depending on the SKU) across two or four EHCI controllers, alongside the platform's first widespread adoption of USB 3.0, typically implemented via two ports from companion controllers like ASMedia ASM1042 on motherboards. Expansion included eight PCIe 2.0 lanes (5 GT/s) from the PCH for peripherals, while the platform supported PCIe 2.0 x16 lanes directly from the Sandy Bridge CPU for discrete graphics cards, enabling high-bandwidth GPU performance without PCH bottlenecks. Additional features encompassed integrated Gigabit Ethernet (on select variants), six-channel HD Audio, and power management compliant with ACPI 4.0, prioritizing efficiency in desktop builds. However, Cougar Point faced a significant defect shortly after launch, identified on January 31, 2011, affecting the four 3 Gb/s ports (ports 2-5) in early B2-stepping units shipped from January 9 to mid-February 2011. The issue stemmed from a design flaw in the controller's internal connections, leading to gradual signal degradation over time, potentially reducing performance or disabling ports and risking in affected systems from 2011-2012. resolved it in the B3 stepping by revising the trace layout, resuming shipments from , 2011, and offering free RMAs or replacements for impacted motherboards, with no estimated impact on overall sales beyond a $300 million charge. This incident highlighted early challenges in high-volume production but did not affect the 6 Gb/s ports (0 and 1) or USB/PCIe functionality.

Panther Point

Panther Point is the codename for the Platform Controller Hub (PCH) used in Intel's 7 Series chipsets, released in April 2012 to accompany the Ivy Bridge family of 3rd-generation Core processors. These chipsets, including desktop variants such as Z77, H77, B75, Q75, and Q77, connect the CPU to peripherals via the Direct Media Interface (DMI) 2.0, supporting up to 2 GB/s bidirectional bandwidth. While compatible with 2nd-generation Sandy Bridge processors on LGA 1155 sockets, Panther Point was primarily designed for Ivy Bridge, enabling features like PCI Express 3.0 on the CPU side. A major advancement in Panther Point was the integration of native USB 3.0 support across all variants, featuring an xHCI controller that provides up to 4 ports at 5 Gb/s, alongside 10 USB 2.0 ports for a total of 14 ports. This built on the Cougar Point's capabilities by expanding storage options to 6 ports, with 4 operating at 6 Gb/s and 2 at 3 Gb/s, enhancing data transfer rates for high-performance drives. Additionally, it includes 8 lanes of PCIe 2.0, configurable for graphics or storage expansion, and supports configurations for improved data redundancy. Fabricated on a , Panther Point maintained a low (TDP) of approximately 6 W for desktop implementations, contributing to efficient system operation without significant increases in power consumption compared to prior generations. This design addressed earlier limitations in USB implementation by embedding the controller directly, eliminating the need for third-party add-ons and improving reliability for high-speed peripherals.

Lynx Point

Lynx Point represents the fourth-generation Platform Controller Hub (PCH) for desktop platforms, serving as the core I/O component in Intel's 8 Series and 9 Series chipsets. Introduced in May 2013 alongside the 8 Series chipsets such as Z87 and H87, it was designed to pair with 4th-generation processors (Haswell) using the socket. An updated variant powered the 9 Series chipsets, including Z97 and H97, launched in May 2014 to accommodate Haswell Refresh and 5th-generation Core processors (Broadwell), extending compatibility while maintaining backward support for Haswell. This evolution addressed the increasing bandwidth demands of Haswell architectures by enhancing I/O flexibility without altering the fundamental PCH topology. Key features of Lynx Point emphasize expanded connectivity, including up to 8 PCIe 2.0 lanes configurable in various widths (such as x4, two x2, or four x1 per port group) for peripherals and storage expansion, operating at 5.0 GT/s. It provides 6 6 Gb/s ports supporting AHCI and modes with hot-plug capabilities, enabling robust storage configurations. The 9 Series iteration introduced native support via two PCIe 2.0 lanes or a interface, facilitating early adoption of compact SSDs and marking a shift toward modular storage standards. Building on prior generations like Panther Point, Lynx Point retained integrated controllers (up to 6 ports) while prioritizing PCIe and enhancements to match Haswell's performance profile. These capabilities were delivered through a 22 nm process, balancing power efficiency with expanded I/O for mainstream and enthusiast desktops. Lynx Point chipsets, particularly Z87 and Z97, enabled on unlocked "" series processors, but early implementations exhibited instability during high-frequency operation due to challenges in the power delivery subsystem. Unsupported modes could lead to system crashes or throttling, often linked to adaptive voltage offsets and load-line calibration inaccuracies. These issues were mitigated through updates released throughout 2014 by motherboard vendors, incorporating revisions for improved voltage stability and reliability. Such patches ensured better compatibility with extreme configurations, though remained chipset-variant specific—enabled on Z87/Z97 but disabled on lower-tier models like H87.

Sunrise Point

Sunrise Point represents the fifth-generation desktop Platform Controller Hub (PCH) developed by , serving as the I/O companion to the Skylake and processor architectures. Released in August 2015 alongside the 100 Series chipsets, such as Z170 and H170, it marked a significant evolution in desktop platform connectivity by integrating enhanced storage and peripheral support tailored for mainstream consumer and enthusiast systems. Key features of Sunrise Point include native support for USB 3.1, with configurations allowing up to two USB 3.1 Gen 2 ports (10 Gb/s) on higher-end variants like Z170 and H170, alongside up to 10 (5 Gb/s) ports for broader peripheral expansion. It also introduced (RST) enhancements enabling NVMe RAID configurations, such as RAID 0, 1, 5, and 10, for PCIe-based SSDs, improving storage performance and redundancy without relying solely on CPU lanes. Building on the PCIe 2.0 limitations of the prior Point PCH, Sunrise Point added PCIe 3.0 lanes directly to the chipset, facilitating faster and expansion options at up to 8 GT/s per lane. Sunrise Point supports sixth-generation (Skylake) and seventh-generation () Intel i processors via the socket, enabling and integrated graphics capabilities while handling platform power management and I/O routing. Notably, it was the first PCH to provide integrated support for Intel Optane acceleration through Intel RST, allowing hybrid storage setups that pair Optane modules with HDDs or SSDs for improved system responsiveness, particularly in the 200 Series variants compatible with . This feature debuted with Optane's consumer launch in 2017, leveraging the PCH's storage controller for seamless caching without dedicated hardware modules.

Comet Lake PCH

The Comet Lake Platform Controller Hub (PCH), part of Intel's 400 Series chipsets, serves as the refreshed desktop I/O controller for the 10th-generation Core i processors codenamed -S. Released in April 2020 alongside the -S CPUs, it introduces the socket and supports high-core-count configurations up to 10 cores, enabling enhanced multitasking and productivity workloads on desktop systems. The 400 Series includes variants such as Z490 for enthusiast , B460 for mainstream builds, H470 for business applications, and H410 for entry-level setups, all built on a mature architecture that extends compatibility with prior-generation features while optimizing for the new CPU family. Key enhancements in the PCH focus on expanded connectivity without a full architectural overhaul from the preceding 300 Series. It provides up to 24 PCIe 3.0 lanes from the PCH, allowing flexible allocation for storage, networking, and expansion cards, in addition to the 16 PCIe 3.0 lanes from the CPU for and high-bandwidth peripherals. USB support includes up to six USB 3.2 Gen 2x1 ports operating at 10 Gb/s for faster data transfers, alongside up to 10 USB 3.2 Gen 1x1 ports at 5 Gb/s and 14 USB 2.0 ports, catering to diverse peripheral needs in desktop environments. Storage options feature up to eight 6.0 Gb/s ports with 0/1/5/10 configurations via , maintaining backward compatibility with NVMe SSDs as established in earlier PCH designs. A notable advancement is the enhanced integration of Wi-Fi 6 (802.11ax) through the Intel CNVi interface, which offloads radio processing to the PCH for improved efficiency and lower power consumption compared to discrete wireless solutions. This native support enables dual-band operation at up to 2.4 Gb/s on 5 GHz bands when paired with compatible CNVi modules like the Intel Wi-Fi 6 AX201, facilitating seamless high-speed wireless connectivity in modern desktops. Overall, the Comet Lake PCH prioritizes incremental expansions in lane count and I/O versatility to support the increased demands of 10th-generation processors, bridging to future transitions like PCIe 4.0 in subsequent series.

Rocket Lake PCH

The Rocket Lake PCH, integrated into Intel's 500 Series Chipset Family, serves as the platform controller hub for 11th-generation Core processors, codenamed -S, and was released in March 2021. This chipset lineup includes variants such as Z590, H570, B560, and H510, designed primarily for desktop systems to enhance connectivity and I/O capabilities while maintaining compatibility with existing sockets. Backward compatibility with 400 Series motherboards is achieved through updates, allowing users to upgrade to Rocket Lake CPUs without replacing the . A key advancement in the PCH is its introduction of PCIe 4.0 compatibility, specifically providing up to x4 lanes for high-speed storage devices like NVMe SSDs, enabling doubled bandwidth over PCIe 3.0 for faster data transfers in demanding applications. The PCH itself delivers up to 24 PCIe 3.0 lanes for general expansion, with PCIe 4.0 support limited to select ports (such as 0, 3, 4, 7, and 9) when paired with 11th-generation processors, while the DMI 3.0 interface connects to the CPU at x8 width for improved inter-component communication. USB connectivity expands to support up to 12 USB 3.2 ports, including Gen 2x2 options at 20 Gbps, building on the USB expansions seen in the prior platform for better peripheral integration. Fabricated on a 14 nm process node, the Rocket Lake PCH represents Intel's final iteration of this technology for desktop platforms before transitioning to 7 nm in subsequent generations. The platform's integrated memory controller (IMC) improvements enable native support for DDR4-3200 memory speeds, enhancing overall system performance for CPUs without requiring . These features collectively position the 500 Series as an evolutionary step, focusing on storage acceleration and I/O efficiency for gaming and productivity workloads.

Alder Lake PCH

The Alder Lake Platform Controller Hub (PCH), part of Intel's 600 Series chipset family, was released in November 2021 alongside the 12th Generation processors. These chipsets, including variants such as Z690, H670, B660, and H610, are designed for desktop platforms and support the hybrid architecture of CPUs, which integrate Performance-cores (P-cores) for high-performance tasks and Efficient-cores (E-cores) for efficiency. The PCH serves as the central I/O hub, managing connectivity while the CPU handles primary processing and functions. A key advancement in the PCH is its enhanced (DMI) 4.0 x8 link operating at 16 GT/s, providing up to approximately 15.75 GB/s of bidirectional throughput between the CPU and PCH. This upgrade supports higher data transfer rates for peripherals. The PCH offers up to 28 total PCIe lanes, including up to 12 PCIe 4.0 lanes and up to 16 additional PCIe 3.0 lanes, enabling robust expansion for storage, networking, and other devices. While the PCH itself does not directly support PCIe 5.0, the overall platform integrates CPU-provided PCIe 5.0 x16 lanes dedicated to graphics cards, marking a significant step in I/O scalability. Memory support in the platform is facilitated through the CPU's integrated , which handles DDR5 (up to 4800 MT/s) or DDR4 (up to 3200 MT/s) configurations, with the PCH overseeing related I/O operations such as USB and interfaces. This dual-memory compatibility allows flexibility for users transitioning to next-generation standards, though DDR5 adoption emphasizes higher bandwidth potential for Lake's hybrid core design. The 600 Series PCH also includes up to 8 6 Gb/s ports and extensive USB support (up to 14 USB 2.0, 10 USB 3.2 Gen 1x1, and 10 USB 3.2 Gen 2x1 ports across SKUs), ensuring comprehensive peripheral connectivity.

Raptor Lake PCH

The Raptor Lake Platform Controller Hub (PCH) serves as the refreshed iteration of Intel's 700 Series chipsets, designed specifically for the 13th-generation processors in desktop systems. Released in October 2022, these chipsets include variants such as Z790 for enthusiast capabilities and B760 for mainstream builds, enabling enhanced connectivity and performance optimizations over prior generations. These chipsets primarily pair with and subsequent compatible processors, with support for 12th and 14th Gen via updates. Key enhancements in the PCH focus on improved I/O integration, supporting up to 20 Gbps USB 3.2 Gen 2x2 ports alongside expanded and 4 interfaces capable of 40 Gb/s bidirectional data transfer for high-speed peripherals. It supports up to PCIe 4.0 x4 lanes from the PCH for NVMe storage, with PCIe 5.0 x4 available from the CPU, facilitating faster SSD performance, while maintaining compatibility with DDR5 up to 192 GB total capacity across four slots after updates. These chipsets build on the hybrid core architecture introduced in by increasing performance core counts for better multitasking efficiency.

Arrow Lake PCH

The Arrow Lake Platform Controller Hub (PCH) serves as the I/O controller for Intel's 15th-generation Core Ultra Series 2 desktop processors, released on , 2024, as part of the 800 series chipsets. These chipsets, including the enthusiast-oriented Z890, mainstream B860, and entry-level H810 variants, enable enhanced connectivity and efficiency for desktop platforms focused on AI workloads and . The PCH integrates with the Arrow Lake CPUs to manage peripherals, storage, and networking, building on prior generations like by continuing support for DDR5 up to 6400 MT/s. A key advancement in the Arrow Lake PCH is its expanded PCIe 5.0 support, providing up to x4 PCIe 5.0 lanes from the on the Z890 model, alongside up to 24 PCIe 4.0 lanes for flexible configurations such as graphics cards, NVMe SSDs, and add-in cards. This configuration allows for doubled bandwidth compared to PCIe 4.0 equivalents, facilitating faster data transfer rates critical for AI training and tasks. The B860 offers PCIe 5.0 x4 but with fewer total lanes, while the H810 limits to PCIe 4.0 without PCIe 5.0 from the PCH. The 800 series PCH also introduces standardized Gen 3x2 support at 40 Gb/s speeds across variants, enabling Thunderbolt-compatible connectivity for external displays, storage, and peripherals with reduced latency. Up to 10 USB 3.2 Gen 2x2 ports (20 Gb/s) and 14 USB 2.0 ports are available on the Z890, with scaled-down options on lower-tier chipsets, enhancing platform efficiency for multi-device ecosystems. For AI-specific enhancements, the PCH facilitates integration with the CPU's built-in Neural Processing Unit (NPU), delivering up to 48 TOPS for inference while maintaining low overall system power draw.
Chipset VariantPCIe 5.0 Lanes (Chipset)USB 3.2 Ports (Max)USB4 PortsKey Use Case
Z890x410 (Gen 2x2)2Enthusiast and AI PCs
B860x46 (Gen 2x2)1Mainstream productivity
H810None4 (Gen 2x1)0Entry-level systems

Mobile PCH Variants

Langwell

Langwell is the codename for Intel's first Platform Controller Hub specifically tailored for ultra-low-power mobile platforms, introduced as part of the Moorestown architecture in 2010 to target mobile devices (MIDs) and smartphones. Announced in 2009 alongside the Lincroft system-on-chip, it represented Intel's push into handheld computing with enhanced power efficiency over previous Atom designs like Pine Trail. The PCH interfaced with a dedicated IC codenamed Briertown to optimize energy delivery, enabling seamless integration of PC-like I/O with mobile peripherals. Fabricated on a , Langwell was engineered for and MID form factors with a platform TDP around 2 W, prioritizing idle power reduction through distributed power gating and advanced sleep states. It supported the Atom Z600 series processors embedded in the 45 nm Lincroft SoC, delivering core computing alongside integrated from the PowerVR SGX 535 GPU. This combination allowed for battery life estimates of up to 5 hours of web browsing or 4-5 hours of talk time in reference designs. Key features focused on mobile-centric I/O, including a NAND flash controller for eMMC storage, an SDIO 2.0 controller for wireless connectivity, a low-power with multi-stream support, and a MIPI-CSI interface for high-resolution cameras up to video. The USB 2.0 host controller enabled connectivity for peripherals, while CE-ATA support provided embedded storage options at up to 1.5 Gb/s transfer rates. Integrated graphics were handled via output for video, with provisions for (LVDS) in display configurations suitable for compact screens. Langwell paralleled the desktop Ibex Peak PCH in using the (DMI) for CPU connectivity but omitted full PCIe lanes in favor of power savings.

Tiger Point

The Intel Tiger Point, codenamed for the NM10 Express Chipset, served as a key platform controller hub in 's low-power mobile platforms, particularly the Pine Trail introduced in late 2009 and extended to the Cedar Trail platform in 2011. This chipset facilitated the transition to more integrated, power-efficient designs for netbooks and entry-level desktops, pairing with Atom processors to enable compact systems with reduced and improved battery life. Manufactured on a , the NM10's compact 17 mm × 17 mm package represented an 85% reduction in size compared to the prior Intel 945GC chipset, contributing to thinner profiles suitable for portable devices like netbooks and early tablets. Key I/O capabilities of Tiger Point emphasized efficiency and connectivity for mobile use, including up to two 3 Gb/s ports for storage access, supporting low-power modes inherited from earlier designs like the Langwell PCH. It provided up to eight USB (Hi-Speed) ports for peripheral expansion, an integrated 10/100 Ethernet MAC for networking, and lanes configurable for graphics or add-in cards, alongside LPC interface for legacy device support. The chipset also integrated an SMBus controller for system management and power delivery features aligned with standards, operating at a typical power draw of around to extend battery runtime in ultraportable systems. While not natively supporting readers, its and general-purpose I/O enabled integration of such features via companion controllers on motherboards. Tiger Point primarily supported Intel processors from the N and D series, including single- and dual-core models like the Atom N450 (1.66 GHz) and D510 (1.66 GHz) in Pine Trail, as well as later Cedar Trail variants such as the dual-core Atom D2700 (2.0 GHz, 10 W TDP) for enhanced media playback and via integrated PowerVR capabilities. This compatibility allowed for systems with up to 4 GB DDR3 memory and onboard processing, targeting sub-$300 s with full HD video decode support. By optimizing for low and form factor, Tiger Point helped sustain the market through 2012, bridging to more advanced mobile platforms before being superseded by higher-performance chipsets.

Whitney Point

The Whitney Point is the codename for the Intel 82SM35 Platform Controller Hub (PCH), integrated into the SM35 Express Chipset and designed specifically for the Oak Trail platform in low-power mobile devices such as tablets. Introduced in early 2011 as part of Intel's Atom-based ecosystem, it pairs with the Lincroft SoC (featuring Atom Z600 series processors) to enable support for full-featured operating systems like on battery-constrained hardware. This PCH represents an early evolution in Intel's mobile chipset strategy, shifting from system-on-package designs to a discrete PCH for enhanced I/O flexibility while prioritizing power efficiency. A key differentiator of Whitney Point is its ultra-low (TDP) of 0.75 W, achieved through advanced techniques including , dynamic voltage scaling, and USB selective suspend modes. It connects to the Lincroft SoC via a (cDMI) with dual uni-directional lanes at 400 MT/s, alongside a Digital Video Out (cDVO) interface at 800 MT/s for display handling. The architecture employs AMBA/OCP-based internal buses to consolidate system control logic, minimizing external components and overall power draw in mobile form factors. Additionally, it incorporates a hardware cryptographic engine for secure and content protection, along with 256 KB of on-chip SRAM dedicated to boot code execution and low-power standby states. Power delivery is managed via an integrated SPI interface to an external power management IC (PMIC), enabling fine-grained control over voltage rails and sleep transitions critical for extending battery life in tablets. Whitney Point's I/O subsystem is tailored for compact, connectivity-rich devices, supporting essential peripherals without excessive pin count. It provides robust storage and expansion options optimized for the era's tablet needs, including serial and parallel interfaces for sensors, storage, and . The following table summarizes its primary connectivity features:
Interface TypeDetails
USB4 x USB 2.0 high-speed ports (480 Mbps), with power-saving modes
1 x SATA 2.6 port (3.0 Gbps) for storage devices
SD/SDIO/MMC2 x SD/SDIO/MMC controller ports; 1 x dedicated SDIO port
Display 1.3a via cDVO (up to 1080p@30 Hz); supports DVI
Audio with multi-streaming capabilities
Other Serial3 x buses; 2 x SPI interfaces; LPC bus for legacy peripherals
These capabilities allowed Oak Trail devices to handle multimedia playback, external storage, and basic peripherals efficiently, though limited to USB 2.0 and single-channel DDR2-800 memory support (up to 2 GB) via the Lincroft SoC. Unlike later PCH variants, Whitney Point lacks PCIe lanes, focusing instead on embedded-oriented interfaces to reduce complexity and cost in sub-10 W platforms. In the broader context of Intel's mobile PCH lineup, Whitney Point marked a transitional design bridging Moorestown's integrated approach with more modular architectures in subsequent generations like Tiger Point. It powered early x86 tablets such as the ViewPad 7 and Sony Tablet S prototypes, demonstrating viable performance for web browsing and light productivity at around 3.75 W total platform TDP when combined with Lincroft. However, its adoption was limited by the rapid rise of ARM-based competitors, leading Intel to refine future variants for even lower power envelopes.

Lynx Point-M

Lynx Point-M is the codename for Intel's mobile Platform Controller Hub (PCH) in the 8 Series family, released in 2013 to support the Haswell platform in high-performance laptops and mobile workstations. It exemplifies variants like the , designed for premium ultrabooks and notebooks. This PCH pairs with mobile Haswell processors from Intel's 4th-generation Core i series, enabling efficient power management and integrated graphics acceleration. Key enhancements focus on storage and wireless capabilities, including support for M.2 slots for solid-state drives (SSDs) to enable faster boot times and application loading. Wireless Display (WiDi) integration allows seamless streaming of video content to compatible screens without cables, leveraging Haswell's improved media processing. Connectivity includes up to 14 USB ports (4 USB 3.0 at 5 Gbps + 10 USB 2.0). A standout advancement in Lynx Point-M is native support for SATA RAID levels 0, 1, and 5 through , allowing configuration of striped arrays for performance or mirrored/parity setups for data protection in . This extends capabilities to mobile systems. Lynx Point-M also supports Thunderbolt 2.0 (up to 20 Gbps) for high-bandwidth external peripherals via a single cable.

Sunrise Point-M

The Sunrise Point-M platform controller hub (PCH) was released in 2015 as part of Intel's 100 Series mobile chipsets, exemplified by the CM236 variant designed for high-end mobile workstations and performance laptops. It serves as the I/O companion to 6th-generation i processors (codenamed Skylake), providing essential connectivity and power management for thin-and-light form factors. Although primarily optimized for Skylake, it maintains compatibility with select 5th-generation Core i configurations in hybrid designs, enabling smooth transitions in mobile platforms. Key features of Sunrise Point-M include support for (up to 5 Gbps) with up to 14 ports total, including Type-C interfaces for reversible connectivity. The PCH also integrates Ethernet support up to 1 Gb/s via multiple MAC controllers, facilitating reliable wired networking in enterprise laptops. Memory handling is enhanced through PCH I/O pathways that accommodate DDR4 and LPDDR4 configurations, with up to 2 DIMMs per channel and ECC support in variants like CM236, allowing for scalable performance in memory-intensive applications. Additionally, it offers DMI 3.0 (8 GT/s), up to 12 PCIe 2.0 lanes, 8 6 Gb/s ports, and 3 display outputs for setups. Sunrise Point-M builds on prior mobile PCH designs by incorporating advanced GPIO capabilities, which enable integration of device sensors for versatile form factors such as 2-in-1 convertibles, supporting features like orientation detection through customizable pin configurations. This optimization enhances in hybrid devices by allowing seamless mode switching between and tablet orientations. The chipset's low TDP of 3.67 contributes to extended battery life, making it ideal for mobile productivity. It also retains with storage slots introduced in earlier generations for SSD expansion.

Cannon Point

Cannon Point served as the transitional (PCH) for Intel's Cannon Lake processors, debuting in limited mobile configurations within the 300 Series chipsets in 2018. This PCH was designed specifically for ultra-low-power 8th-generation Core processors, such as the Core i3-8121U, a 10 nm dual-core 15 W part aimed at thin-and-light laptops. As Intel's first foray into 10 nm fabrication for both CPU and PCH components, Cannon Point represented an early attempt to shrink the platform for better power efficiency in mobile devices, though its scope was confined to low-volume production due to manufacturing challenges. The Cannon Point PCH featured PCIe 3.0 support with 8 lanes for peripheral connectivity, USB 3.1 Gen 2 ports inheriting capabilities from prior designs like Union Point, and the introduction of the integrated interface to streamline integration via compatible modules. These elements prioritized compact I/O for battery-constrained systems, enabling features like faster data transfer and simplified wireless hardware without discrete controllers. However, the debut encountered yield issues, resulting in throttled clock speeds and suboptimal performance compared to established 14 nm alternatives, which limited Cannon Point's market penetration to a handful of devices before shifted focus to more reliable architectures. This brief lifecycle underscored Cannon Point's role as a proof-of-concept for on-chip integration trends, paving the way for subsequent PCH evolutions while highlighting the risks of aggressive process transitions in mobile platforms. Adoption remained low, with the platform phased out by early 2020 in favor of refined 14 nm mobile solutions.

Union Point

Union Point is the codename for Intel's mobile Platform Controller Hub (PCH) in the 200 Series family, released in 2016 to support the Kaby Lake platform. It exemplifies variants like the HM175 chipset for high-end mobile workstations and performance laptops. It serves as the I/O companion to 7th-generation Intel Core i processors (codenamed Kaby Lake). Key features include continued support with improved Type-C integration, Ethernet up to 1 Gb/s, DDR4/LPDDR3 memory with ECC in select variants, DMI 3.0, up to 12 PCIe 2.0 lanes, 8 6 Gb/s ports, and multiple display outputs. It introduces better power efficiency for convertible devices with enhanced GPIO for sensors. TDP around 4 W for mobile variants.

Later Mobile PCH Variants

Following Cannon Point, Intel's mobile PCH evolved with the 400 Series (, 2020), using a 14 nm refresh of Cannon Point, supporting 10th-generation -H processors with PCIe 3.0, USB 3.2 Gen 1, and improved 3 integration for gaming laptops. The 500 Series (, 2020) shifted toward integration, with low-power U-series featuring on-die I/O, while H-series used discrete PCH with PCIe 4.0 support from CPU, / 4 (40 Gbps), and 2.0 for 6. The 600 Series (Alder Lake mobile, 2021) introduced hybrid architecture support, PCIe 5.0 (from CPU), up to 28 PCIe 4.0 lanes total, DDR5/LPDDR5, and via . The 700 Series ( mobile, 2022) enhanced with more PCIe 5.0 lanes, , and better for 13th-gen processors. By 2023-2025, Core Ultra series (, Arrow Lake mobile equivalents) integrated PCH on-package in the compute tile for ultra-low power, supporting PCIe 5.0, v2 (80 Gbps), and AI accelerators, reducing discrete components in thin laptops. As of November 2025, discrete PCH persists in high-end H-series for expandability.

Server and Workstation PCH Variants

Topcliff

The Topcliff Platform Controller Hub (PCH), codenamed EG20T, represents an early implementation of Intel's PCH architecture tailored for embedded and low-end server systems. Released in 2009 as part of the Queens Bay platform, it serves as the I/O controller for low-power, reliable computing environments such as industrial and compact servers. Designed for integration with Intel's Atom E6xx series processors (Tunnel Creek), including models like the E620T and E640T, Topcliff supports Atom-based server configurations equivalent to the N450 series but optimized for embedded reliability and extended temperature ranges. These processors operate at clock speeds up to 1.6 GHz with low (TDP) of 2-3 W, enabling fanless operation in space-constrained server setups. The PCH connects to the CPU via a interface, facilitating efficient data transfer for server workloads focused on storage and networking rather than . Key features of Topcliff emphasize robust I/O for server connectivity, including two ports supporting speeds up to 3 Gb/s for reliable in embedded or direct-attached configurations. It integrates a single [Gigabit Ethernet](/page/Gigabit Ethernet) controller (10/100/1000 Mbps) to enable networked server operations, with support for additional Ethernet via PCIe expansion for dual-port setups in multi-interface environments. Overall, Topcliff prioritizes stability and low power over raw speed, making it suitable for 24/7 embedded server applications on a node.

Cave Creek

The Intel Cave Creek platform controller hub refers to the server-oriented variants of the C600 series chipset, launched in the first quarter of as part of Intel's Crystal Forest platform. This chipset family was developed to deliver robust I/O connectivity for enterprise workloads, emphasizing reliability and scalability in two-socket server environments. It interfaces with the CPU via a (DMI) at 5 GT/s, handling peripheral functions to offload the processor. Cave Creek supports processors from the Sandy Bridge-EP family, specifically the E5-2600 series, which utilize the socket. These systems leverage (QPI) links operating at up to 8 GT/s to enable dual-socket configurations, facilitating cache-coherent communication between processors for demanding computational tasks. The is fabricated using a technology, balancing power efficiency with the integration of multiple controllers. A hallmark of Cave Creek is its expanded storage subsystem, optimized for data-intensive applications. Server variants such as the C606 provide up to eight ports configurable as or SAS through dual integrated Storage Controller Units (SCUs), with two ports supporting at 6 Gb/s and the remainder at 3 Gb/s for SAS or operation. This setup enables high-availability storage arrays, including levels 0, 1, 5, and 10 via Enterprise (RSTe), enhancing data redundancy and performance without dedicated add-in cards. Additionally, the chipset delivers eight lanes of 2.0 connectivity, configurable in various widths (x1, x2, x4, or x8) for peripherals and networking, complementing the CPU's native PCIe 3.0 support.

Patsburg

The Patsburg , part of 's C610 series, was released between 2012 and 2013 as a platform controller hub (PCH) tailored for server and environments supporting multi-socket configurations. It introduced advancements in scalability for enterprise systems, particularly enabling dual PCH setups to manage I/O demands in up to four-socket platforms through features like PM_SYNC2 . This design evolved from earlier server PCHs, such as Cave Creek, by incorporating enhanced support for storage reliability in larger deployments. Key features of Patsburg include support for 10GbE networking via PCIe interfaces, facilitating high-bandwidth connectivity in data center applications. It provides up to 14 SATA/SAS ports, combining eight 3 Gb/s SAS ports, two 6 Gb/s SATA ports, and four 3 Gb/s SATA ports, allowing flexible storage configurations for RAID arrays and direct-attached storage. The chipset connects to the CPU via a DMI 2.0 interface at 20 Gb/s, ensuring efficient data transfer in multi-processor setups. Patsburg supports Intel Xeon processors based on the Ivy Bridge-EP and Haswell-EP architectures, specifically the E5-2600 v2 and v3 families, enabling robust performance for compute-intensive workloads in two- to four-socket servers. A notable innovation is the transition from the (LPC) interface to (SPI) for firmware management, which supports up to two 16 MB SPI flash devices and allows for larger sizes to accommodate complex server boot processes. This shift improved boot efficiency and scalability for enterprise firmware updates.

Wellsburg

The Wellsburg , marketed as part of Intel's C610 series and specifically the C612 variant, was launched in September 2014 to serve server and platforms requiring robust I/O capabilities. It succeeded the Patsburg by integrating enhanced connectivity in a single-die design optimized for enterprise scalability. Designed for processors based on the Haswell-EP and Broadwell-EP microarchitectures, Wellsburg primarily supports the E5-2600 v3 and v4 families, enabling configurations with up to 18 cores per socket and DDR4 memory at speeds up to 2400 MT/s. The connects to the CPU via a 2.0 (DMI 2.0) at 5 GT/s, facilitating efficient data transfer between the processor and peripherals. A core feature is its integration with the QuickPath Interconnect (QPI), operating at up to 9.6 GT/s for low-latency, coherent communication in multi-socket systems. This allows for high-bandwidth scaling, with each CPU providing 40 lanes of PCIe 3.0 directly, while the PCH contributes 8 additional PCIe 2.0 lanes configurable as x1, x2, x4, or x8. Wellsburg emphasizes advanced Reliability, Availability, and Serviceability (RAS) through features like Intel Virtualization Technology for Directed I/O (VT-d) for secure I/O virtualization and Node Manager for power and thermal monitoring. These capabilities support mission-critical operations by enabling error detection, recovery, and remote management. It supports up to 2-socket configurations for E5-2600 v3 and v4 processors.

Lewisburg

The Lewisburg , part of Intel's C620 series, was released in July 2017 as the platform controller hub for server and systems based on the first-generation Scalable processors (Skylake-SP). Manufactured on a node, it emphasizes efficiency through features like states (including D0/D3 and Deep Sx), , and Energy Efficient Ethernet (EEE) to optimize in multi-socket environments. A key adaptation in Lewisburg is its support for the mesh architecture and (UPI) in Skylake-SP platforms, providing up to three UPI links per CPU for scalable multi-socket connectivity while maintaining backward compatibility with prior QPI-based designs like Wellsburg. The platform delivers up to 48 PCIe 3.0 lanes from the CPU; the PCH provides up to 20 PCIe 3.0 lanes, configurable as up to 20 root ports, enabling high-bandwidth expansion for storage, networking, and accelerators without introducing PCIe 4.0. Integrated Ethernet options include 10 GbE (up to four ports via Intel X722) and 25 GbE support with features like RDMA, Data Center Bridging (DCB), and virtualization offloads for cloud and virtualization workloads. Lewisburg pairs with Skylake-SP processors via a DMI 3.0 x4 interface and supports six-channel DDR4 up to 2666 MT/s, facilitating up to 1.5 TB per socket with Registered DIMMs (RDIMMs) or Load-Reduced DIMMs (LRDIMMs) for memory-intensive applications. Additional efficiency measures include Latency Tolerance Reporting (LTR), Dynamic Link Throttling, and Single Root (SR-IOV) with up to 128 virtual functions, enhancing resource utilization in virtualized environments. The chipset also incorporates the for and security features like (TPM) support to bolster reliability. Subsequent generations, such as C621/C622 for Ice Lake-SP and C741 for (as of 2023), continue to evolve the server PCH architecture with enhanced PCIe 4.0/5.0 support and improved security.

Basin Falls

The C422 chipset is a platform controller hub designed for workstation systems supporting the second-generation Scalable processors based on the microarchitecture. Released in 2019 as part of the Cascade Lake-W platform, it builds on prior workstation PCH designs by incorporating enhanced features tailored for professional workloads. A key advancement in the C422 is the inclusion of hardware-based mitigations for vulnerabilities such as Spectre and Meltdown, which were first addressed in production with processors to improve system resilience without relying solely on software patches. This PCH supports up to 64 PCIe 3.0 lanes directly from the CPU in single-socket configurations, enabling high-bandwidth connectivity for GPUs, storage, and networking in demanding workstation environments. Additionally, it provides native support for Intel Optane persistent memory, allowing systems to combine DRAM with for larger effective memory capacities while maintaining data persistence across power cycles. The C422 specifically enables Software Guard Extensions (SGX) enclaves, an Intel technology that creates hardware-isolated regions of memory for running sensitive code and data in trusted execution environments, enhancing security for applications like secure data analytics and in deployments. These features position the C422 as an incremental evolution from server-oriented PCHs like Lewisburg, retaining the DMI 3.0 interface while adding Cascade Lake-specific security hardware without major changes to the interconnect architecture.

References

  1. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/5-chipset-3400-chipset-datasheet.pdf
  2. https://cdrdv2-public.intel.com/743835/743835-004.pdf
  3. https://www.intel.com/content/www/us/en/content-details/332690/intel-100-series-chipset-family-platform-controller-hub-pch-datasheet-volume-1.html
  4. https://edc.intel.com/content/www/th/th/design/products/platforms/details/arrow-lake-s/800-series-chipset-family-platform-controller-hub-pch-datasheet-volume/integrated-pull-ups-and-pull-downs_3/
  5. https://cdrdv2-public.intel.com/786255/786255_330119_ia-introduction-basics-paper.pdf
  6. https://www.tomshardware.com/picturestory/784-intel-chipset-history.html
  7. https://www.tomshardware.com/picturestory/784-intel-chipset-history-2.html
  8. https://cdrdv2-public.intel.com/635218/635218-008.pdf
  9. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c620-series-chipset-datasheet.pdf
  10. https://www.intel.com/content/www/us/en/support/articles/000094185/processors.html
  11. https://www.techpowerup.com/review/intel-meteor-lake-technical-deep-dive/2.html
  12. https://cdrdv2-public.intel.com/842318/intel-800-series-chipset-brief-public.pdf
  13. https://newsroom.intel.com/client-computing/intel-unveils-panther-lake-architecture-first-ai-pc-platform-built-on-18a
  14. https://www.techpowerup.com/82318/intel-5-series-chipset-lineup-detailed
  15. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82577-gbe-phy-datasheet.pdf
  16. https://www.gigabyte.com/Motherboard/GA-H55M-USB3-rev-20/sp
  17. https://support.microsoft.com/en-us/topic/intel-5-and-3400-series-chipset-family-usb-ports-stall-with-bulk-and-control-traffic-d75f9f86-9a2e-147a-62f1-4cea9d93a6d9
  18. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf
  19. https://www.intc.com/news-events/press-releases/detail/688/intel-identifies-chipset-design-error-implementing-solution
  20. https://www.techspot.com/news/42225-more-details-emerge-about-intels-cougar-point-chipset-flaw.html
  21. https://www.techspot.com/guides/519-intel-z77-panther-point-chipset/
  22. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7-series-chipset-pch-datasheet.pdf
  23. https://www.pcstats.com/articles/2714/3.html
  24. https://www.techspot.com/review/521-intel-z77-motherboard-roundup/
  25. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8-series-chipset-pch-datasheet.pdf
  26. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/9-series-chipset-pch-datasheet.pdf
  27. https://bit-tech.net/reviews/tech/motherboards/the-intel-9-series-chipsets-examined/2/
  28. https://www.asus.com/supportonly/z87k/helpdesk_bios/
  29. https://arstechnica.com/gadgets/2015/08/intels-100-series-chipsets-ddr4-pcie-3-0-ssds-and-other-skylake-supplements/
  30. https://pcper.com/2015/08/check-out-the-architecture-at-skylake-and-sunrise-point/
  31. https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf
  32. https://theretroweb.com/chip/documentation/hm170-qm170-chipset-brief-64b14982198cd696537604.pdf
  33. https://www.intel.com/content/www/us/en/products/sku/90590/intel-h110-chipset/compatible.html
  34. https://www.intel.com/content/www/us/en/support/articles/000026040/memory-and-storage/intel-optane-memory.html
  35. https://wccftech.com/intel-10th-gen-comet-lake-cpu-z490-desktop-platform-official-launch/
  36. https://www.intel.com/content/www/us/en/products/sku/201834/intel-z490-chipset/specifications.html
  37. https://www.tomshardware.com/news/intel-z490-comet_lake_s-motherboards
  38. https://bit-tech.net/news/tech/motherboards/intel-releases-details-on-400-series-chipset/1/
  39. https://www.tomshardware.com/news/intel-rocket-lake-release-date-specifications-performance-all-we-know
  40. https://www.techpowerup.com/270435/intel-11th-gen-core-rocket-lake-s-es-shown-running-pcie-4-0-nvme-ssd
  41. https://www.intc.com/news-events/press-releases/detail/1506/intel-unveils-12th-gen-intel-core-launches-worlds-best
  42. https://www.intel.com/content/www/us/en/products/platforms/details/alder-lake-s.html
  43. https://www.tomshardware.com/news/intel-alder-lake-h670-b660-h610-chipset-specifications-exposed
  44. https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/intel-600-series-chipset-family-platform-controller-hub-pch-datasheet-volume/004/pch-skus/
  45. https://www.tomshardware.com/news/intel-600-series-chipsets-no-pcie-gen-5
  46. https://www.tomshardware.com/news/intel-13th-gen-raptor-lake-release-date-specifications-pricing-benchmarks-all-we-know-specs
  47. https://www.wepc.com/tips/intel-700-series-motherboards-release-date-price-what-we-know/
  48. https://www.asus.com/microsite/motherboard/Intel-Raptor-Lake-Z790-H770-B760/v1/download/ASUS-700-Series-Specs_20231004.pdf
  49. https://www.sportskeeda.com/gaming-tech/news-intel-13th-gen-raptor-lake-rumored-release-date-specs
  50. https://www.corsair.com/us/en/explorer/diy-builder/memory/best-memory-for-intel-14th-gen-raptor-lake-refresh-cpus/
  51. https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-p/700-series-chipset-family-on-package-platform-controller-hub-pch-specif/
  52. https://www.pcgamesn.com/intel/arrow-lake-guide
  53. https://www.tomshardware.com/pc-components/motherboards/intel-arrow-lake-chipsets-reportedly-detailed-w890-chipset-touted-for-next-gen-intel-xeon-hedt-cpus
  54. https://www.pcgamer.com/intels-arrow-lake-specs-break-cover-say-hello-to-ddr5-6400-wave-goodbye-to-ddr4-and-possibly-hyper-threading/
  55. https://www.guru3d.com/story/very-detailed-specifications-of-intel-800series-chipsets-leaked/
  56. https://www.techpowerup.com/324153/intels-upcoming-800-series-chipsets-leak-in-detail
  57. https://www.intel.com/pressroom/archive/reference/Moorestown_backgrounder.pdf
  58. https://en.wikichip.org/wiki/intel/chipsets/langwell
  59. https://www.intel.com/pressroom/enhanced/atom_n450/pdfs/Next_Gen_Atom_Processor_factsheet.pdf
  60. https://www.techpowerup.com/157617/intel-launches-the-cedar-trail-atom-platform
  61. https://jetwaycomputer.com/NC9E.html
  62. https://www.intel.com/content/www/us/en/products/platforms/details/cedar-trail.html
  63. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/sm35-express-chipset-datasheet.pdf
  64. https://www.zdnet.com/article/intel-first-oak-trail-tablets-coming-next-month/
  65. https://en.wikichip.org/wiki/intel/platforms/oak_trail
  66. https://kupaworld.wordpress.com/2011/08/11/intel-atom-z670/
  67. https://www.intel.com/content/www/us/en/products/sku/75531/intel-hm86-chipset/specifications.html
  68. https://www.intel.com/content/www/us/en/products/sku/75531/intel-hm86-chipset/compatible.html
  69. https://www.intel.com/content/www/us/en/products/docs/chipsets/8-series-chipset-pch-datasheet-volume-1.html
  70. https://www.intel.com/content/www/us/en/products/sku/90593/mobile-intel-cm236-chipset/specifications.html
  71. https://www.intel.com/content/www/us/en/products/platforms/details/skylake-h.html
  72. https://www.gigabyte.com/us/Press/News/1370
  73. https://www.intel.com/content/www/us/en/products/platforms/details/skylake-u-y.html
  74. https://www.intel.com/content/www/us/en/products/sku/136863/intel-core-i38121u-processor-4m-cache-up-to-3-20-ghz/specifications.html
  75. https://chipsandcheese.com/p/cannon-lake-intels-forgotten-generation
  76. https://www.intel.com/content/www/us/en/products/sku/135101/mobile-intel-hm370-chipset/specifications.html
  77. https://www.intel.com/content/www/us/en/support/articles/000026155/wireless.html
  78. https://endoflife.date/intel-processors
  79. https://www.intel.com/content/www/us/en/products/sku/100599/intel-hm175-chipset/specifications.html
  80. https://www.intel.com/content/www/us/en/products/ark/products-series/90787/7th-generation-intel-core-i-processors.html
  81. https://www.intel.com/content/www/us/en/products/docs/chipsets/400-series-chipset-pch-datasheet-volume-1.html
  82. https://www.intel.com/content/www/us/en/products/platforms/details/tiger-lake-h.html
  83. https://www.intel.com/content/www/us/en/products/docs/chipsets/600-series-chipset-pch-datasheet.html
  84. https://www.intel.com/content/www/us/en/products/docs/chipsets/700-series-chipset-brief.html
  85. https://www.intel.com/content/www/us/en/products/docs/processors/core-ultra/core-ultra-series-1-datasheet-volume-1.html
  86. https://hardwaresecrets.com/intel-chipset-codenames-cross-reference-table/
  87. https://www.cnblogs.com/baiyw/p/3413399.html
  88. https://www.dfi.com/pressroom/content/63
  89. https://edge.seco.com/usa/felis.html
  90. https://www.mouser.com/pdfdocs/Intel_Atom_Processor_E6xx_product_brief.pdf
  91. https://www.mouser.com/ProductDetail/Intel/CS82TPCF-S-LJ42?qs=L4m7d03Wznl4zI132ZmdwQ%3D%3D
  92. https://theretroweb.com/motherboard/manual/50-1z105-1020-cm720-referencemanual-final-en-64405ba244a15652029648.pdf
  93. https://www.rtsoft.ru/upload/pdfcat/COMe-mTT10_Manuals.pdf
  94. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c600-series-chipset-datasheet.pdf
  95. https://www.intel.com/content/www/us/en/products/sku/63984/intel-c602-chipset/specifications.html
  96. https://www.intel.com/content/www/us/en/products/sku/63984/intel-c602-chipset/compatible.html
  97. https://www.intel.com/content/www/us/en/products/sku/63986/intel-c606-chipset/specifications.html
  98. https://datasheet.octopart.com/DH82029PCHSLKM8-Intel-datasheet-180112615.pdf
  99. https://www.intel.com/content/www/us/en/products/sku/81759/intel-c612-chipset/specifications.html
  100. https://www.intel.com/content/dam/www/public/us/en/documents/platform-briefs/xeon-e5-2600-v3-c612-chipset-brief.pdf
  101. https://www.tweaktown.com/reviews/6813/supermicro-x10drg-q-intel-c612-workstation-motherboard-review/index.html
  102. https://en.wikichip.org/wiki/intel/cores/broadwell_ex
  103. https://pcper.com/2017/07/intel-xeon-scalable-processor-launch-new-architecture-new-platform-for-data-center/2/
  104. https://www.intel.com/content/www/us/en/products/sku/126691/intel-c422-chipset/specifications.html
  105. https://www.impactcomponents.com/motherboards/extended-lifecycle/d3598/
Add your contribution
Related Hubs
User Avatar
No comments yet.