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Diffused junction transistor
Diffused junction transistor
Diffused junction transistor
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A diffused junction transistor is a transistor formed by diffusing dopants into a semiconductor substrate. The diffusion process was developed later than the alloy-junction and grown junction processes for making bipolar junction transistors (BJTs).

Bell Labs developed the first prototype diffused junction bipolar transistors in 1954.[1]

Diffused-base transistor

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The earliest diffused junction transistors were diffused-base transistors. These transistors still had alloy emitters and sometimes alloy collectors like the earlier alloy-junction transistors. Only the base was diffused into the substrate. Sometimes the substrate formed the collector, but in transistors like Philco's micro-alloy diffused transistors the substrate was the bulk of the base.

Double diffusion

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At Bell Labs Calvin Souther Fuller produced basic physical understanding of a means of directly forming the emitter, base, and collector by double diffusion. The method was summarized in a history of science at Bell:[2]

"Fuller had shown that acceptors of low atomic weight diffuse more rapidly than donors, which made possible n–p–n structures by simultaneous diffusion of donors and acceptors of appropriately different surface concentrations. The first n layer (the emitter) was formed because of the greater surface concentration of the donor (for example, antimony). The base formed beyond it because of the more rapid diffusion of the acceptor (for example, aluminum). The inner (collector) boundary of the base appeared where the diffused aluminum no longer over-compensated the n-type background doping of the original silicon. The base layers of the resulting transistors were 4 μm thick. ... Resulting transistors had a cut-off frequency of 120 MHz."

Mesa transistor

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Comparison of the mesa (left) and planar (Hoerni, right) technologies. Dimensions are shown schematically.

Texas Instruments made the first grown-junction silicon transistors in 1954.[3] The diffused silicon mesa transistor was developed at Bell Labs in 1955 and made commercially available by Fairchild Semiconductor in 1958.[4]

These transistors were the first to have both diffused bases and diffused emitters. Unfortunately, like all earlier transistors, the edge of the collector–base junction was exposed, making it sensitive to leakage through surface contamination, thus requiring hermetic seals or passivation to prevent degradation of the transistor's characteristics over time.[5]

Planar transistor

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Simplified cross section of a planar npn bipolar junction transistor

The planar transistor was developed by Dr. Jean Hoerni[6] at Fairchild Semiconductor in 1959. The planar process used to make these transistors made mass-produced monolithic integrated circuits possible.

Planar transistors have a silica passivation layer to protect the junction edges from contamination, making inexpensive plastic packaging possible without risking degradation of the transistor's characteristics over time.

The first planar transistors had a switching speed much lower than alloy junction transistors of the period, but as they could be mass-produced, and alloy junction transistors could not, they cost much less, and the characteristics of planar transistors improved very rapidly, quickly exceeding those of all earlier transistors and making earlier transistors obsolete.

References

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Diffused junction transistor

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from Grokipedia
A diffused junction transistor is a type of in which the p-n junctions are created by impurities, such as or , into a substrate like or , allowing for the formation of precise, shallow base regions typically on the order of micrometers in thickness. This fabrication method contrasts with earlier alloy-junction or grown-junction techniques by enabling controlled doping profiles and uniform junction formation through gaseous or solid-state processes at elevated temperatures. The resulting device structure typically features an emitter, base, and collector regions, with the base being the diffused layer, supporting both amplification and switching functions in electronic circuits. The development of diffused junction transistors originated at Bell Laboratories in the early 1950s, building on foundational work in impurity diffusion pioneered by Calvin S. Fuller in 1952, who demonstrated precise diffusion of dopants into germanium and silicon with penetration depths better than 1 micrometer. In 1954, Charles A. Lee applied this technique to fabricate the first diffused-base germanium transistors, achieving base widths of about 1 micrometer and operational frequencies up to 170 MHz—ten times higher than the 10-20 MHz of prior junction transistors. By 1955, Morris Tanenbaum and D.E. Thomas extended the process to silicon, producing n-p-n diffused-base transistors that addressed leakage issues in switching applications, while concurrent efforts by researchers like Carl Frosch and Lincoln Derick introduced silicon dioxide masking for selective diffusion, laying groundwork for planar processing. These innovations were showcased at Bell Labs' landmark 1956 transistor symposium and marked a shift from point-contact and alloyed devices toward scalable semiconductor manufacturing. Diffused junction transistors significantly advanced by providing higher reliability, , and power handling compared to earlier types, facilitating applications in , early computers, and . For instance, double-diffused mesa structures derived from this technology powered systems like IBM's Stretch computer in 1959 and satellites such as in the early . The process also improved to 6% and influenced the toward integrated circuits by enabling photolithographic patterning and impurity control essential for . Although largely superseded by modern epitaxial and ion-implantation methods, diffused junction transistors remain a pivotal milestone in history, contributing to the transistor's role as the cornerstone of digital revolution.

Background and Fundamentals

Junction Formation in Transistors

The (BJT) operates on the principle of two p-n junctions connected back-to-back, forming the emitter-base (EB) and base-collector (BC) junctions that enable controlled current amplification. In an NPN BJT, the emitter and collector regions are heavily doped n-type semiconductors where electrons serve as majority carriers, while the base is a thinner p-type region with holes as majority carriers; conversely, minority carriers consist of electrons in the p-type base and holes in the n-type regions. The EB junction is typically forward-biased to inject minority carriers (electrons from the emitter into the base), which then diffuse across the narrow base and are swept into the collector by the reverse-biased BC junction, generating the primary collector current while minimizing recombination. At each p-n junction, occurs due to the built-in potential difference arising from the alignment of Fermi levels between the p- and n-type materials, creating a where mobile carriers are scarce and an opposes further . This , spanning primarily the lighter-doped side, has a width proportional to the square root of the applied voltage and doping levels, typically on the order of 0.1–1 μm in . Under forward bias, the potential barrier decreases, narrowing the and facilitating minority carrier injection across the junction; in reverse bias, the barrier increases, widening the region and suppressing current flow to a small leakage dominated by thermally generated carriers. These behaviors are essential for BJT operation, as the forward-biased EB junction promotes injection while the reverse-biased BC junction ensures efficient collection, though junction type influences the sharpness of and thus and switching speed. Alloy junction transistors form p-n junctions through a process of fusing metallic dopants, such as pellets, into opposite sides of a thin (often ), creating abrupt interfaces where the p-type regions penetrate the n-type base material. This method results in a base region defined by the residual thickness, which is typically lightly doped and thin, leading to high base resistance that limits current gain and high-frequency performance due to increased RC time constants. Additionally, the approach suffers from poor reproducibility in junction depth and alignment, hindering scalability for and integration into complex circuits, as variations in alloying temperature and contact placement cause inconsistencies across devices. In contrast, diffused junction transistors create p-n junctions by introducing impurities through thermal diffusion into the semiconductor lattice, yielding gradual doping profiles that transition more smoothly from p- to n-type regions. This technique provides precise control over junction depth and dopant concentration via parameters like temperature and duration, enabling base widths as thin as 2.5 μm for enhanced speed. Diffusion also ensures greater uniformity in electrical properties across large wafers, facilitating scalable manufacturing and reducing variations compared to the point-contact nature of alloy methods, though it requires more sophisticated processing equipment.

Diffusion Doping Process

The diffusion doping process involves the solid-state diffusion of impurity atoms, such as for n-type doping or for p-type doping, into a substrate at elevated temperatures typically ranging from 800°C to 1200°C. This process begins with cleaning the wafer to remove contaminants, followed by exposing the surface to a dopant source, such as a gas (e.g., for or for ) or a solid film, in a controlled furnace environment. The dopant atoms then migrate into the lattice through atomic-scale mechanisms, primarily vacancy or diffusion, creating regions of altered conductivity essential for forming p-n junctions in transistors. The of is governed by Fick's first law, which describes the JJ of dopant atoms as proportional to the : J=−DdcdxJ = -D \frac{dc}{dx} where DD is the , cc is the dopant , and xx is the distance into the . The exhibits strong dependence, following the Arrhenius relation: D=D0exp⁡(−EakT)D = D_0 \exp\left(-\frac{E_a}{kT}\right) with D0D_0 as the , EaE_a the (typically 3-5 eV for vacancy or 0.5-1.5 eV for ), kk Boltzmann's constant, and TT the absolute ; this exponential behavior allows precise control of junction depth by adjusting annealing time and . Diffusion occurs in two main steps: predeposition, where dopants are introduced at the surface under constant source conditions to form a shallow, high-concentration layer (resulting in an complementary, or erfc, profile: c(x,t)=cs\erfc(x2Dt)c(x,t) = c_s \erfc\left(\frac{x}{2\sqrt{Dt}}\right)
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