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Computer memory and data storage types
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A ferroelectric field-effect transistor (Fe FET) is a type of field-effect transistor that includes a ferroelectric material sandwiched between the gate electrode and source-drain conduction region of the device (the channel). Permanent electrical field polarisation in the ferroelectric causes this type of device to retain the transistor's state (on or off) in the absence of any electrical bias.

FeFET based devices are used in FeFET memory - a type of single transistor non-volatile memory.

Description

[edit]

In 1955, Ian Munro Ross filed a patent for a FeFET or MFSFET. Its structure was like that of a modern inversion channel MOSFET, but ferroelectric material was used as a dielectric/insulator instead of oxide.[1] Use of a ferroelectric (triglycine sulfate) in a solid state memory was proposed by Moll and Tarui in 1963 using a thin film transistor.[2] Further research occurred in the 1960s, but the retention characteristics of the thin film based devices was unsatisfactory.[3] Early field effect transistor based devices used bismuth titanate (Bi4Ti3O12) ferroelectric, or Pb1−xLnxTiO3 (PLT) and related mixed zirconate/titanates (PLZT).[3] In the late 1980 Ferroelectric RAM was developed, using a ferroelectric thin film as capacitor, connected to an addressing FET.[3]

FeFET based memory devices are read using voltages below the coercive voltage for the ferroelectric.[4]

Issues involved in realising a practical FeFET memory device include (as of 2006) : choice of a high permitivity, highly insulating layer between ferroelectric and gate; issues with high remanent polarisation of ferroelectrics; limited retention time (c. a few days, cf required 10 years).[5]

Provided the ferroelectric layer can be scaled accordingly FeFET based memory devices are expected to scale (shrink) as well as MOSFET devices; however a limit of ~20 nm laterally may exist[6] (the superparaelectric limit, aka ferroelectric limit). Other challenges to feature shrinks include : reduced film thickness causing additional (undesired) polarisation effects; charge injection; and leakage currents.[5]

Research and development

[edit]
Structure of a 1 Transistor FeRAM cell

In 2017 FeFET based non-volatile memory was reported as having been built at 22nm node using FDSOI CMOS (fully depleted silicon on insulator) with hafnium dioxide (HfO2) as the ferroelectric- the smallest FeFET cell size reported was 0.025 μm2, the devices were built as 32Mbit arrays, using set/reset pulses of ~10ns duration at 4.2V - the devices showed endurance of 105 cycles and data retention up to 300C.[7]

As of 2017 the startup Ferroelectric Memory Company is attempting to develop FeFET memory into a commercial device, based on hafnium dioxide. The company's technology is claimed to scale to modern process node sizes, and to integrate with contemporary production processes, i.e. HKMG, and is easily integrable into conventional CMOS processes, requiring only two additional masks.[8]

See also

[edit]
  • Ferroelectric RAM, RAM that uses a ferroelectric material in the capacitor of a conventional DRAM structure

References

[edit]

Further reading

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Fe FET

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A ferroelectric field-effect transistor (FeFET) is a type of that integrates a ferroelectric material as the gate dielectric, allowing the device's channel conductivity to be controlled by the remnant polarization of the ferroelectric layer rather than solely by applied voltage. This configuration enables operation, where the retains its on or off state without continuous , distinguishing it from conventional MOSFETs. FeFETs have emerged as a promising technology for next-generation due to their combination of high-speed switching, low power consumption, and scalability. Key advantages include faster read/write speeds compared to traditional , non-destructive readout capabilities, and high endurance, making them suitable for embedded applications in CMOS-compatible processes. Recent advancements incorporate 2D materials and novel ferroelectric dielectrics like HfO₂-based compounds to address challenges such as interface traps and polarization retention, enhancing performance for both and logic functions. Additionally, FeFETs show potential in and multifunctional devices, leveraging the ferroelectric polarization to regulate carriers in photodetectors and neuromorphic computing elements.

Overview

Definition and Principles

A ferroelectric field-effect transistor (FeFET) is a type of that incorporates a ferroelectric material as the gate , enabling functionality through the retention of polarization states. This integration allows the device to store information by modulating the channel conductivity based on the ferroelectric's spontaneous polarization, which persists without applied voltage. The basic operating principle of an FeFET relies on the ferroelectric polarization to control the formation of the conductive channel in the semiconductor substrate, similar to a conventional FET but with enhanced non-volatility. In standard FETs, channel conductivity is governed by capacitive charge accumulation at the gate dielectric-semiconductor interface, which dissipates when the gate voltage is removed. In contrast, the ferroelectric layer in an FeFET induces a remnant polarization that maintains the channel state (on or off) indefinitely without power consumption, enabling bistable operation for . This polarization switching occurs under applied , creating accumulated or depleted carrier regions at the channel interface. A hallmark of FeFET behavior is the hysteresis observed in its current-voltage (I-V) transfer characteristics, resulting from the reversible polarization switching and potential charge effects during voltage sweeps. This manifests as distinct s for forward and reverse sweeps, corresponding to the two polarization directions. The magnitude of the threshold voltage shift, ΔVth\Delta V_{th}, between these states is given by ΔVth=Pr⋅tfε0⋅εr,\Delta V_{th} = \frac{P_r \cdot t_f}{\varepsilon_0 \cdot \varepsilon_r}, where PrP_r is the remnant polarization, tft_f is the ferroelectric layer thickness, ε0\varepsilon_0 is the vacuum permittivity, and εr\varepsilon_r is the relative permittivity of the ferroelectric material. This shift enables the representation of binary logic states ('0' and '1') through the stable polarization-induced channel modulation, underpinning the device's memory window.

Comparison to Conventional FETs

Ferroelectric field-effect transistors (FeFETs) differ from conventional field-effect transistors (FETs) in their core operating principle, where FeFETs incorporate a ferroelectric layer that enables non-volatility through the retention of spontaneous polarization states, allowing without continuous . In contrast, conventional FETs, such as those used in logic or DRAM, depend on charge storage in the gate or , resulting in volatility where stored information dissipates rapidly without refresh. This ferroelectric polarization in FeFETs introduces a in the transfer characteristics, providing bistable states for functionality, while conventional FETs exhibit linear threshold behavior without inherent retention. Despite these differences, FeFETs and conventional FETs share fundamental similarities in device physics, both utilizing gate voltage to modulate channel conductivity and form an inversion layer in the semiconductor substrate or channel material, inheriting the scalability and integration benefits of silicon-based FET architectures. FeFETs extend this by leveraging the ferroelectric hysteresis for additional non-volatile capabilities, enabling unified logic-memory operations in a single device, whereas conventional FETs require separate memory elements like capacitors in DRAM or floating gates in Flash for data persistence. In terms of performance, FeFETs offer significant advantages in endurance, with demonstrated cycles exceeding 10^{12} in HfO_2-based devices, far surpassing the typical 10^5 program/erase cycles of NAND . Data retention in FeFETs can exceed 10 years due to stable polarization, compared to the milliseconds (around 64 ms) required for periodic refresh in DRAM to prevent . Additionally, FeFETs achieve faster switching speeds, with write and read operations in the sub-nanosecond to 10 ns range, outperforming the slower write latencies (microseconds to milliseconds) of Flash while consuming lower power during state changes owing to the capacitive of ferroelectric switching.

Device Structure and Operation

Architecture Components

The ferroelectric (FeFET) architecture fundamentally consists of a channel, source and drain electrodes, a gate electrode, and a ferroelectric layer serving as the gate insulator. The channel, typically (Si) or two-dimensional materials such as MoS₂ and , provides the conductive pathway for charge carriers modulated by the gate. Source and drain electrodes are formed from metals like (TiN) or (Au) to establish ohmic contacts with the channel. The gate electrode, also metallic (e.g., TiN or ), overlays the ferroelectric layer to apply the control voltage. To mitigate defects and charge trapping at interfaces, a thin buffer or interfacial layer—such as SiO₂, Al₂O₃, or high-k dielectrics—is often inserted between the ferroelectric material and the channel. FeFET structures exhibit several variants tailored to specific integration needs. In the metal-ferroelectric- (MFS) configuration, the ferroelectric layer directly contacts the , enabling compact integration but requiring careful interface control to avoid effects. Alternatively, the metal-ferroelectric-metal (MFM) can be embedded within the gate stack, as in metal-ferroelectric-metal-ferroelectric-insulator- (MFMFIS) or metal-ferroelectric-insulator- (MFIS) setups, where the MFM acts in series with the for enhanced stability. Common device implementations include the 1T-FeFET, a single- structure leveraging the ferroelectric gate for non-volatile storage, and the 1T-1C configuration, which pairs one with a separate MFM connected to the gate for improved endurance and scalability in memory arrays. Scaling FeFETs demands precise optimization of layer thicknesses to preserve functionality while minimizing leakage. The ferroelectric layer is typically engineered to 5-20 nm, such as 10 nm HfO₂-based films, ensuring the coercive field remains below the dielectric breakdown threshold and supporting compatibility with advanced nodes such as sub-10 nm. Thinner ferroelectrics, down to 1.8 nm in HfO₂ variants, enhance remnant polarization retention without sacrificing structural integrity.

Polarization and Switching Mechanism

In ferroelectric field-effect transistors (FeFETs), the polarization of the ferroelectric layer aligns with the direction of the applied , generating bound charges at the ferroelectric-semiconductor interface that modulate the channel carrier concentration and shift the (VthV_{th}). A remnant polarization pointing toward the channel (down state) induces negative charge, depleting the channel and increasing VthV_{th}, while the opposite (up state) induces positive charge, accumulating carriers and decreasing VthV_{th}. This bistable polarization enables non-volatile storage of the two states, with memory windows ranging from 1 to over 15 V depending on the ferroelectric thickness and material. The switching mechanism relies on the reorientation of ferroelectric domains under an applied field exceeding the coercive field (EcE_c), primarily through of reversed domains followed by propagation. occurs preferentially at defects, grain boundaries, or interfaces, forming small regions of opposite polarization, after which domain walls move laterally via sideways expansion driven by the field. In polycrystalline ferroelectrics like HfO₂, the process is often -limited, while in single-crystal or epitaxial films, domain wall motion dominates; the Kolmogorov-Avrami-Ishibashi model describes the temporal evolution of switched polarization as Psw(t)=Ps[1−exp⁡(−(t/τ)m)]P_{sw}(t) = P_s [1 - \exp(-(t/\tau)^m)], where PsP_s is spontaneous polarization, τ\tau is the characteristic time, and mm is the dimensionality exponent (2-3). This contrasts with -dominated switching in thin films, where events control the overall speed. The write operation applies a short voltage (typically 1-5 , with recent demonstrations below 1 , 10 ns to 1 μs duration) to align domains into the desired up or down state, setting the VthV_{th} accordingly. As of , FeFETs have achieved windows up to 19.4 and write voltages as low as 0.9 , enabling enhanced efficiency in advanced applications. The read operation uses a low-voltage to measure drain current (IdI_d), exploiting the >10^3-fold difference in on/off currents between states without reversing polarization, thus ensuring non-destructive readout. However, fields—arising from unscreened bound charges in thin layers (<10 nm)—oppose the remnant polarization, promoting back-switching and limiting retention to 10 years at room temperature only with proper interface engineering. Fatigue from repeated cycling (10^{10}-10^{12} cycles) stems from charge trapping and defect generation, which immobilize domain walls and widen the hysteresis loop. The switching speed is governed by the relation τ≈(a/Ec)n\tau \approx (a / E_c)^n, where aa is the lattice constant, EcE_c is the coercive field, and nn (1-2) reflects dimensionality in nucleation or wall motion regimes; this yields intrinsic times down to picoseconds in defect-free materials, far surpassing conventional charge-trapping memories and enabling MHz operation.

Materials and Fabrication

Ferroelectric Materials

Ferroelectric materials form the core of ferroelectric field-effect transistors (FeFETs), enabling non-volatile memory through reversible polarization that modulates the channel conductivity. Traditional ferroelectric materials, such as lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT), have been widely explored for FeFETs due to their robust ferroelectric properties. PZT exhibits a high remnant polarization (P_r) of up to 50 μC/cm² and a Curie temperature above 300°C, making it suitable for early device prototypes. Similarly, SBT offers good fatigue resistance and thermal stability, with P_r around 10-20 μC/cm², though both materials suffer from processing challenges like high-temperature annealing (>600°C) and in PZT, limiting their scalability in modern silicon-based electronics. Hafnium-based ferroelectrics, particularly doped oxide (HfO₂), have emerged as the leading choice for FeFET integration owing to their compatibility with complementary metal-oxide-semiconductor () processes. Zirconium-doped HfO₂ (HZO), often with additional (Si) or aluminum (Al) doping, stabilizes the non-centrosymmetric orthorhombic phase responsible for , achieving P_r values exceeding 20 μC/cm² in thin films (5-20 nm thick). These materials demonstrate low coercive voltages below 2 V for sub-10 nm thicknesses, enabling low-power switching, and exhibit thermal stability up to 400°C, aligning with back-end-of-line CMOS thermal budgets. The high bandgap (~5.5 eV) of HfO₂ ensures low leakage currents (<10^{-7} A/cm² at 1 MV/cm), crucial for maintaining polarization states. In FeFETs, this polarization contributes to threshold voltage shifts of over 1 V, directly influencing device on/off characteristics. Emerging two-dimensional (2D) ferroelectric materials, such as CuInP₂S₆ (CIPS), offer promise for ultra-scaled FeFETs by enabling van der Waals heterostructures with minimal lattice mismatch. CIPS displays room-temperature ferroelectricity with a Curie temperature of ~315 K and P_r around 3-5 μC/cm², though enhancements via stacking or doping aim to boost these values. Its layered structure facilitates integration with 2D channel materials like MoS₂ or WSe₂, potentially reducing interface traps. Selection of ferroelectric materials for FeFETs prioritizes criteria such as lattice matching to silicon (e.g., HfO₂'s cubic structure aligns well with Si, minimizing defects), low leakage to preserve charge retention, and against imprint—a polarization offset over time due to charge trapping that can degrade memory windows after 10^6 cycles. Hafnium-based films excel here, with optimized doping reducing imprint shifts to <0.5 V after baking at 125°C for 1000 hours, while traditional perovskites like PZT often require buffer layers to address ~10% lattice mismatch with Si. Overall, these properties ensure reliable operation, with HfO₂ variants demonstrating >10^{10} cycle in optimized structures.

Integration and Processing Techniques

The integration of ferroelectric materials into FeFETs involves precise deposition techniques to achieve thin, uniform films compatible with silicon-based processes. (ALD) is widely used for hafnium oxide (HfO₂)-based ferroelectrics, enabling precise control over film thickness down to a few nanometers while maintaining conformal coverage on complex gate structures. , particularly radio-frequency magnetron sputtering, is employed for (PZT) films, offering high deposition rates and the ability to incorporate dopants for enhanced ferroelectric properties. Post-deposition, rapid thermal annealing (RTA) at 500–700°C crystallizes the films and stabilizes the ferroelectric orthorhombic phase, typically lasting 10–60 seconds in an oxygen ambient to minimize defects. Fabrication challenges arise from the need to maintain ferroelectric functionality amid constraints. Interface traps at the ferroelectric-semiconductor boundary promote charge trapping, which degrades stability and retention over cycles. Scaling the ferroelectric layer below 10 nm is hindered by thermodynamic , as thinner films tend to revert to non-ferroelectric monoclinic phases, limiting memory density. BEOL compatibility demands processing temperatures under 400°C to prevent or damage to interconnects, yet traditional annealing often exceeds this, necessitating alternative low-thermal-budget methods like or annealing. Advances in processing have addressed these issues through targeted modifications. Doping with elements like or mitigates the wake-up effect—where initial polarization increases with cycling—by suppressing oxygen vacancy migration and promoting uniform domain formation. Multi-layer stacks, such as HfO₂/SiO₂ or doped HfO₂ heterostructures, enhance film uniformity, reduce leakage, and improve endurance by engineering strain and interface properties during deposition and annealing.

Applications

Non-Volatile Memory

Ferroelectric field-effect transistors (FeFETs) serve as embedded (eNVM) devices, offering a compelling alternative to traditional due to their integration compatibility with processes. These transistors leverage the ferroelectric polarization in the gate stack to store data non-volatily by shifting the , enabling fast access times in the range of 10-100 ns. This speed advantage stems from the direct electrical switching of polarization without requiring charge trapping or tunneling mechanisms inherent in NOR flash. Furthermore, FeFETs achieve high areal densities up to 10 Gb/cm² through scalable architectures, while maintaining low write energies below 1 pJ per bit, making them suitable for power-constrained embedded applications. In terms of configurations, standalone FeFET cells operate as 1T (one-transistor) memory units, effectively replacing NOR flash in code storage for microcontrollers and embedded systems by providing simpler integration and reduced cell size compared to 1T-1C FeRAM cells. These cells program and erase via voltage pulses that align the ferroelectric domains, storing '0' or '1' states based on the resulting shift. For higher density arrays, shared- architectures distribute control signals across multiple FeFETs, similar to NOR array layouts, which minimizes peripheral overhead and supports without the block-level constraints of NAND flash. Such designs have been demonstrated in HfO₂-based prototypes, achieving compatibility with advanced nodes below 28 nm. Recent 2025 developments include dual-bit FeFET configurations achieving enhanced storage density and endurance beyond 10^8 cycles. Key performance metrics underscore FeFETs' viability for non-volatile storage. Retention exceeds 10 years at 85°C, as the stable polarization states resist thermal depolarization, with extrapolated data from accelerated bake tests confirming long-term . Endurance reaches 10¹⁰ to >10¹¹ cycles in optimized HfO₂ or doped variants, far surpassing NOR flash's typical 10⁵ cycles, due to the ferroelectric material's fatigue-resistant domain switching. Readout is non-destructive, employing amplifiers to detect drain current differences between programmed states without altering the polarization, thus avoiding read disturb issues common in charge-based memories. These attributes position FeFETs as a high-reliability option for eNVM in IoT and automotive applications.

Logic and Neuromorphic Computing

FeFETs enable logic applications through in-memory computing paradigms, where the ferroelectric polarization states modulate the 's to represent binary or multi-level logic values, allowing computations to occur directly within the array without frequent shuttling between separate logic and storage units. This approach supports reconfigurable logic gates and analog multipliers by exploiting 2-4 polarization states per , facilitating operations such as 2-bit multiply-accumulate (MAC) in a single cell via time-encoded activations and . For instance, complementary FeFET (CFeFET) structures can implement multifunction gates like multiplexers and logic with reduced power overhead compared to traditional designs. In neuromorphic computing, FeFETs serve as artificial synapses by storing multi-level synaptic weights through gradual polarization switching, enabling up to 64 or more intermediate conductance states for analog weight representation in brain-inspired architectures. This multi-level capability, combined with low-voltage operation (typically below 2 V), supports energy-efficient AI accelerators, with switching energies as low as 10 fJ per synaptic operation, significantly outperforming conventional CMOS-based synapses in power-constrained environments. Ferroelectric field-effect transistors integrated into crossbar arrays mimic , allowing on-chip learning and inference with minimal external control circuitry. Representative examples include FeFET-based neural networks achieving over 90% accuracy in tasks, such as 96.6% on the MNIST dataset using a 32×32 crossbar for with less than 2% degradation under device variations. Hybrid CMOS-FeFET chips further enhance by combining non-volatile FeFET synapses with peripherals, enabling efficient on-device inference for image classification, as demonstrated in VGG-8 networks reaching 90.3% accuracy on while consuming approximately 2 fJ per operation. These integrations leverage the non-volatility of FeFETs to maintain low standby power in resource-limited settings.

Research and Development

Historical Milestones

The concept of the ferroelectric field-effect transistor (FeFET) was first proposed in 1963 by J. L. Moll and Y. Tarui, who described a structure incorporating a ferroelectric gate insulator, such as triglycine sulfate, to enable non-volatile storage through polarization-induced channel conductance modulation. This theoretical foundation highlighted the potential for FeFETs as compact, low-power memory devices, building on earlier ideas of in semiconductors. The first experimental silicon-based FeFET prototype was demonstrated in 1974 by S. Y. Wu, who fabricated a metal-ferroelectric-semiconductor (MFS) transistor using a bismuth titanate (Bi4Ti3O12) film deposited on a silicon substrate, achieving bistable memory states with a threshold voltage shift due to ferroelectric polarization reversal. In the 1980s, initial prototypes explored organic ferroelectrics like poly(vinylidene fluoride) (PVDF) on silicon to improve compatibility and flexibility, though these devices suffered from poor retention and interface traps, limiting practical viability. During the 1990s, significant progress occurred with the integration of (PZT) thin films into silicon-based FeFETs, as researchers at institutions including developed buffer layers to mitigate interdiffusion and enable epitaxial growth, resulting in devices with improved polarization switching and memory windows up to several volts. A major breakthrough came in 2011 with the discovery of in doped hafnium oxide (HfO2) thin films by T. S. Böscke and colleagues at and , revealing an orthorhombic phase stabilized by dopants like or that is fully compatible with processes, enabling scalable FeFETs without lead-based materials. This led to demonstrations at advanced nodes, including a 22 nm fully depleted silicon-on-insulator (FDSOI) FeFET in 2017 by , which exhibited ultra-low power operation with write energies below 1 fJ per bit and retention over 10 years. In 2018, introduced the first commercial FeFET-based embedded technology in their 22 nm FDSOI platform, offering designers process design kits for integration into logic circuits with read speeds exceeding 10 GHz and compatibility with standard flows. In 2024, advancements enabled flexible FeFETs using HfO2 on bendable substrates, demonstrated for wearable applications with mechanical endurance over 10,000 cycles and sensitivities suitable for strain sensing in health monitoring devices.

Recent Advances and Challenges

Recent advances in FeFET technology since 2020 have focused on enhancing , multi-functionality, and integration density to meet demands for next-generation memory and computing. One key innovation involves 2D FeFETs utilizing MoS₂ channels, enabling ultra-scaling to sub-5 nm gate lengths through van der Waals ferroelectric heterostructures that minimize short-channel effects and support low-voltage operation below 1 V. These devices leverage the atomic thickness of 2D materials to achieve high on/off ratios exceeding 10⁶ and endurance over 10⁶ cycles, paving the way for beyond-Moore scaling in . Another breakthrough is the development of multi-state FeFETs, demonstrated in a 2024 study achieving up to 16 discrete states for in-memory computing applications. This multi-level quantization, enabled by precise control of partial switching in HfO₂-based ferroelectrics, supports analog synaptic weights with low power consumption under 10 fJ per operation, enhancing efficiency in neuromorphic systems. Complementing these, 3D stacked FeFET arrays have been proposed to boost storage density, with simulations showing feasibility for vertical integrations of HfO₂ ferroelectrics on IGZO channels with up to 128 layers, and experimental demonstrations of 3-tier monolithic stacking, while maintaining retention over 10 years at 85°C. Despite these progresses, significant challenges persist in FeFET reliability and manufacturability. Imprint and retention degradation at elevated temperatures above 150°C remain critical issues, as accelerates in HfO₂ films, leading to significant loss in memory window after prolonged baking. Variability in polarization uniformity across devices, stemming from random ferroelectric phase distributions and interface traps, results in shifts of 200-500 mV, complicating multi-level operations and yield in large arrays. Additionally, the cost of doping processes for stabilizing ferroelectric phases in HfO₂—such as Zr or Al incorporation via —poses economic hurdles, with high-temperature annealing requirements adding to fabrication complexity and costs compared to conventional dielectrics. Looking ahead, FeFET integration at the 5 nm node is under development, as outlined in industry roadmaps, potentially enabling hybrid ferroelectric-perovskite stacks for optoelectronic applications like light-tunable synapses with responsivities over 10⁴ A/W. As of , ongoing focuses on cryogenic compatibility for quantum integration, with projected commercialization expansions. These advancements could address current limitations through improved material , fostering widespread adoption in AI hardware and beyond-silicon electronics.

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