Community hub
Recent from talks
Contribute something
Nothing was collected or created yet.
Racetrack memory
View on Wikipedia | This article needs to be updated. (December 2021) |
| Computer memory and data storage types |
|---|
| Volatile |
| Non-volatile |
Racetrack memory or domain-wall memory (DWM) is an experimental non-volatile memory device under development at IBM's Almaden Research Center by a team led by physicist Stuart Parkin.[1] It is a current topic of active research at the Max Planck Institute of Microstructure Physics in Dr. Parkin's group. In early 2008, a 3-bit version was successfully demonstrated.[2] If it were to be developed successfully, racetrack memory would offer storage density higher than comparable solid-state memory devices like flash memory.[citation needed]
Description
[edit]Racetrack memory uses a spin-coherent electric current to move magnetic domains along a nanoscopic permalloy wire about 200 nm across and 100 nm thick. As current is passed through the wire, the domains pass by magnetic read/write heads positioned near the wire, which alter the domains to record patterns of bits. A racetrack memory device is made up of many such wires and read/write elements. In general operational concept, racetrack memory is similar to the earlier bubble memory of the 1960s and 1970s. Delay-line memory, such as mercury delay lines of the 1940s and 1950s, are a still-earlier form of similar technology, as used in the UNIVAC and EDSAC computers. Like bubble memory, racetrack memory uses electrical currents to "push" a sequence of magnetic domains through a substrate and past read/write elements. Improvements in magnetic detection capabilities, based on the development of spintronic magnetoresistive sensors, allow the use of much smaller magnetic domains to provide far higher bit densities.
In production, it was expected[citation needed] that the wires could be scaled down to around 50 nm. There were two arrangements considered for racetrack memory. The simplest was a series of flat wires arranged in a grid with read and write heads arranged nearby. A more widely studied arrangement used U-shaped wires arranged vertically over a grid of read/write heads on an underlying substrate. This would allow the wires to be much longer without increasing its 2D area, although the need to move individual domains further along the wires before they reach the read/write heads results in slower random access times. Both arrangements offered about the same throughput performance. The primary concern in terms of construction was practical; whether or not the three dimensional vertical arrangement would be feasible to mass-produce.
Comparison to other memory devices
[edit]Projections in 2008 suggested that racetrack memory would offer performance on the order of 20-32 ns to read or write a random bit. This compared to about 10,000,000 ns for a hard drive, or 20-30 ns for conventional DRAM. The primary authors discussed ways to improve the access times with the use of a "reservoir" to about 9.5 ns. Aggregate throughput, with or without the reservoir, would be on the order of 250-670 Mbit/s for racetrack memory, compared to 12800 Mbit/s for a single DDR3 DRAM, 1000 Mbit/s for high-performance hard drives, and 1000 to 4000 Mbit/s for flash memory devices. The only current technology that offered a clear latency benefit over racetrack memory was SRAM, on the order of 0.2 ns, but at a higher cost. Larger feature size "F" of about 45 nm (as of 2011) with a cell area of about 140 F2.[3][4]
Racetrack memory is one among several emerging technologies that aim to replace conventional memories such as DRAM and Flash, and potentially offer a universal memory device applicable to a wide variety of roles. Other contenders included magnetoresistive random-access memory (MRAM), phase-change memory (PCRAM) and ferroelectric RAM (FeRAM). Most of these technologies offer densities similar to flash memory, in most cases worse, and their primary advantage is the lack of write-endurance limits like those in flash memory. Field-MRAM offers excellent performance as high as 3 ns access time, but requires a large 25-40 F² cell size. It might see use as an SRAM replacement, but not as a mass storage device. The highest densities from any of these devices is offered by PCRAM, with a cell size of about 5.8 F², similar to flash memory, as well as fairly good performance around 50 ns. Nevertheless, none of these can come close to competing with racetrack memory in overall terms, especially density. For example, 50 ns allows about five bits to be operated in a racetrack memory device, resulting in an effective cell size of 20/5=4 F², easily exceeding the performance-density product of PCM. On the other hand, without sacrificing bit density, the same 20 F² area could fit 2.5 2-bit 8 F² alternative memory cells (such as resistive RAM (RRAM) or spin-torque transfer MRAM), each of which individually operating much faster (~10 ns).
In most cases, memory devices store one bit in any given location, so they are typically compared in terms of "cell size", a cell storing one bit. Cell size itself is given in units of F², where "F" is the feature size design rule, representing usually the metal line width. Flash and racetrack both store multiple bits per cell, but the comparison can still be made. For instance, hard drives appeared to be reaching theoretical limits around 650 nm²/bit,[5] defined primarily by the capability to read and write to specific areas of the magnetic surface. DRAM has a cell size of about 6 F², SRAM is much less dense at 120 F². NAND flash memory is currently the densest form of non-volatile memory in widespread use, with a cell size of about 4.5 F², but storing three bits per cell for an effective size of 1.5 F². NOR flash memory is slightly less dense, at an effective 4.75 F², accounting for 2-bit operation on a 9.5 F² cell size.[4] In the vertical orientation (U-shaped) racetrack, nearly 10-20 bits are stored per cell, which itself would have a physical size of at least about 20 F². In addition, bits at different positions on the "track" would take different times (from ~10 to ~1000 ns, or 10 ns/bit) to be accessed by the read/write sensor, because the "track" would move the domains at a fixed rate of ~100 m/s past the read/write sensor.
Development challenges
[edit]One limitation of the early experimental devices was that the magnetic domains could be pushed only slowly through the wires, requiring current pulses on the orders of microseconds to move them successfully. This was unexpected, and led to performance equal roughly to that of hard drives, as much as 1000 times slower than predicted. Recent research has traced this problem to microscopic imperfections in the crystal structure of the wires which led to the domains becoming "stuck" at these imperfections. Using an X-ray microscope to directly image the boundaries between the domains, their research found that domain walls would be moved by pulses as short as a few nanoseconds when these imperfections were absent. This corresponds to a macroscopic performance of about 110 m/s.[6]
The voltage required to drive the domains along the racetrack would be proportional to the length of the wire. The current density must be sufficiently high to push the domain walls (as in electromigration). A difficulty for racetrack technology arises from the need for high current density (>108 A/cm2); a 30 nm x 100 nm cross-section would require >3 mA. The resulting power draw becomes higher than that required for other memories, e.g., spin-transfer torque memory (STT-RAM) or flash memory.
Another challenge associated with racetrack memory is the stochastic nature in which the domain walls move, i.e., they move and stop at random positions.[7] There have been attempts to overcome this challenge by producing notches at the edges of the nanowire.[8] Researchers have also proposed staggered nanowires to pin the domain walls precisely.[9] Experimental investigations have shown[10] the effectiveness of staggered domain wall memory.[11] Recently researchers have proposed non-geometrical approaches such as local modulation of magnetic properties through composition modification. Techniques such as annealing induced diffusion[12] and ion-implantation[13] are used.
See also
[edit]- Giant magnetoresistance (GMR) effect
- Magnetoresistive random-access memory (MRAM)
- Spintronics
- Spin transistor
References
[edit]- ^ "Spintronics Devices Research, Magnetic Racetrack Memory Project". Archived from the original on 12 October 2007. Retrieved 15 September 2007.
- ^ Masamitsu Hayashi; et al. (April 2008). "Current-Controlled Magnetic Domain-Wall Nanowire Shift Register". Science. 320 (5873): 209–211. Bibcode:2008Sci...320..209H. doi:10.1126/science.1154587. PMID 18403706. S2CID 7872869.
- ^ "ITRS 2011". Archived from the original on 31 January 2013. Retrieved 8 November 2012.
- ^ a b Parkin; et al. (11 April 2008). "Magnetic Domain-Wall Racetrack Memory". Science. 320 (5873): 190–4. Bibcode:2008Sci...320..190P. doi:10.1126/science.1145799. PMID 18403702. S2CID 19285283.
- ^ 1 Tbit/in2 is approx. 650nm²/bit.
- ^ Swarup, Amarendra (11 May 2007). "'Racetrack' memory could gallop past the hard disk". New Scientist.
- ^ Kumar, D.; Jin, T.; Risi, S. Al; Sbiaa, R.; Lew, W. S.; Piramanayagam, S. N. (March 2019). "Domain Wall Motion Control for Racetrack Memory Applications". IEEE Transactions on Magnetics. 55 (3) 2876622. Bibcode:2019ITM....5576622K. doi:10.1109/TMAG.2018.2876622. hdl:10356/139037. ISSN 0018-9464. S2CID 67872687.
- ^ Hayashi, M.; Thomas, L.; Moriya, R.; Rettner, C.; Parkin, S. S. P. (2008). "Current-Controlled Magnetic Domain-Wall Nanowire Shift Register". Science. 320 (5873): 209–211. Bibcode:2008Sci...320..209H. doi:10.1126/science.1154587. ISSN 0036-8075. PMID 18403706. S2CID 7872869.
- ^ Mohammed, H. (2020). "Controlled spin-torque driven domain wall motion using staggered magnetic wires". Applied Physics Letters. 116 (3): 032402. arXiv:1908.09304. Bibcode:2020ApPhL.116c2402M. doi:10.1063/1.5135613. S2CID 201695574.
- ^ Prem Piramanayagam (24 February 2019), Staggered Domain Wall Memory, archived from the original on 21 December 2021, retrieved 13 March 2019
- ^ Al Bahri, M.; Borie, B.; Jin, T.L.; Sbiaa, R.; Kläui, M.; Piramanayagam, S.N. (8 February 2019). "Staggered Magnetic Nanowire Devices for Effective Domain-Wall Pinning in Racetrack Memory". Physical Review Applied. 11 (2) 024023. Bibcode:2019PhRvP..11b4023A. doi:10.1103/PhysRevApplied.11.024023. hdl:10220/48230. S2CID 139224277.
- ^ Jin, T. L.; Ranjbar, M.; He, S. K.; Law, W. C.; Zhou, T. J.; Lew, W. S.; Liu, X. X.; Piramanayagam, S. N. (2017). "Tuning magnetic properties for domain wall pinning via localized metal diffusion". Scientific Reports. 7 (1): 16208. Bibcode:2017NatSR...716208J. doi:10.1038/s41598-017-16335-z. PMC 5701220. PMID 29176632.
- ^ Jin, Tianli; Kumar, Durgesh; Gan, Weiliang; Ranjbar, Mojtaba; Luo, Feilong; Sbiaa, Rachid; Liu, Xiaoxi; Lew, Wen Siang; Piramanayagam, S. N. (2018). "Nanoscale Compositional Modification in Co/Pd Multilayers for Controllable Domain Wall Pinning in Racetrack Memory". Physica Status Solidi RRL. 12 (10) 1800197. Bibcode:2018PSSRR..1200197J. doi:10.1002/pssr.201800197. hdl:10356/137507. S2CID 52557582.
External links
[edit]- Redefining the Architecture of Memory
- IBM Moves Closer to New Class of Memory (YouTube video)
- IBM Racetrack Memory Project Archived 29 August 2013 at the Wayback Machine
Racetrack memory
View on GrokipediaCore Concepts
Operating Principle
Racetrack memory relies on the controlled displacement of magnetic domain walls within ferromagnetic nanowires to store and manipulate digital information. These nanowires function as linear "racetracks," where binary bits are encoded by the positions of domain walls that separate adjacent magnetic domains with opposite magnetization directions. Each domain wall represents a bit boundary, allowing multiple bits to be stored sequentially along the track without the need for individual cells. This approach leverages the stability of magnetic domains in ferromagnets, where below the Curie temperature, exchange interactions align electron spins into macroscopic magnetization, forming domains to minimize demagnetizing fields, with domain walls as narrow transition zones (typically 10–100 nm wide) where magnetization rotates between domains. The concept draws from spintronics, the field exploiting electron spin alongside charge for device functionality, enabling non-volatile storage with low energy dissipation.[4] Domain wall motion in racetrack memory is primarily driven by spin-transfer torque (STT) or spin-orbit torque (SOT), both rooted in spin angular momentum transfer to the lattice magnetization. In STT, spin-polarized electrons from a current flowing parallel to the nanowire experience a misalignment of their spin with the local magnetization at the domain wall, leading to absorption of spin angular momentum that generates a torque, propelling the wall along the track in the direction opposite to electron flow. This adiabatic process couples the electron spin to the texture of the magnetization, effectively dragging the wall at speeds proportional to current density. The domain wall velocity in the adiabatic STT regime follows from the torque balance in the Landau-Lifshitz-Gilbert equation augmented by Slonczewski-like terms, yielding , where is the reduced Planck's constant, is the elementary charge, is the saturation magnetization, and is the current density (assuming polarization ).[4][5] Alternatively, SOT arises from spin currents generated via the spin Hall effect in an adjacent heavy-metal layer, where charge current produces transverse spin accumulation that diffuses into the ferromagnet, exerting a damping-like torque (with the magnetization unit vector and perpendicular to the interface), enabling efficient, current-in-plane domain wall drive without Joule heating in the magnetic layer. The resulting velocity scales similarly, often , where is the spin Hall angle and is the Gilbert damping parameter, though exact forms depend on wall chirality and pinning.[6] Data writing in racetrack memory involves applying pulsed currents to shift domain walls to desired positions, effectively encoding bit patterns by adjusting the sequence of up and down domains; for instance, a positive current pulse moves walls in one direction to insert or expand domains, while reversal writes the complement. This process exploits the torque-induced dynamics to position multiple walls precisely along the track, with stability provided by intrinsic pinning from edge roughness or engineered notches. Reading occurs via magnetoresistive sensing of the local magnetization state: integrated read heads, such as magnetic tunnel junctions (MTJs), detect resistance changes due to the relative orientation of fixed and free layers aligned with the domain magnetization, allowing non-destructive readout of bit values as walls are shuttled past the sensor. Anomalous Hall or anisotropic magnetoresistance effects can also probe the domain configuration electrically, ensuring high signal-to-noise ratios at nanoscale dimensions. These operations enable dense, three-dimensional stacking of tracks while maintaining coherence over thousands of bits.[4][7]Device Architecture
Racetrack memory devices consist of arrays of magnetic nanowires, referred to as racetracks, which function as the core storage elements. These nanowires are typically linear in horizontal configurations, lying parallel to the substrate plane, or U-shaped in vertical setups, oriented perpendicular to the substrate for enhanced density. They are fabricated from soft ferromagnetic materials such as permalloy (Ni₈₁Fe₁₉), with dimensions including widths of 100–500 nm and thicknesses of 10–50 nm.[4] Advanced implementations utilize Co/Ni multilayers to enable perpendicular magnetic anisotropy, supporting more stable domain wall configurations.[8] Read and write operations are facilitated by integrated transverse access ports that enable non-destructive access to data along the racetrack. These ports incorporate magnetic tunnel junctions (MTJs) for reading, positioned adjacent to or in direct contact with the nanowire to sense magnetic states via magnetoresistance. Writing is achieved through localized application of magnetic fields or spin-transfer torque at these ports, allowing precise control over domain wall positions.[4] The design inherently supports three-dimensional stacking to scale storage capacity, employing vertical arrays of racetracks formed as tall columns of magnetic material on a silicon substrate. Access ports are embedded within each layer, aligned to intersect domain walls efficiently across the stacked structure. IBM's 2008 prototype architecture, based on this vertical configuration, enables high areal densities through 3D integration.[4]Historical Development
Origins and Invention
Racetrack memory was first proposed in 2002 by Stuart S. P. Parkin, a physicist at IBM's Almaden Research Center, as a novel spintronic approach to address the growing "memory wall" in computing—the widening performance gap between rapidly advancing processor speeds and the slower evolution of memory technologies.[1] This concept emerged from Parkin's earlier work on magnetic storage, including a foundational U.S. patent filed in 2001 (issued in 2004) describing a shiftable magnetic shift register that utilized current to manipulate magnetic domains along a nanowire track.[9] The invention aimed to create a solid-state, non-volatile memory device capable of achieving the high storage density of hard disk drives (HDDs) while offering the speed and reliability of dynamic random-access memory (DRAM), thereby overcoming the mechanical limitations and scaling challenges of traditional HDDs, such as slow access times exceeding 10 milliseconds and vulnerability to mechanical failure.[1] The initial motivation drew directly from the impending limits of HDD scaling in the early 2000s, where areal densities had increased dramatically thanks to advancements in read-head technology, but further progress was constrained by physical and mechanical barriers. Parkin envisioned racetrack memory as a way to store data in a series of magnetic domains separated by domain walls along nanoscale "racetracks" (nanowires), with data bits shifted via spin-polarized currents rather than mechanical motion. This design promised terabit-per-square-inch densities in a fully electronic form factor, eliminating moving parts while maintaining non-volatility. Early theoretical work, including Parkin's 2008 seminal paper in Science, outlined the core architecture: arrays of horizontal or vertical magnetic nanowires on a silicon chip, where domain walls serve as mobile data carriers.[1] The development of racetrack memory was deeply rooted in the broader progress of spintronics during the 2000s, particularly the exploitation of electron spin for information processing and storage. Parkin's own discovery of giant magnetoresistance (GMR) in 1988 had revolutionized HDD read heads by enabling detection of weaker magnetic fields from smaller domains, paving the way for multi-gigabyte drives and earning him the 2007 Nobel Prize in Physics. By the early 2000s, these spintronic principles—combining charge and spin degrees of freedom—had matured sufficiently to inspire non-volatile memory innovations like racetrack, which leverages GMR-based sensors for reading domain wall positions.[1]Key Milestones
Following the proposal and patenting of racetrack memory by Stuart S. P. Parkin at IBM in the early 2000s, with key details published in a 2008 Science paper, the period from 2009 to 2012 saw initial experimental demonstrations of current-induced domain wall motion in nanowires. In 2009, IBM researchers reported the first controlled motion of domain walls using spin-polarized currents in permalloy nanowires, establishing the feasibility of shifting magnetic domains along linear tracks without mechanical components.[10] By 2011, the team advanced to demonstrating the synchronous movement of multiple domain walls in series along nanowires, validating key operational principles for multi-bit storage.[11] These efforts culminated in 2012 with the fabrication of a 256-bit prototype chip incorporating U-shaped nanowire arrays, where domain walls were successfully read and shifted bidirectionally.[12] In 2013, significant progress was made in device architecture, with simulations showing the integration of dedicated read ports along U-shaped tracks enabling multi-bit storage and access. These designs projected areal densities of 1 Tb/in² through vertical stacking of nanowires, optimizing for efficient domain wall positioning and non-destructive readout without excessive power dissipation.[13] From 2016 to 2019, the adoption of spin-orbit torque mechanisms dramatically improved domain wall motion efficiency and speed, addressing limitations of earlier spin-transfer torque approaches. Researchers reported domain wall velocities exceeding 100 m/s in heavy-metal/ferromagnet bilayers, driven by spin Hall and Rashba effects that generate torque perpendicular to the current flow.[14] These advances were bolstered by collaborations, including work with Tohoku University on spintronics integration for scalable tracks and New York University on torque optimization in synthetic antiferromagnets.[15][16] In 2020, prototypes demonstrated integrated racetrack arrays with enhanced thermal stability and read/write operations, advancing toward practical implementations.[2] By 2025, reports of buffer-layer-free ultrathin devices marked further progress in material efficiency and three-dimensional stacking.[3] Funding and partnerships played a crucial role in these developments, with DARPA supporting spintronics initiatives like the C-Spin center (launched in 2013) that advanced domain wall dynamics for memory applications.[15] IBM's internal roadmap outlined progressive prototypes toward commercialization, targeting integration with CMOS processes by the late 2010s while emphasizing low-power multi-gigabit arrays.[17]Performance Characteristics
Advantages and Benefits
Racetrack memory offers significant potential for high storage density through its unique domain wall-based architecture, which allows multiple bits to be stored along a single nanowire in a compact linear arrangement. By leveraging three-dimensional stacking of vertical nanowires, it can achieve densities surpassing the limitations of two-dimensional flash memory, with projections enabling areal densities on the order of 1 Tb/in² or higher in advanced configurations.[18] This is facilitated by the ability to pack numerous magnetic domains per track, such as up to 150 bits per nanowire using short domain wall separations around 40 nm.[19] As a non-volatile memory technology, racetrack memory retains data indefinitely without power, similar to hard disk drives, while providing much faster access times that bridge the gap between dynamic random-access memory (DRAM) and traditional storage. Domain walls can be shifted at speeds allowing read and write operations in less than 10 ns, enabling nanosecond-scale access comparable to solid-state memories but with persistent storage.[20][21] This combination addresses the volatility issues of DRAM and the speed bottlenecks of non-volatile alternatives like flash.[22] Energy efficiency is a key strength, particularly for write operations, where spin-orbit torque mechanisms enable low-power domain wall motion at approximately 1-10 pJ per bit. Recent 2025 advancements in ultrathin devices have demonstrated even lower energies approaching 0.1 pJ per bit.[23][3] This is achieved through current-induced shifting that minimizes energy overhead compared to charge-based writing in other memories, with demonstrated reductions in overall cache energy consumption by up to 73% in cache applications.[23] Non-volatility further eliminates static power leakage, contributing to sustained low-power operation during idle states.[19] Scalability remains promising for future nodes, as racetrack memory can operate effectively below 10 nm without the leakage currents that plague semiconductor-based memories, relying instead on magnetic domain stability enhanced by perpendicular magnetic anisotropy materials. This compatibility with existing CMOS processes supports integration into high-density chips while maintaining performance at nanoscale dimensions.[24][25]Comparisons to Other Memory Types
Racetrack memory positions itself as a promising universal memory technology, aiming to bridge the gap between volatile high-speed memories like DRAM and SRAM and non-volatile storage options such as NAND flash and MRAM. It combines the non-volatility and high endurance of MRAM with storage densities approaching those of hard disk drives (HDDs), potentially enabling a single memory type to replace multiple tiers in the memory hierarchy.[18][26] Key performance metrics highlight racetrack memory's trade-offs and advantages relative to established technologies. The following table summarizes representative comparisons based on theoretical and demonstrated capabilities as of 2025 (note: racetrack values are largely theoretical; others reflect current commercial products):| Metric | Racetrack Memory | DRAM | SRAM | NAND Flash | MRAM |
|---|---|---|---|---|---|
| Density | >1 Tb/in² (theoretical, with 3D stacking) | ~200 Gb/in² (at 1γ node, 2025) | ~40 Gb/in² (at advanced nodes, 2025) | >10 Tb/in² (areal, 3D stacked, 200+ layers) | ~50 Gb/in² (planar, STT-MRAM) |
| Access Speed | 1–10 ns (read/write) | ~10–20 ns (read), ~20–40 ns (write) | <5 ns (read/write) | ~10–100 µs (read), ~1 ms (write) | ~10 ns (read/write) |
| Endurance | >10¹² cycles | Unlimited (but volatile) | Unlimited (but volatile) | ~10³–10⁵ cycles (TLC/QLC) | ~10¹⁰–10¹² cycles |
| Power | Low static power (non-volatile, no refresh) | High dynamic power (refresh required) | High static power (always on) | Low static, moderate write energy | Low static, low write energy |