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Phase-change memory
Phase-change memory
Phase-change memory
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Computer memory and data storage types
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Volatile
RAM
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Non-volatile
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Early-stage NVRAM
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Phase-change memory (also known as PCM, PCME, PRAM, PCRAM, OUM (ovonic unified memory) and C-RAM or CRAM (chalcogenide RAM)) is a type of non-volatile random-access memory. PRAMs exploit the unique behaviour of chalcogenide glass. In PCM, heat produced by the passage of an electric current through a heating element generally made of titanium nitride is used to either quickly heat and quench the glass, making it amorphous, or to hold it in its crystallization temperature range for some time, thereby switching it to a crystalline state.[1] PCM also has the ability to achieve a number of distinct intermediary states, thereby having the ability to hold multiple bits in a single cell[2].

Recent research on PCM has been directed towards attempting to find viable material alternatives to the phase-change material Ge2Sb2Te5 (GST), with mixed success. Other research has focused on the development of a GeTe–Sb2Te3 superlattice to achieve non-thermal phase changes by changing the co-ordination state of the germanium atoms with a laser pulse. This new Interfacial Phase-Change Memory (IPCM) has had many successes and continues to be the site of much active research.[3]

Leon Chua has argued that all two-terminal non-volatile-memory devices, including PCM, should be considered memristors.[4] Stan Williams of HP Labs has also argued that PCM should be considered a memristor.[5] However, this terminology has been challenged, and the potential applicability of memristor theory to any physically realizable device is open to question.[6][7]

Background

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In the 1960s, Stanford R. Ovshinsky of Energy Conversion Devices first explored the properties of chalcogenide glasses as a potential memory technology. In 1969, Charles Sie published a dissertation at Iowa State University that both described and demonstrated the feasibility of a phase-change-memory device by integrating chalcogenide film with a diode array.[8][9] A cinematographic study in 1970 established that the phase-change-memory mechanism in chalcogenide glass involves electric-field-induced crystalline filament growth.[10][11] In the September 1970 issue of Electronics, Gordon Moore, co-founder of Intel, published an article on the technology.[12] However, material quality and power consumption issues prevented commercialization of the technology. More recently, interest and research have resumed as flash and DRAM memory technologies are expected to encounter scaling difficulties as chip lithography shrinks.[13]

The crystalline and amorphous states of chalcogenide glass have dramatically different electrical resistivity values. The amorphous, high resistance state represents a binary 0, while the crystalline, low resistance state represents a 1.[citation needed] Chalcogenide is the same material used in re-writable optical media (such as CD-RW and DVD-RW). In those instances, the material's optical properties are manipulated, rather than its electrical resistivity, as chalcogenide's refractive index also changes with the state of the material.

Although PRAM has not yet reached the commercialization stage for consumer electronic devices, nearly all prototype devices make use of a chalcogenide alloy of germanium (Ge), antimony (Sb) and tellurium (Te) called GeSbTe (GST). The stoichiometry, or Ge:Sb:Te element ratio, is 2:2:5 in GST. When GST is heated to a high temperature (over 600 °C), its chalcogenide crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state [14] and its electrical resistance is high. By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. A crystallization time scale on the order of 100 ns is commonly used.[15] This is longer than conventional volatile memory devices like modern DRAM, which have a switching time on the order of two nanoseconds. However, a January 2006 Samsung Electronics patent application indicates PRAM may achieve switching times as fast as five nanoseconds.

A 2008 advance pioneered by Intel and ST Microelectronics allowed the material state to be more carefully controlled, allowing it to be transformed into one of four distinct states: the previous amorphous or crystalline states, along with two new partially crystalline ones. Each of these states has different electrical properties that can be measured during reads, allowing a single cell to represent two bits, doubling memory density.[16]

Aluminum/antimony

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Phase-change memory devices based on germanium, antimony and tellurium present manufacturing challenges, since etching and polishing of the material with chalcogens can change the material's composition. Materials based on aluminum and antimony are more thermally stable than GeSbTe. Al50Sb50 has three distinct resistance levels, offering the potential to store three bits of data in two cells as opposed to two (nine states possible for the pair of cells, using eight of those states yields log2 8 = 3 bits).[17][18]

A cross-section of two PRAM memory cells. One cell is in low resistance crystalline state, the other in high resistance amorphous state.

PRAM vs. Flash

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PRAM's switching time and inherent scalability[19] make it more appealing than flash memory. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology.

Flash memory works by modulating charge (electrons) stored within the gate of a MOS transistor. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or in insulator "traps"). The presence of charge within the gate shifts the transistor's threshold voltage higher or lower, corresponding to a change in the cell's bit state from 1 to 0 or 0 to 1. Changing the bit's state requires removing the accumulated charge, which demands a relatively large voltage to "suck" the electrons off the floating gate. This burst of voltage is provided by a charge pump, which takes some time to build up power. General write times for common flash devices are on the order of 100 μs (for a block of data), about 10,000 times the typical 10 ns read time for SRAM for example (for a byte).[citation needed]

PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times faster than conventional hard drives, makes it particularly interesting in nonvolatile memory roles that are currently performance-limited by memory access timing.

In addition, with flash, each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are rated for, currently, only 5,000 writes per sector, and many flash controllers perform wear leveling to spread writes across many physical sectors.

PRAM devices also degrade with use, for different reasons than flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles.[20] PRAM lifetime is limited by mechanisms such as degradation due to GST thermal expansion during programming, metal (and other material) migration, and other mechanisms still unknown.

Flash parts can be programmed before being soldered onto a board, or even purchased pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (see reflow soldering or wave soldering). This was made worse by the requirement to have lead-free manufacturing requiring higher soldering temperatures. A manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place.

The special gates used in flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The resistivity of the memory element in PRAM is more stable; at the normal working temperature of 85 °C, it is projected to retain data for 300 years.[21]

By carefully modulating the amount of charge stored on the gate, flash devices can store multiple (usually two) bits in each physical cell. In effect, this doubles the memory density, reducing cost. PRAM devices originally stored only a single bit in each cell, but Intel's recent advances have removed this problem.[citation needed]

Because flash devices trap electrons to store information, they are susceptible to data corruption from radiation, making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.

PRAM cell selectors can use various devices: diodes, BJTs and MOSFETs. Using a diode or a BJT provides the greatest amount of current for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. Chalcogenide resistance is necessarily larger than that of a diode, meaning operating voltage must exceed 1 V by a wide margin to guarantee adequate forward bias current from the diode. Perhaps the most severe consequence of using a diode-selected array, in particular for large arrays, is the total reverse bias leakage current from the unselected bit lines. In transistor-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40 nm is the effect of discrete dopants as the p-n junction width scales down. Thin film-based selectors allow higher densities, utilizing < 4 F2 cell area by stacking memory layers horizontally or vertically. Often the isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Chalcogenide-based threshold switches have been demonstrated as a viable selector for high-density PCM arrays [22]

2000 and later

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In August 2004, Nanochip licensed PRAM technology for use in MEMS (micro-electric-mechanical-systems) probe storage devices. These devices are not solid state. Instead, a very small platter coated in chalcogenide is dragged beneath thousands or even millions of electrical probes that can read and write the chalcogenide. Hewlett-Packard's micro-mover technology can accurately position the platter to 3 nm so densities of more than 1 Tbit (125 GB) per square inch will be possible if the technology can be perfected. The basic idea is to reduce the amount of wiring needed on-chip; instead of wiring every cell, the cells are placed closer together and read by current passing through the MEMS probes, acting like wires. This approach resembles IBM's Millipede technology.

Samsung 46.7 nm cell

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In September 2006, Samsung announced a prototype 512 Mb (64 MB) device using diode switches.[23] The announcement was something of a surprise, and it was especially notable for its fairly high memory density. The prototype featured a cell size of only 46.7 nm, smaller than commercial flash devices available at the time. Although flash devices of higher capacity were available (64 Gb, or 8 GB, was just coming to market), other technologies competing to replace flash in general offered lower densities (larger cell sizes). The only production MRAM and FeRAM devices are only 4 Mb, for example. The high density of Samsung's prototype PRAM device suggested it could be a viable flash competitor, and not limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potential replacement for NOR flash, where device capacities typically lag behind those of NAND flash devices. State-of-the-art capacities on NAND passed 512 Mb some time ago. NOR flash offers similar densities to Samsung's PRAM prototype and already offers bit addressability (unlike NAND where memory is accessed in banks of many bytes at a time).

Intel's PRAM device

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Samsung's announcement was followed by one from Intel and STMicroelectronics, who demonstrated their own PRAM devices at the 2006 Intel Developer Forum in October.[24] They showed a 128 Mb part that began manufacture at STMicroelectronics's research lab in Agrate, Italy. Intel stated that the devices were strictly proof-of-concept.

BAE device

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PRAM is also a promising technology in the military and aerospace industries where radiation effects make the use of standard non-volatile memories such as flash impractical. PRAM devices have been introduced by BAE Systems, referred to as C-RAM, claiming excellent radiation tolerance (rad-hard) and latchup immunity. In addition, BAE claims a write cycle endurance of 108, which will allow it to be a contender for replacing PROMs and EEPROMs in space systems.

Multi-level cell

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In February 2008, Intel and STMicroelectronics revealed the first multilevel (MLC) PRAM array prototype. The prototype stored two logical bits in each physical cell, in effect 256 Mb of memory stored in a 128 Mb physical array. This means that instead of the normal two states—fully amorphous and fully crystalline—an additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area.[16] In June 2011,[25] IBM announced that they had created stable, reliable, multi-bit phase-change memory with high performance and stability. SK Hynix had a joint developmental agreement and a technology license agreement with IBM for the development of multi-level PRAM technology.[26]

Intel's 90 nm device

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Also in February 2008, Intel and STMicroelectronics shipped prototype samples of their first PRAM product to customers. The 90 nm, 128 Mb (16 MB) product was called Alverstone.[27]

In June 2009, Samsung and Numonyx B.V. announced a collaborative effort in the development of PRAM market-tailored hardware products.[28]

In April 2010,[29] Numonyx announced the Omneo line of 128-Mbit NOR-compatible phase-change memories. Samsung announced shipment of 512 Mb phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile handsets by Fall 2010.

ST 28 nm, 16 MB array

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In December 2018 STMicroelectronics presented design and performance data for a 16 MB ePCM array for a 28 nm fully depleted silicon on insulator automotive control unit.[30]

In-memory computing

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More recently, there is significant interest in the application of PCM for in-memory computing.[31] The essential idea is to perform computational tasks such as matrix-vector-multiply operations in the memory array itself by exploiting PCM's analog storage capability and Kirchhoff's circuit laws. PCM-based in-memory computing could be interesting for applications such as deep learning inference which do not require very high computing precision.[32] In 2021, IBM published a full-fledged in-memory computing core based on multi-level PCM integrated in 14 nm CMOS technology node.[33]

Challenges

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The greatest challenge for phase-change memory has been the requirement of high programming current density (>107 A/cm2, compared to 105...106 A/cm2 for a typical transistor or diode). [citation needed] The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose adhesion when expanding at a different rate from the phase-change material.

Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions that allow for fast crystallization should not be too similar to standby conditions, e.g. room temperature, otherwise data retention cannot be sustained. With the proper activation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions.

Probably the biggest challenge for phase-change memory is its long-term resistance and threshold voltage drift.[34] The resistance of the amorphous state slowly increases according to a power law (~t0.1). This severely limits the ability for multilevel operation, since a lower intermediate state would be confused with a higher intermediate state at a later time, and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.

In April 2010, Numonyx released its Omneo line of parallel and serial interface 128 Mb NOR flash replacement PRAM chips. Although the NOR flash chips they intended to replace operated in the −40-85 °C range, the PRAM chips operated in the 0-70 °C range, indicating a smaller operating window compared to NOR flash. This is likely due to the use of highly temperature-sensitive p–n junctions to provide the high currents needed for programming.

Timeline

[edit]
  • January 1955: Kolomiets and Gorunova revealed semiconducting properties of chalcogenide glasses.[35][36]
  • September 1966: Stanford Ovshinsky files first patent on phase-change technology
  • January 1969: Charles H. Sie published a dissertation at Iowa State University on chalcogenide phase-change-memory device
  • June 1969: US Patent 3,448,302 (Shanefield) licensed to Ovshinsky claims first reliable operation of PRAM device
  • September 1970: Gordon Moore publishes research in Electronics Magazine
  • June 1999: Ovonyx joint venture is formed to commercialize PRAM technology
  • November 1999: Lockheed Martin works with Ovonyx on PRAM for space applications
  • February 2000: Intel invests in Ovonyx, licenses technology
  • December 2000: ST Microelectronics licenses PRAM technology from Ovonyx
  • March 2002: Macronix files a patent application for transistor-less PRAM
  • July 2003: Samsung begins work on PRAM technology
  • 2003 through 2005: PRAM-related patent applications filed by Toshiba, Hitachi, Macronix, Renesas, Elpida, Sony, Matsushita, Mitsubishi, Infineon and more
  • August 2004: Nanochip licenses PRAM technology from Ovonyx for use in MEMS probe storage
  • August 2004: Samsung announces successful 64 Mbit PRAM array
  • February 2005: Elpida licenses PRAM technology from Ovonyx
  • September 2005: Samsung announces successful 256 Mbit PRAM array, touts 400 μA programming current
  • October 2005: Intel increases investment in Ovonyx
  • December 2005; Hitachi and Renesas announce 1.5 V PRAM with 100 μA programming current
  • December 2005: Samsung licenses PRAM technology from Ovonyx
  • July 2006: BAE Systems begins selling the first commercial PRAM chip
  • September 2006: Samsung announces 512 Mbit PRAM device
  • October 2006: Intel and STMicroelectronics show a 128 Mbit PRAM chip
  • December 2006: IBM Research Labs demonstrate a prototype 3 by 20 nanometers[37]
  • January 2007: Qimonda licenses PRAM technology from Ovonyx
  • April 2007: Intel's chief technology officer Justin Rattner is set to give the first public demonstration of the company's PRAM (phase-change RAM) technology [38]
  • October 2007: Hynix begins pursuing PRAM by licensing Ovonyx' technology
  • February 2008: Intel and STMicroelectronics announce four-state MLC PRAM[16] and begin shipping samples to customers.[27]
  • December 2008: Numonyx announces mass production 128 Mbit PRAM device to selected customer.
  • June 2009: Samsung's phase-change RAM will go into mass production starting in June[39]
  • September 2009: Samsung announces mass production start of 512 Mbit PRAM device[40]
  • October 2009: Intel and Numonyx announce they have found a way to stack phase-change memory arrays on one die[41]
  • December 2009: Numonyx announces 1 Gb 45 nm product[42]
  • April 2010: Numonyx releases Omneo PRAM Series (P8P and P5Q), both in 90 nm.[43]
  • April 2010: Samsung releases 512 Mbit PRAM with 65 nm process, in Multi-Chip-Package.[44]
  • February 2011: Samsung presented 58 nm 1.8V 1 Gb PRAM.[45]
  • February 2012: Samsung presented 20 nm 1.8V 8 Gb PRAM[46]
  • July 2012: Micron announces availability of Phase-Change Memory for mobile devices - the first PRAM solution in volume production[47]
  • January 2014: Micron withdraws all PCM parts from the market.[48]
  • May 2014: IBM demonstrates combining PCM, conventional NAND, and DRAM on a single controller[49]
  • August 2014: Western Digital demonstrates prototype PCM storage with 3 million I/Os and 1.5 microsecond latency[50]
  • July 2015: Intel and Micron announced 3D Xpoint memory where phase-change alloy is used as a storage part of a memory cell.

See also

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References

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

Phase-change memory

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Phase-change memory (PCM), also known as phase-change random access memory (PCRAM), is a technology that stores data by inducing reversible structural changes in phase-change materials, typically chalcogenide alloys, between an amorphous (high-resistance) state and a crystalline (low-resistance) state. This is achieved through electrical pulses that heat the material, enabling without power and offering scalability down to nanometer dimensions. The concept of phase-change memory traces its origins to the 1960s, when Stanford Ovshinsky discovered the Ovshinsky effect in chalcogenide glasses, demonstrating reversible switching between amorphous and crystalline phases for memory applications. Commercial development accelerated in the , with the first PCM product—a 128-Mbit chip—released by Numonyx in 2008, followed by Intel's Optane technology in 2018 (discontinued in 2022), which integrated 3D-stacked PCM for storage-class memory bridging DRAM and NAND flash. As of 2025, PCM is primarily deployed in embedded systems, with companies like and advancing embedded PCM (ePCM) for microcontrollers, and ongoing research focusing on overcoming endurance limits to exceed 10¹² write cycles. At its core, PCM operates as a two-terminal resistive device where a heater electrode delivers via current pulses: short, high-amplitude pulses (~10 μA in advanced designs) amorphize the material (reset, storing '0'), while longer, lower-amplitude pulses crystallize it (set, storing '1'), resulting in resistance differences of 2–3 orders of magnitude. Key materials include Ge₂Sb₂Te₅ (GST), a prototypical chalcogenide , alongside emerging alternatives like GeTe-based composites, Sb-rich variants for improved , and SiTeₓ nano-filaments that reduce reset currents and enable multilevel storage. Recent innovations, such as nanoconfinement and defect (e.g., Bi-doping in GeTe), enhance thermal stability, minimize resistance drift, and lower power consumption, with switching speeds reaching <20 ns for resets. PCM's advantages include non-volatility, high density potential (<10 nm scaling), fast read/write speeds (e.g., 6.75 μs read, 12 μs write in Optane), and compatibility with CMOS fabrication, positioning it as a successor to flash memory for applications in AI accelerators and neuromorphic computing. However, challenges persist, such as thermal crosstalk in dense arrays, limited write endurance compared to DRAM, and higher initial costs, though advancements like superlattices (e.g., Sb₂Te₃/GeTe) have reduced thermal conductivity by 40% to mitigate these issues. Emerging uses extend to in-memory computing for edge devices and synaptic emulation in brain-inspired hardware.

Fundamentals

Operating Principle

Phase-change memory (PCM) stores data by exploiting the reversible phase transitions in chalcogenide materials between an amorphous state, which exhibits high electrical resistance and represents logic 0, and a crystalline state, which has low electrical resistance and represents logic 1. The amorphous state is formed by rapid cooling from the melt, resulting in a disordered atomic structure that impedes electron flow, while the crystalline state is achieved through controlled annealing, allowing for ordered atomic arrangement and enhanced conductivity. The switching processes rely on electrical pulses to induce Joule heating in the phase-change material. In the SET operation, a moderate current pulse heats the material to its crystallization temperature (typically around 150–300°C), enabling atomic rearrangement into the crystalline state without melting; this process, often called annealing, lowers the resistance. Conversely, the RESET operation uses a higher-amplitude, shorter-duration current pulse to rapidly heat the material above its melting point (around 600–700°C), followed by a quick quench to freeze it into the amorphous state, thereby increasing resistance. These thermal transitions are driven by the power dissipated as heat, given by the equation P=I2R,P = I^2 R, where PP is the power, II is the applied current, and RR is the material resistance, with the resulting temperature rise determining the phase change. For reading data, a low-voltage bias is applied to sense the resistance without disturbing the phase state, as the read current is kept below the threshold that would trigger switching. The basic electrical model of PCM features a resistance ratio between the amorphous and crystalline states typically ranging from 10310^3 to 10410^4, providing sufficient contrast for reliable detection, along with a threshold voltage (around 1–5 V, depending on device geometry) that initiates the non-linear switching behavior.

Materials and Physics

Phase-change memory primarily utilizes chalcogenide alloys, with the Ge-Sb-Te (GST) family, particularly Ge₂Sb₂Te₅, serving as the most widely adopted material due to its suitable phase-switching properties. These alloys exhibit a glass transition temperature of approximately 150–200°C, enabling stable amorphous states at room temperature, a crystallization temperature around 140–160°C for rapid switching, and a melting point near 600–650°C to facilitate amorphization via melt-quenching. The physics of phase change in these materials revolves around the reversible transition between amorphous and crystalline states, driven by thermal or electrical stimuli. In the amorphous phase, atoms are arranged in a disordered structure with short-range order, resembling a frozen supercooled liquid, which results in high electrical resistivity due to localized charge transport and a wide bandgap. Conversely, the crystalline phase features a long-range ordered lattice, typically hexagonal or face-centered cubic in GST, promoting delocalized electrons and metallic-like conductivity, with resistivity dropping by several orders of magnitude. This stark contrast in electrical properties underpins data storage, where the amorphous state represents high resistance (logical '0') and the crystalline state low resistance (logical '1'). Accompanying the electrical changes, these materials display significant optical reflectivity variations between phases, a property first exploited in rewritable optical discs like CDs and DVDs. The amorphous phase scatters light more diffusely, reducing reflectivity, while the crystalline phase enhances specular reflection due to its ordered structure, enabling optical readout with contrast ratios up to 50%. Crystallization kinetics follow thermal activation models, primarily involving nucleation and growth processes. Nucleation initiates at heterogeneous sites or homogeneously in the undercooled melt, followed by anisotropic growth via atomic diffusion, with the overall rate governed by an Arrhenius-type dependence on temperature. The crystallization time tcryt_{\text{cry}} can be approximated as tcry∼exp⁡(EakT),t_{\text{cry}} \sim \exp\left(\frac{E_a}{kT}\right), where EaE_a is the activation energy (typically 2–3 eV for Ge₂Sb₂Te₅), kk is Boltzmann's constant, and TT is the temperature; this reflects the diffusion-controlled nature of the transition in the relevant temperature range of 500–650 K.

Historical Background

Early Discoveries

The foundational observations of phase-change memory trace back to the mid-20th century, when researchers began exploring the unique electrical properties of chalcogenide materials. In 1955, scientists B.T. Kolomiets and N.A. Goryunova at the Ioffe Institute of the Soviet Academy of Sciences discovered the semiconducting properties of chalcogenide glasses, revealing that these amorphous materials exhibited electrical conductivity akin to crystalline semiconductors under certain conditions. This breakthrough highlighted the potential of chalcogenides for novel electronic applications, as their glassy structure allowed for tunable resistivity without the need for long-range order. During the 1960s, further investigations into amorphous semiconductors uncovered threshold switching phenomena, where high electric fields induced a rapid, reversible transition from high to low resistance states. Pioneering work by W.R. Northover and G.L. Pearson at in 1964 first observed this threshold switching in chalcogenide glasses, demonstrating a voltage-dependent snap-back in current that returned to the initial state upon removal of the field. These experiments laid the groundwork for understanding how applied voltage could trigger non-linear conduction in amorphous materials, a key mechanism for memory-like behavior. Subsequent studies expanded on these findings, showing that threshold switching was widespread in chalcogenide systems due to field-enhanced carrier generation and thermal effects. These discoveries occurred alongside parallel developments in optical technologies, where similar phase-change principles in chalcogenides enabled rewritable optical discs. In the 1980s, researchers at companies like Matsushita demonstrated phase-change media for rewritable discs, using laser-induced amorphous-to-crystalline transitions in Te-based alloys to store and erase data optically, achieving multiple rewrite cycles with high stability. This context underscored the versatility of chalcogenide phase changes for both electrical and optical memory applications.

Ovshinsky's Contributions

Stanford R. Ovshinsky, a self-taught inventor and scientist, played a pivotal role in pioneering phase-change memory through his work on amorphous chalcogenide materials in the 1960s and 1970s. Building briefly on 1950s discoveries of chalcogenide glass properties, Ovshinsky's innovations focused on electrical switching behaviors that enabled non-volatile memory applications. His inventions laid the intellectual foundation for devices that reversibly switch between amorphous (high-resistance) and crystalline (low-resistance) states via . In 1966, Ovshinsky received U.S. Patent 3,271,591 for the "Symmetrical current controlling device," describing an Ovonic threshold switch using thin-film chalcogenides like Te-As-Ge that exhibited negative differential resistance and rapid, reversible switching under applied voltage. This device served as a precursor to memory elements by demonstrating voltage-controlled conductivity changes in amorphous semiconductors. Two years later, in a landmark 1968 publication, Ovshinsky detailed bistable, non-volatile switching in disordered chalcogenide structures, where electrical pulses induced phase transitions for data storage, effectively inventing the core concept of . To advance commercialization, Ovshinsky co-founded Energy Conversion Devices (ECD) in 1964—evolving from the 1960 Energy Conversion Laboratory—to develop and license "Ovonic" technologies based on amorphous materials. Throughout the 1970s, ECD researchers under Ovshinsky's direction demonstrated reliable non-volatile bistable switching in thin-film devices, showcasing endurance over multiple cycles and potential for array integration, which highlighted the scalability of these memory switches. In 1976, ECD entered a development agreement with North American Philips (including its Signetics subsidiary) to prototype Ovonic memory devices, marking an early industry push toward practical implementation. Ovshinsky's broader "Ovonics" framework unified these advances into a theory of amorphous semiconductors, positing that structural disorder in chalcogenides enables filamentary conduction and phase-change effects suitable for both memory and computational elements, challenging traditional crystalline semiconductor paradigms.

Development and Milestones

2000s Prototypes

In 2000, Energy Conversion Devices (ECD) and Intel established the joint venture Ovonyx to commercialize phase-change memory technology, building on foundational patents by Stanford Ovshinsky for chalcogenide-based non-volatile memory. Ovonyx focused on developing PRAM devices, licensing the technology and collaborating with semiconductor firms to integrate amorphous semiconductor materials into practical chips. In 2004, Samsung announced a 64 Mbit PRAM prototype fabricated using a 0.18 μm CMOS process, integrating Ge₂Sb₂Te₅ chalcogenide material into a 1T1R cell structure for non-volatile storage. This prototype demonstrated reliable phase transitions between amorphous and crystalline states, achieving read/write speeds competitive with DRAM while maintaining non-volatility. In 2006, BAE Systems began selling the first commercial radiation-hard 512 Kbit × 8 PRAM chip designed for aerospace applications, emphasizing resilience to total ionizing dose and single-event effects, suitable for space and military systems. The device utilized chalcogenide materials to provide non-volatile memory with resilience to total ionizing dose and single-event effects, suitable for space and military systems. In 2007, Samsung developed a 512 Mbit PRAM chip on a 90 nm process, featuring a diode-switch architecture that enabled higher density and improved manufacturability. Concurrently, Intel produced the 128 Mbit Alverstone test chip at 90 nm, a prototype that validated phase-change integration for NOR flash replacement with faster write latencies. In September 2006, Samsung announced a prototype PRAM with a 46.7 nm cell size, demonstrating potential for high-density scaling. During the mid-2000s, early experiments with multi-level cell (MLC) configurations in phase-change memory achieved four distinct resistance states per cell by controlling partial crystallization levels in the chalcogenide layer. These MLC prototypes, tested in 0.18 μm and 90 nm nodes, demonstrated potential for doubling storage density without significant endurance loss, though drift and margin challenges required further optimization.

2010s Advancements

During the 2010s, phase-change memory (PCM) technology advanced significantly through process node scaling and integration improvements, building on earlier 2000s prototypes that demonstrated basic single-level cell functionality. In 2011, a 90 nm embedded PCM macro of 4 Mbit was integrated into standard CMOS technology using a low-voltage MOS selector, achieving 12 ns read times and demonstrating feasibility for microcontroller units (MCUs) in embedded applications. Further progress in array demonstration came from STMicroelectronics, which in 2017 announced embedded phase-change memory (ePCM) integration with 28 nm fully depleted silicon-on-insulator (FDSOI) processes, enabling large-scale arrays for automotive MCUs with excellent current distributions and endurance up to 10,000 cycles. A pivotal commercial launch occurred in 2015 when Intel and Micron introduced 3D XPoint technology, leveraging PCM principles in a 3D crosspoint architecture for non-volatile storage-class memory; initial modules reached 128 Gbit capacities, offering up to 1,000 times the endurance and 10 times the performance of NAND flash. This marked PCM's transition from research to market-ready products, with stacked layers enhancing density and access speeds. Research prototypes in the 2010s also explored multi-level cells (MLC) to boost storage density, with demonstrations of 3-4 bits per cell using refined programming schemes to distinguish multiple resistance states reliably. IBM's 2011 512-Mbit 2-bit/cell array at 90 nm and 2013 extension to 4-bit/cell highlighted the potential, though challenges like resistance drift required advanced error-correction techniques. Concurrently, early explorations into in-memory computing utilized PCM arrays for analog vector operations, such as matrix-vector multiplications, by exploiting the devices' tunable conductance states to perform computations directly in the memory array, reducing data movement overhead in neural network primitives. These efforts laid groundwork for PCM's role beyond storage, emphasizing its analog computing capabilities in high-impact applications.

Recent Developments

In 2022, Intel discontinued its Optane product line, which was based on 3D XPoint phase-change memory technology, primarily due to persistent cost challenges and limited market adoption despite years of development. Despite this commercial setback, research into (PCM) persisted, with academic and industry efforts focusing on overcoming scalability and efficiency barriers to sustain its potential as a non-volatile memory solution. Between 2023 and 2024, significant progress emerged in low-power PCM materials, particularly Sb-rich alloys such as Sb2Te3 variants, which demonstrated enhanced thermal stability and reduced power consumption for high-density applications. These alloys, often nanostructured or doped, achieved endurance levels exceeding 10^12 cycles in prototype devices, enabling reliable operation for data-intensive uses while minimizing energy requirements during phase transitions. Complementary advancements in materials like In2Se3 further supported low-power switching by improving crystallization kinetics and compatibility with flexible electronics. In 2025, key publications highlighted breakthroughs in extending PCM switching endurance through targeted doping strategies, such as those reducing RESET currents to prevent over-programming and material degradation. For instance, a Nature Communications study detailed how nano-confined structures and carbon doping in Ge-Sb-Te alloys achieved endurance beyond 1.1 × 10¹¹ cycles, with current reductions in optimized cells. Concurrently, rumors surfaced regarding SanDisk's development of 3D Matrix Memory, speculated to revive PCM through a stacked, phase-change-based architecture that could integrate seamlessly with existing NAND ecosystems for higher densities. The PCM market, valued at $328 million in 2025, is projected to reach $2.5 billion by 2034, growing at a compound annual rate of 25.6%, largely propelled by demands from AI training workloads and edge computing devices requiring fast, persistent storage. This expansion underscores PCM's role in bridging DRAM and flash performance gaps, with applications in neuromorphic systems driving adoption. GeTe-based PCM has also advanced toward optical-electrical hybrid computing paradigms, where its reversible phase transitions enable integrated photonic-electronic devices for low-latency data processing. Recent implementations leverage GeTe's high optical contrast and electrical tunability in metasurfaces and ring resonators, facilitating energy-efficient in-memory computations for AI accelerators.

Device Technologies

Cell Structures

Phase-change memory cells typically employ chalcogenide materials like Ge₂Sb₂Te₅ (GST) confined between electrodes to enable phase transitions between amorphous and crystalline states for data storage. One fundamental architecture is the pore cell, where the GST is confined within a sublithographic pore etched into an insulating dielectric layer atop the bottom electrode, minimizing the active volume to reduce switching power and improve thermal efficiency. This design localizes the phase-change region, preventing lateral heat spreading and enhancing scalability. Another prevalent structure is the mushroom cell, featuring a larger GST volume between top and bottom electrodes, with a confined "mushroom cap" region at the interface where the phase transition occurs due to localized heating from the bottom electrode. In this configuration, the bottom electrode acts as a heater, generating Joule heat to amorphize or crystallize the GST dome-shaped active zone. Mushroom cells offer robust endurance, supporting up to 10⁹ cycles before degradation in optimized setups. Electrode configurations often utilize titanium nitride (TiN) for the bottom electrode due to its thermal stability and compatibility with semiconductor processes, paired with a tungsten (W) heater to efficiently deliver current and heat to the GST layer. Self-heating designs further optimize power consumption by positioning the hotspot within the phase-change material itself, reducing reliance on external heaters and minimizing thermal losses. These approaches can lower reset currents by incorporating carbon-based liners or nanostructured interfaces in pillar-shaped cells. For higher-density arrays, 3D crosspoint architectures stack multiple layers of perpendicular word and bit lines, placing PCM cells at their intersections in a selector-based configuration using Ovonic Threshold Switches that leverage the material's threshold switching for access control. This design, exemplified in technologies like , enables dense integration without transistors per cell, though it requires careful management of sneak currents. To support multi-level cell (MLC) operation, differential cells incorporate two PCM elements per bit, allowing precise resistance sensing through differential readout that mitigates drift and noise for reliable multi-state storage. This paired structure enhances accuracy in distinguishing intermediate resistance levels. Phase-change memory cells are designed for back-end-of-line (BEOL) compatibility with CMOS processes, using low-temperature fabrication steps below 400°C to integrate seamlessly above logic transistors without degrading underlying silicon circuitry. Such integration supports embedded applications in advanced nodes like 28 nm FD-SOI.

Scaling and Integration

Phase-change memory (PCM) devices have followed a scaling roadmap that began with demonstrations at the 180 nm technology node in 2003, progressing to the 28 nm node by 2018 through innovations in cell design and material processing. This progression enabled higher densities, with early 180 nm cells achieving data retention at 85°C for ten years, while 28 nm implementations incorporated novel test structures to maintain performance metrics like resistance contrast. Scaling has relied on reducing the active volume of the phase-change material to sustain efficient amorphization and crystallization. Below 20 nm, scaling faces significant challenges, particularly in achieving thermal confinement to localize heating and prevent cross-talk between adjacent cells. Volume reduction of the phase-change material exacerbates these issues by complicating the melting and rapid quenching processes required for state switching, potentially leading to incomplete phase transitions and reliability degradation. Advanced electrode materials, such as carbon nanotubes, have been explored to enhance thermal boundaries at these scales, confining crystalline paths to approximately 1.2 nm. To overcome planar scaling limits, 3D stacking has emerged as a key strategy, employing multi-layer crosspoint arrays that enable vertical integration for increased capacity. In technologies like Intel's Optane, which utilized phase-change mechanisms in a 3D crosspoint configuration, densities up to 1 Tb have been realized through layered architectures that boost overall storage volume while maintaining access speeds. These arrays achieve cell areas as small as 4 F², supporting ultra-high densities exceeding 10¹⁰ cm⁻² in neuromorphic and storage applications. Recent advancements as of 2025 include nano-confined structures in mushroom-type devices demonstrating endurance exceeding 10¹¹ cycles. Additionally, nitrogen-doped Cr₂Ge₂Te₆ phase-change materials have been developed to lower switching energy in next-generation cells. Integration of PCM into larger systems requires compatibility with complementary metal-oxide-semiconductor (CMOS) logic processes, particularly in the back-end-of-line (BEOL) metallization stages. Precise via alignment during BEOL fabrication ensures electrical connectivity without compromising underlying transistor performance, allowing monolithic embedding of memory arrays atop logic circuitry. Conventional fabrication techniques, including those for selectors and electrodes, facilitate this co-integration at temperatures compatible with BEOL constraints. Yield improvements in PCM fabrication have been achieved through defect reduction techniques, such as optimizing the thickness of the phase-change layer to 10-50 nm, which minimizes voids and improves uniformity during deposition. This range balances electrical contact resistance with phase-transition efficiency, enabling endurance exceeding 10⁶ cycles in test structures while reducing fabrication variability. Power scaling in PCM has advanced via material engineering, reducing switching current densities from approximately 10 MA/cm² in early designs to below 1 MA/cm² in optimized configurations. Techniques like interfacial thermoelectric layers and superlattice structures in Ge-Sb-Te alloys achieve densities as low as 0.1 MA/cm², lowering reset energies by over an order of magnitude through enhanced heating efficiency and reduced thermal dissipation. These tweaks, including dopant additions and electrode modifications, support sub-10 ns programming pulses while preserving multilevel cell operation.

Comparisons

With Flash Memory

Phase-change memory (PCM) offers significant advantages over NAND flash in performance metrics, particularly in write and read latencies. PCM achieves write speeds on the order of 10-100 ns, compared to NAND flash's typical write times in the microsecond to millisecond range, enabling faster data updates without the need for block-level erasures. Read operations in PCM are also rapid, around 10 ns, approaching dynamic random-access memory (DRAM) levels, while NAND flash reads generally take about 25 μs. These differences stem from PCM's ability to perform in-place byte-addressable writes by inducing phase transitions in chalcogenide materials via localized heating, bypassing the page or block programming constraints of NAND flash. In terms of reliability, PCM demonstrates superior endurance, supporting up to 10^9 write cycles per cell, far exceeding NAND flash's typical 10^4 to 10^5 cycles. This high endurance arises from the reversible amorphous-crystalline phase changes in PCM materials, which avoid the wear mechanisms like charge trapping in NAND flash's floating-gate structures. Additionally, PCM eliminates the need for pre-erasure of entire blocks before writing, reducing operational overhead and enhancing reliability in frequent-update scenarios. Density and cost remain areas where NAND flash holds an edge due to its mature 3D-stacked architectures, achieving areal densities up to several Tb/cm² at lower costs per gigabit. In contrast, PCM densities are currently lower, though scalable through multi-level cells and 3D integration, but manufacturing complexities with chalcogenide materials result in higher $/Gb pricing. However, PCM's byte-addressable nature provides efficiency advantages for applications requiring fine-grained access, potentially offsetting costs in targeted uses. Power consumption in PCM involves higher write voltages, typically 1-3 V, to generate the necessary thermal pulses for phase switching, but overall energy per bit is lower—on the order of femtojoules—compared to NAND flash's picojoule-range writes that require elevated voltages around 15-20 V for charge injection. This makes PCM more power-efficient for random, low-volume writes, though NAND flash excels in sequential bulk operations due to optimized controller designs. Use-case wise, PCM positions itself as storage-class memory, bridging the performance gap between DRAM and NAND flash by offering non-volatility with near-DRAM speeds for caching and persistent workloads. NAND flash, conversely, dominates bulk storage in solid-state drives and consumer devices where high density and low cost outweigh the need for rapid random access.

With Other Non-Volatile Memories

Phase-change memory (PCM) offers non-volatility similar to other emerging non-volatile memories, providing data retention without power, in contrast to dynamic random-access memory (DRAM), which is volatile and requires periodic refresh cycles to maintain data. While PCM achieves read speeds comparable to DRAM at around 10-50 ns, its write latency is higher, typically 20-400 ns compared to DRAM's sub-10 ns access times, though both operate in the nanosecond regime overall. This persistence without refresh enables PCM to bridge the gap between volatile working memory and slower storage, positioning it as a potential storage-class memory alternative to DRAM in systems demanding both speed and endurance. Compared to magnetoresistive random-access memory (MRAM), PCM demonstrates higher density potential, enabling larger-scale arrays through phase-change materials that support multilevel storage, while MRAM relies on magnetic tunnel junctions with more limited bit densities. However, MRAM exhibits superior endurance, often exceeding 10^15 cycles due to non-destructive magnetic switching, versus PCM's typical 10^8 to 10^12 cycles limited by material fatigue from repeated thermal cycling. The core distinction lies in their switching mechanisms: PCM uses thermal-induced phase transitions between amorphous and crystalline states in chalcogenide alloys, whereas MRAM employs spin-transfer torque or magnetic fields for state changes, resulting in lower power for writes in MRAM but potentially higher scalability for PCM in dense 3D structures. Resistive random-access memory (ReRAM) and PCM share filamentary conduction aspects in some designs, but PCM leverages bulk phase changes across the entire cell volume for more uniform switching, avoiding the variability inherent in ReRAM's localized filament formation via oxygen vacancies or metal ions. PCM shows stronger scalability below 10 nm, with demonstrated integration at 14 nm nodes and projections for continued density gains through confined cell structures, while ReRAM, though also viable sub-10 nm, faces challenges in uniformity and selector integration for high-density arrays. Endurance in ReRAM can reach 10^12 cycles in optimized oxide-based cells, comparable to advanced PCM, but PCM's thermal mechanism allows for faster reset operations in some configurations, though at higher energy costs than ReRAM's voltage-driven switching. In contrast to ferroelectric random-access memory (FeRAM), PCM provides unlimited non-destructive read cycles, eliminating the need for post-read restoration that FeRAM requires due to its destructive readout of ferroelectric polarization states, which can degrade endurance over time. PCM also achieves higher densities, scaling to gigabit arrays via 3D stacking, while FeRAM remains constrained to megabit scales owing to ferroelectric material thickness and capacitor integration limits. Both offer nanosecond-range speeds—PCM writes at 20-400 ns and FeRAM at 2-50 ns—but PCM's phase-change approach supports better multilevel cell operation for enhanced storage efficiency compared to FeRAM's binary polarization states. Hybrid integrations highlight PCM's role in technologies like 3D XPoint, where it combines with selectors for byte-addressable storage-class memory, outperforming pure logic-embedded alternatives such as MRAM or ReRAM in density for main memory extensions, though MRAM excels in low-power embedded applications and ReRAM in neuromorphic circuits. These synergies underscore PCM's versatility in mixed hierarchies, leveraging its non-volatility and speed to complement other non-volatile types without fully replacing them.

Applications

Storage-Class Memory

Storage-class memory (SCM) represents a class of byte-addressable, non-volatile memory technologies that bridge the gap between volatile dynamic random-access memory (DRAM) and slower block-addressable storage devices like NAND flash in computing hierarchies. Phase-change memory (PCM) serves as a key enabler for SCM by storing data in a persistent manner using reversible phase transitions in chalcogenide materials, allowing systems to cache frequently accessed ("hot") data closer to the processor. This reduces dependence on DRAM's limited capacity and high cost while preserving data across power cycles, thus optimizing performance for data-intensive workloads. A flagship commercial implementation of PCM-based SCM is Intel's Optane DC Persistent Memory, launched in 2019 and discontinued in 2022. These dual in-line memory modules (DIMMs) utilized 3D XPoint technology, a form of PCM, to provide capacities up to 512 GB per module, with server systems scaling to totals of 6 TB or more when combined with DRAM. Operating in either Memory Mode—for transparent capacity extension—or App Direct Mode—for direct byte-addressable access—Optane enabled persistent data storage without requiring significant software modifications. PCM SCM delivers read latencies of approximately 300 ns and bandwidths exceeding 100 GB/s, positioning it as a high-performance alternative to traditional storage for extending memory footprints. These characteristics support larger-scale in-memory databases, where datasets previously constrained by DRAM limits can persist affordably, enhancing query speeds and system efficiency in memory-bound applications. In server deployments for big data analytics, PCM has proven effective in mitigating I/O bottlenecks; for instance, optimized database structures on PCM reduced data access times by up to 10 times compared to disk-based systems, allowing faster processing of analytical queries on terabyte-scale datasets. Such case studies highlight PCM's role in accelerating hash joins and index operations in memory-resident environments, directly benefiting analytics platforms like in-memory OLAP systems. Following Optane's phase-out, ongoing research explores PCM integrations in disaggregated memory architectures for cloud computing, where memory pools are decoupled from compute nodes to enable elastic resource allocation. Efforts focus on standards like to facilitate remote PCM access with minimal latency overhead, supporting scalable persistent storage for distributed databases and microservices.

In-Memory Computing

Phase-change memory (PCM) enables analog in-memory computing by leveraging the tunable resistance states of phase-change materials to perform multiply-accumulate (MAC) operations directly within memory arrays, mitigating the von Neumann bottleneck associated with data movement between memory and processing units in artificial intelligence workloads. In this paradigm, the conductance of PCM cells represents synaptic weights, allowing matrix-vector multiplications to be executed via Ohm's law and Kirchhoff's current law in a massively parallel manner without frequent data transfers. Key implementations utilize crossbar arrays of PCM devices to accelerate matrix-vector multiplication, a core operation in neural networks. For instance, prototypes in the 2020s have demonstrated energy efficiencies reaching up to 10^{12} operations per second per watt (OPS/W) for deep neural network inference, surpassing traditional digital accelerators by performing computations in the analog domain at the point of data storage. These arrays map weights to cell conductances, with input vectors applied as voltage pulses, yielding summed currents proportional to the MAC results, thus enabling high-throughput AI processing with reduced latency. Notable examples include IBM's development of PCM-based chips inspired by the TrueNorth neuromorphic architecture, where phase states store weights for efficient synaptic operations in spiking neural networks. Complementary research has advanced multilevel PCM states to support 8-bit precision, as demonstrated with projected phase-change memory devices that maintain accurate scalar multiplications across 256 conductance levels, facilitating precise inference in convolutional neural networks without significant accuracy degradation. By 2025, advancements have integrated PCM into hybrid optical computing systems, where phase-change materials modulate light transmission for all-optical convolutional neural networks, achieving picosecond-scale operations for edge AI applications. Additionally, PCM serves as neuromorphic synapses by storing weights in amorphous and crystalline phases, enabling rapid learning in hardware with phase-change devices that adapt to new tasks through in-memory updates, as shown in prototypes pairing local learning rules with PCM arrays. These approaches yield substantial efficiency gains, with PCM in-memory computing demonstrating up to 100× energy savings over GPU-based inference for neural network tasks compared to traditional digital logic, primarily due to eliminated data shuttling and low-power analog operations.

Challenges

Technical Hurdles

One major technical hurdle in phase-change memory (PCM) is the limited endurance, typically ranging from 10^9 to 10^12 write/erase cycles for Ge₂Sb₂Te₅ (GST)-based devices, primarily due to element segregation and electromigration during repeated thermal cycling that leads to material degradation and device failure. Doping GST with elements such as carbon or nitrogen suppresses this segregation by stabilizing the phase-change material's structure, thereby extending endurance beyond 10¹¹ cycles in optimized cells. Thermal crosstalk presents another significant challenge, where heat generated during the high-temperature reset operation (>500°C) in one cell diffuses through the substrate or electrodes in dense arrays, causing unintended phase transitions and errors in adjacent cells. This effect becomes more pronounced at high densities, potentially reducing array reliability by inducing partial crystallization in neighboring amorphous states. Mitigation strategies include the use of confined cell architectures, such as pore or dash-type structures, which localize the active phase-change volume and minimize heat propagation to surrounding areas. Data retention in the amorphous state is limited by structural relaxation and resistance drift, where the metastable amorphous phase slowly evolves over time, leading to shifts that compromise readability; standard GST materials achieve retention for at least 10 years at 85°C, supported by activation energies of approximately 2.5-3 eV that create barriers to spontaneous . Enhanced retention can be obtained through doping, which raises activation energies to over 4 eV, reducing drift rates and stabilizing the amorphous configuration for extended periods under operating conditions. Write latency variability arises from the stochastic nature of during the (SET) process, resulting in cycle-to-cycle differences in switching time and resistance distribution, often on the order of 10-20% due to random nucleus formation sites and growth kinetics in the small active volumes. This inherent randomness complicates precise control in high-speed operations and contributes to overall device non-uniformity, though it can be partially addressed by optimizing pulse shapes to promote more deterministic growth. Scalability below 10 nm encounters severe challenges, including increased resistance variability from statistical fluctuations in the nanoscale phase-change volume and elevated reset currents required to achieve sufficient melt-quench temperatures, which strain power efficiency and integration with processes. As cell dimensions shrink, the higher current densities exacerbate and thermal management issues, limiting reliable operation without advanced material engineering or novel designs.

Economic and Manufacturing Issues

Phase-change memory (PCM) fabrication involves exotic materials like germanium-antimony-tellurium (GST) alloys, which require specialized back-end-of-line (BEOL) processes for integration with complementary metal-oxide-semiconductor (CMOS) circuitry. These processes, including high-temperature annealing up to 400°C for material crystallization, increase complexity and thermal budgets compared to traditional flash memory production. As a result, PCM manufacturing costs are significantly higher than those for NAND flash, with estimates suggesting costs on the order of tens of times more per Gb, primarily due to the need for precise control over phase-change material deposition and the larger cell selectors required to handle higher programming currents. GST deposition typically occurs via (PVD) techniques such as , which ensures an amorphous starting phase but introduces challenges like alloy composition variability from . This process, often combined with co-sputtering for doping (e.g., or carbon at 1-4% levels), adds to the cost premium, as it demands advanced equipment and multiple deposition steps not routine in flash fabrication. While BEOL compatibility allows PCM to be integrated above existing interconnect layers (e.g., using metal layers 5+ for phase-change elements), the overall process yield suffers from these sensitivities, limiting scalability. Yield challenges in PCM production are particularly pronounced in 3D crosspoint arrays, where defects arise due to variability in aperture sizes, resistance distributions, and process-induced damage to the GST layer. Alignment issues in crosspoint structures further exacerbate this, as sub-lithographic patterning (e.g., via spacer or keyhole processes) is needed to achieve densities approaching 4F² per cell, but misalignment during conformal filling of high-aspect-ratio vias reduces functional cell rates. These defects, often stemming from etching alterations to the chalcogenide composition, necessitate error-correcting codes and write-verify schemes, further impacting throughput and economic viability. Commercialization efforts, exemplified by Intel's Optane (based on 3D XPoint PCM technology), faced significant market adoption barriers, culminating in its discontinuation in 2022 after achieving less than 1% penetration in the overall standalone memory market and minimal uptake in servers due to specialized architecture requirements. Competition from cheaper, higher-capacity NAND flash SSDs, whose prices have plummeted while performance improves (e.g., exceeding 10 GB/s reads), rendered Optane uncompetitive, leading to a $559 million inventory impairment for . Emerging non-volatile memories like PCM thus struggle against NAND's dominance, with Optane's exit highlighting the difficulty in displacing established storage hierarchies. The PCM supply chain is heavily dependent on rare elements like (Te), a key component in GST alloys, which is primarily recovered as a of and exhibits supply volatility due to low recovery rates (often below 50%) and geopolitical concentrations in production. This reliance poses risks of price fluctuations and shortages, complicating large-scale manufacturing; for instance, Te's scarcity has historically limited chalcogenide-based applications. Projections for 2025 indicate that PCM costs will remain 30-40% higher than DRAM per bit, with cost parity achievable only in specialized niches like AI hardware for neuromorphic computing, where energy efficiency gains (e.g., 50-75% over DRAM) justify the premium amid maturing processes. As of 2025, the PCM market is projected to grow at a CAGR of 27.2% through 2034, driven by AI and embedded applications, though economic challenges like higher costs and yields continue to limit broad adoption. The (IP) landscape for PCM is fragmented and licensing-intensive, with foundational s originating from Ovonyx (a of Energy Conversion Devices), which has granted long-term licenses to major players including (2005), Hynix (2007), Numonyx (2008), and (2007). Micron's 2015 acquisition of Ovonyx assets consolidated much of this IP, but ongoing litigation (e.g., suits over ) and pre-existing cross-licenses have complicated new partnerships, raising barriers for entrants seeking to commercialize without infringement risks or royalty burdens. This IP entanglement contributes to delayed adoption, as companies must navigate multiple agreements to access core phase-change processes.

Timeline

Pre-2000 Events

In January 1955, B. T. Kolomiets and N. A. Gorunova reported the semiconducting properties of chalcogenide glasses at the in the , laying foundational groundwork for materials used in phase-change devices. In September 1966, filed the first for the Ovonic switch, describing a threshold switching device based on chalcogenide materials that enabled rapid transitions between high- and low-resistance states. In November 1968, U.S. Patent 3,271,591 was granted to Ovshinsky for switching in disordered structures, detailing the use of phase-change effects in amorphous chalcogenides for applications. In 1970, Energy Conversion Devices (ECD) demonstrated the first Ovonic device, a 256-bit read-mostly array using ovonic switches integrated in a 16×16 configuration, as described in a collaborative publication with researchers. In 1976, and Signetics licensed Ovshinsky's technology from ECD to develop prototype chips based on phase-change memory principles, marking an early industry push toward commercialization. In 1987, initiated early research on optical phase-change materials for rewritable storage, leading to the development of technology that utilized chalcogenide alloys for data recording via laser-induced phase transitions. During the 1990s, Hewlett-Packard (HP) and other research groups developed electrical phase-change memory prototypes, including array demonstrations with improved scalability and endurance, advancing the technology toward practical non-volatile RAM applications.

2000-2020 Events

2000
Ovonyx was formed as a joint venture between Energy Conversion Devices (ECD) and Intel to commercialize phase-change memory technology, marking a key step in transitioning from research to industry development. 2003
initiated development of phase-change (PRAM) , laying the groundwork for subsequent prototypes. 2005
developed a 1 Mb embedded PRAM device, focused on radiation-hardened applications for and defense. 2007
demonstrated a fully integrated 512 Mb PRAM using 90 nm , achieving a cell size of 0.047 μm² and highlighting scalability for mobile applications.
In the same year, announced plans for sampling a 128 Mb phase-change chip on 90 nm process, aimed at evaluating performance in embedded and cellular systems. 2010
Samsung shipped its first commercial 512 Mb PRAM in a multi-chip package for mobile handsets, building on earlier prototypes with improved integration. 2012
demonstrated a 28 nm 16 Mb phase-change array, advancing embedded for automotive and industrial uses. 2015
Intel and Micron announced technology, a phase-change-based offering up to 1,000 times faster performance than NAND flash while maintaining high endurance. 2017
released the first Optane SSDs utilizing , including the DC P4800X series for data centers, providing low-latency storage with PCIe connectivity. 2019
Intel launched Optane Persistent Memory modules (DCPMM), enabling byte-addressable capacities up to 512 GB per socket for servers, bridging DRAM and storage hierarchies. 2020
Early demonstrations of phase-change memory for in-memory computing emerged, showcasing analog computing capabilities with PCM arrays for efficient .

2021-Present Events

In 2021, researchers demonstrated improved phase-change performance using GeTe/Sb₂Te₃ s, which enabled lower RESET currents and faster switching speeds compared to conventional Ge₂Sb₂Te₅-based devices. This work highlighted GeTe's potential for high-speed applications by integrating thin stacks into functional cells. In 2022, Intel announced the winding down of its Optane memory business, which relied on technology incorporating phase-change materials, citing economic challenges and shifting market priorities. The decision marked the end of active development for this line, though existing products remained available for a transition period. Research in 2023 advanced low-power phase-change switching with In₂Se₃ materials, as shown in studies demonstrating reversible thermally driven phase transitions in layered structures, enabling energy-efficient multi-level storage. Additional work explored proton-mediated metastable ferroelectric phases in α-In₂Se₃ transistors, achieving reversible switching with reduced power consumption suitable for next-generation devices. In 2024, issued notifications confirming the discontinuation of Optane 200-series modules, with final shipments scheduled through December 31, 2025, effectively closing out production of this phase-change-based technology. The global phase-change memory market reached a valuation of $669 million that year, driven by emerging applications in and . By 2025, a article reported extended switching endurance exceeding 1.1 × 10¹¹ cycles in phase-change memory devices using nano-confined carbon-doped Ge₂Sb₂Te₅ structures, addressing key reliability limitations for storage-class memory. Rumors surfaced regarding SanDisk's development of 3D Matrix Memory as a potential phase-change-based , speculated to offer disruptive non-volatile storage capabilities, though the company did not confirm details. Market projections indicated the phase-change memory sector could reach $2.5 billion by 2034, fueled by growth in automotive and enterprise sectors at a compound annual rate of approximately 25%.

References

  1. https://www.sciencedirect.com/topics/materials-science/phase-change-memory
  2. https://www.sciencedirect.com/science/article/pii/S2590049825000165
  3. https://www.eenewseurope.com/en/st-microcontrollers-go-to-18nm-fdsoi-with-phase-change-memory/
  4. https://www.nature.com/articles/s41586-024-07230-5
  5. https://www.nature.com/articles/s41578-018-0076-x
  6. https://www.nature.com/articles/srep13698
  7. https://www.sciencedirect.com/topics/engineering/phase-change-memory
  8. https://www.nature.com/articles/s41598-019-55874-5
  9. https://pubs.acs.org/doi/10.1021/acs.jpcc.6b11707
  10. https://advanced.onlinelibrary.wiley.com/doi/full/10.1002/adma.201900784
  11. https://www.nature.com/articles/s41524-024-01217-6
  12. https://pubs.aip.org/aip/jap/article/112/7/071101/369564/Electrical-conduction-in-chalcogenide-glasses-of
  13. https://re.public.polimi.it/retrieve/handle/11311/1049034/271586/chapter3_v3.pdf
  14. https://link.aps.org/doi/10.1103/PhysRevB.86.045212
  15. https://www.nature.com/articles/s41598-017-02710-3
  16. https://link.aps.org/doi/10.1103/PhysRevLett.98.236403
  17. https://www.sciencedirect.com/science/article/pii/S1369702108701184
  18. https://www.sciencedirect.com/topics/materials-science/chalcogenides-glass
  19. https://onlinelibrary.wiley.com/doi/full/10.1002/pssb.202000138
  20. https://pmc.ncbi.nlm.nih.gov/articles/PMC10784450/
  21. https://onlinelibrary.wiley.com/doi/full/10.1002/pssb.201200420
  22. https://opticaorgdev.blob.core.windows.net/%24web/optica/media/osa.history/century_of_optics/1960-1974/138.pdf
  23. https://patents.google.com/patent/US3271591A/en
  24. https://doi.org/10.1103/PhysRevLett.21.1450
  25. https://physicstoday.aip.org/features/the-discovery-of-ovshinsky-switching-and-phase-change-memory
  26. https://findingaids.lib.umich.edu/catalog/umich-bhl-2014092
  27. https://doi.org/10.1063/PT.3.3948
  28. https://www.edn.com/ovonyx-intel-to-pursue-amorphorous-chip-technology-for-flash-logic-devices/
  29. https://www.sec.gov/Archives/edgar/data/32878/000003287800000017/0000032878-00-000017-0001.txt
  30. https://files.futurememorystorage.com/proceedings/2011/20110811_S306_Atwood.pdf
  31. https://www.researchgate.net/publication/224697642_Full_Integration_of_Highly_Manufacturable_512Mb_PRAM_based_on_90nm_Technology
  32. https://nccavs-usergroups.avs.org/wp-content/uploads/TFUG2009/2009_10dennison.pdf
  33. https://patents.google.com/patent/US8759810B2/en
  34. https://www.researchgate.net/publication/224184466_A_4_Mb_LV_MOS-selected_embedded_phase_change_memory_in_90_nm_standard_CMOS_technology
  35. https://www.intc.com/news-events/press-releases/detail/324/intel-and-micron-produce-breakthrough-memory-technology
  36. https://research.ibm.com/publications/a-512mb-phase-change-memory-pcm-in-90nm-cmos-achieving-2bcell
  37. https://www.nature.com/articles/s41467-017-01481-9
  38. https://blog.purestorage.com/perspectives/in-remembrance-of-optane/
  39. https://par.nsf.gov/servlets/purl/10473514
  40. https://www.matec-conferences.org/articles/matecconf/pdf/2024/16/matecconf_menec2024_03008.pdf
  41. https://www.researchgate.net/publication/361628725_Multilayered_Sb-Rich_GeSbTe_Phase-Change_Memory_for_Best_Endurance_and_Reduced_Variability
  42. https://pubmed.ncbi.nlm.nih.gov/36178431/
  43. https://www.nature.com/articles/s41467-025-60644-1
  44. https://www.eenewseurope.com/en/does-phase-change-memory-ride-again-with-sandisk/
  45. https://www.datainsightsconsultancy.com/reports/phase-change-memory-materials-market/
  46. https://arxiv.org/html/2412.07447v1
  47. https://iopscience.iop.org/article/10.1088/1361-6463/ab7794
  48. https://ar5iv.labs.arxiv.org/html/1001.1164
  49. https://www.cambridge.org/core/journals/mrs-bulletin/article/phasechange-memory-cycling-endurance/4B7019F184081B441D27701A432A42CD
  50. https://pubs.aip.org/aip/apl/article/91/7/073505/131178/Phase-change-memory-cell-with-an-upper-amorphous
  51. https://pubs.acs.org/doi/10.1021/acs.chemrev.4c00670
  52. https://ieeexplore.ieee.org/document/9174799
  53. https://www.techtarget.com/searchstorage/definition/3D-XPoint
  54. https://ieeexplore.ieee.org/document/10529438
  55. https://www.researchgate.net/publication/363071654_BEOL_Process_Effects_on_ePCM_Reliability
  56. https://www.researchgate.net/publication/228375378_Phase_Change_Memory
  57. https://stacks.stanford.edu/file/druid:vh328kj9007/Rakesh_Jeyasingh_2014_Final_Thesis-augmented.pdf
  58. https://ieeexplore.ieee.org/document/8048346
  59. https://www.techinsights.com/blog/intel-3d-xpoint-memory-die-removed-intel-optanetm-pcm-phase-change-memory
  60. https://www.wpi-aimr.tohoku.ac.jp/en/aimresearch/highlight/2024/20241125_001869.html
  61. https://semiengineering.com/embedded-phase-change-memory-emerges/
  62. https://cmosedu.com/jbaker/papers/2009/integration_of_IC.pdf
  63. https://digitalcommons.lib.uconn.edu/context/dissertations/article/6804/viewcontent/the_thesis_final.pdf
  64. https://www.science.org/doi/10.1126/science.abj1261
  65. https://poplab.stanford.edu/pdfs/Khan-TEPCM-edl20.pdf
  66. https://irds.ieee.org/images/files/pdf/2021/2021IRDS_BC.pdf
  67. https://www.st.com/content/st_com/en/about/innovation---technology/PCM.html
  68. https://pmc.ncbi.nlm.nih.gov/articles/PMC4182445/
  69. https://link.springer.com/article/10.1557/s43579-024-00660-2
  70. https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/phase-change-memory/
  71. https://theses.hal.science/tel-04052655/file/LAMA_2022_archivage.pdf
  72. https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/optane-dc-persistent-memory-brief.pdf
  73. https://lenovopress.lenovo.com/lp1066-intel-optane-persistent-memory-100-series
  74. https://pages.cs.wisc.edu/~swift/papers/nvmw_muses.pdf
  75. https://www.cidrdb.org/cidr2011/Papers/CIDR11_Paper3.pdf
  76. https://imec-publications.be/bitstreams/0a9e5dc9-b77a-43b2-b874-0ae7e6db8bd9/download
  77. https://www3.cs.stonybrook.edu/~anshul/dimes23-pmem.pdf
  78. https://dl.acm.org/doi/10.1145/3582016.3582055
  79. https://www.vldb.org/pvldb/vol15/p4023-lee.pdf
  80. https://www.nature.com/articles/s41467-024-51221-z
  81. https://www.nature.com/articles/s41928-023-01064-1
  82. https://arxiv.org/pdf/2105.13904
  83. https://research.ibm.com/blog/what-is-neuromorphic-or-brain-inspired-computing
  84. https://ieeexplore.ieee.org/document/8614558
  85. https://www.nature.com/articles/s41598-025-06259-4
  86. https://www.nature.com/articles/s41467-025-56345-4
  87. https://www.nature.com/articles/s43588-025-00854-1
  88. https://pubs.aip.org/aip/adv/article/12/6/065018/2818873/Segregation-induced-Ge-precipitation-in-Ge2Sb2Te5
  89. https://onlinelibrary.wiley.com/doi/full/10.1002/pssb.202400646
  90. https://www.sciencedirect.com/science/article/pii/S0022309325004685?dgcid=rss_sd_all
  91. https://iopscience.iop.org/article/10.1088/1742-6596/2624/1/012020/pdf
  92. https://digitalcommons.lib.uconn.edu/cgi/viewcontent.cgi?article=1068&context=srhonors_holster
  93. https://www.sciencedirect.com/science/article/pii/S1369800121004364
  94. https://www.researchgate.net/publication/367061358_Analysis_of_Intrinsic_Variability_in_Phase-Change_Memory_Switching_Originating_from_Stochastic_Nucleation_Using_Fully_Coupled_Electrothermal_and_Phase-Field_Models
  95. https://www.researchgate.net/publication/254062242_Reset_Current_Scaling_in_PhaseChange_Memory_Cells_Modeling_and_Experiments
  96. http://www-9.unipv.it/dottMICR/theses/Kiouseloglou.pdf
  97. https://eureka.patsnap.com/report-projected-roadmap-for-pcm-commercialization-in-ai-hardware
  98. https://www.eetimes.com/what-legacy-will-money-losing-optane-have/
  99. https://www.theregister.com/2022/07/29/intel_optane_memory_dead/
  100. http://markets.chroniclejournal.com/chroniclejournal/article/marketminute-2025-10-1-the-heat-is-on-tellurium-powered-thermoelectrics-ignite-a-new-era-in-energy-efficiency
  101. https://www.gminsights.com/industry-analysis/phase-change-memory-pcm-market
  102. https://www.mram-info.com/ovonyx-and-samsung-sign-technology-licensing-agreement-phase-change-memory
  103. https://news.skhynix.com/ovonyx-and-hynix-sign-technology-and-licensing-agreement-for-phase-change-memory/
  104. https://investors.micron.com/news-releases/news-release-details/numonyx-and-ovonyx-sign-technology-licensing-agreement-phase
  105. https://www.design-reuse.com/news/202512731-ovonyx-and-qimonda-sign-technology-licensing-agreement-for-phase-change-memory/
  106. https://blocksandfiles.com/2020/10/05/3d-xpoint-patent-suit-intel-micron/
  107. https://www.sciencedirect.com/science/article/pii/0040609076901140
  108. https://www.strategy-business.com/article/11111
  109. https://computerhistory.org/blog/pioneers-of-semiconductor-non-volatile-memory-nvm-the-first-four-decades/
  110. https://www.worldradiohistory.com/Archive-Electronics/70s/78/Electronics-1978-06-08.pdf
  111. https://www.eetimes.com/the-evolution-of-phase-change-memory/
  112. https://www.edn.com/intel-to-sample-phase-change-memory-in-1h-2007/
  113. https://www.eetimes.com/phase-change-memory-found-in-handset/
  114. https://www.st.com/content/dam/AME/2019/developers-conference-2019/presentations/STDevCon19_7.7_Auto-Domain-MCU.pdf
  115. https://arstechnica.com/information-technology/2017/03/intels-first-optane-ssd-375gb-that-you-can-also-use-as-ram/
  116. https://ieeexplore.ieee.org/document/8964852
  117. https://onlinelibrary.wiley.com/doi/full/10.1002/pssr.202000538
  118. https://www.forbes.com/sites/tomcoughlin/2022/07/28/intel-winding-down-its-optane-memory-business/
  119. https://pubs.acs.org/doi/abs/10.1021/acs.nanolett.3c01247
  120. https://www.science.org/doi/10.1126/sciadv.adg4561
  121. https://www.tomshardware.com/pc-components/ssds/intel-schedules-the-end-of-its-200-series-optane-memory-dimms-shipments-to-draw-to-an-end-in-late-2025
  122. https://finance.yahoo.com/news/global-phase-change-memory-market-151100859.html
  123. https://www.accio.com/business/trending-pcm-flash-new-model
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