Hubbry Logo
Bonnell (microarchitecture)Bonnell (microarchitecture)Main
Open search
Bonnell (microarchitecture)
Community hub
Bonnell (microarchitecture)
logo
7 pages, 0 posts
0 subscribers
Be the first to start a discussion here.
Be the first to start a discussion here.
Bonnell (microarchitecture)
Bonnell (microarchitecture)
Bonnell (microarchitecture)
View on Wikipedia
from Wikipedia
Bonnell
General information
Launched2008
Discontinued2013
Common manufacturer
  • Intel
Performance
Max. CPU clock rate600 MHz to 2.13 GHz
FSB speeds400 MHz to 667 MHz
Architecture and classification
Technology node45 nm to 32 nm
Instruction setx86-16, IA-32,
x86-64 (some)
InstructionsMMX
Extensions
Physical specifications
Cores
  • 1, 2
Package
Products, models, variants
Core names
  • Silverthorne
  • Diamondville
  • Pineview
  • Tunnel Creek
  • Lincroft
  • Stellarton
  • Sodaville
  • Cedarview
History
SuccessorSilvermont

Bonnell is a CPU microarchitecture used by Intel Atom processors which can execute up to two instructions per cycle.[1][2] Like many other x86 microprocessors, it translates x86 instructions (CISC instructions) into simpler internal operations (sometimes referred to as micro-ops, effectively RISC style instructions) prior to execution. The majority of instructions produce one micro-op when translated, with around 4% of instructions used in typical programs producing multiple micro-ops. The number of instructions that produce more than one micro-op is significantly fewer than the P6 and NetBurst microarchitectures. In the Bonnell microarchitecture, internal micro-ops can contain both a memory load and a memory store in connection with an ALU operation, thus being more similar to the x86 level and more powerful than the micro-ops used in previous designs.[3] This enables relatively good performance with only two integer ALUs, and without any instruction reordering, speculative execution or register renaming. A side effect of having no speculative execution is invulnerability against Meltdown and Spectre.

The Bonnell microarchitecture therefore represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio. However, hyper-threading is implemented in an easy (i.e. low-power) way to employ the whole pipeline efficiently by avoiding the typical single thread dependencies.[3]

First generation cores

[edit]

Silverthorne microprocessor

[edit]

On 2 March 2008, Intel announced a new single-core Atom Z5xx series processor (code-named Silverthorne), to be used in ultra-mobile PCs and mobile Internet devices (MIDs), which will supersede Stealey (A100 and A110). The processor has 47 million transistors on a 25 mm2 die, allowing for extremely economical production at that time (~2500 chips on a single 300 mm diameter wafer).

An Atom Z500 processor's dual-thread performance is equivalent to its predecessor Stealey, but should outperform it on applications that can use simultaneous multithreading and SSE3.[4] They run from 0.8 to 2.0 GHz and have a TDP rating between 0.65 and 2.4 W that can dip down to 0.01 W when idle.[5] They feature 32 KB instruction L1 and 24 KB data L1 caches, 512 KB L2 cache and a 533 MT/s front-side bus. The processors are manufactured in 45 nm process.[6][7] Poulsbo was used as System Controller Hub and the platform was called Menlow.

Diamondville microprocessor

[edit]

The Intel Atom N270

On 2 March 2008, Intel announced lower-power variants of the Diamondville CPU named Atom N2xx. It was intended for use in nettops and the Classmate PC.[8][9][10] Like their predecessors, these are single-core CPUs with Hyper-Threading.

The N270 has a TDP rating of 2.5 W, runs at 1.6 GHz and has a 533 MHz FSB.[11] The N280 has a clock speed of 1.66 GHz and a 667 MHz FSB.[12]

On 22 September 2008, Intel announced a new 64-bit dual-core processor (unofficially code-named Dual Diamondville) branded Atom 330, to be used in desktop computers. It runs at 1.6 GHz and has an FSB speed of 533 MHz and a TDP rating of 8 W. Its dual core consists of two Diamondville dies on a single substrate.[13]

During 2009, Nvidia used the Atom 300 and their GeForce 9400M chipset on a mini-ITX form factor motherboard for their Ion platform.

First generation power requirements

[edit]
The relatively low power Atom CPU was originally used with a cheaper, not so electricity-efficient chipset such as the Intel 945G.

Although the Atom processor itself is relatively low-power for an x86 microprocessor, many chipsets commonly used with it dissipate significantly more power. For example, while the Atom N270 commonly used in netbooks through mid-2010 has a TDP rating of 2.5 W, an Intel Atom platform that uses the 945GSE Express chipset has a specified maximum TDP of 11.8 W, with the processor responsible for a relatively small portion of the total power dissipated. Individual figures are 2.5 W for the N270 processor, 6 W for the 945GSE chipset and 3.3 W for the 82801GBM I/O controller.[11][14][15][16] Intel also provides a US15W System Controller Hub-based chipset with a combined TDP of less than 5 W together with the Atom Z5xx (Silverthorne) series processors, to be used in ultra-mobile PCs and MIDs,[17] though some manufacturers have released ultra-thin systems running these processors (e.g. Sony VAIO X).

Initially, all Atom motherboards on the consumer market featured the Intel 945GC chipset, which uses 22 watts by itself. As of early 2009, only a few manufacturers are offering lower-power motherboards with a 945GSE or US15W chipset and an Atom N270, N280 or Z5xx series CPU.

Second generation cores

[edit]

Pineview microprocessor

[edit]

New Intel Atom N450 SLBMG 1.66GHz 512KB L2 BGA559

On 21 December 2009, Intel announced the N450, D510 and D410 CPUs with integrated graphics.[18] The new manufacturing process resulted in a 20% reduction in power consumption and a 60% smaller die size.[19][20] The Intel GMA 3150, a 45 nm shrink of the GMA 3100 with no HD capabilities, is included as the on-die GPU. Netbooks using this new processor were released on 11 January 2010.[19][21] The major new feature is longer battery life (10 or more hours for 6-cell systems).[22][23]

This generation of the Atom was codenamed Pineview, which is used in the Pine Trail platform. Intel's Pine Trail-M platform utilizes an Atom processor (codenamed Pineview-M) and Platform Controller Hub (codenamed Tiger Point). The graphics and memory controller have moved into the processor, which is paired with the Tiger Point PCH. This creates a more power-efficient 2-chip platform rather than the 3-chip one used with previous-generation Atom chipsets.[24]

On 1 March 2010, Intel introduced the N470 processor,[25] running at 1.83 GHz with a 667 MHz FSB and a TDP rating of 6.5 W.[26]

The new Atom N4xx chips became available on 11 January 2010.[27] It is used in netbook and nettop systems and includes an integrated single-channel DDR2 memory controller and an integrated graphics core. It also features Hyper-Threading and is manufactured on a 45 nm process.[28] The new design uses half the power of the older Menlow platform. This reduced overall power consumption and size makes the platform more desirable for use in smartphones and other mobile internet devices.

The D4xx and D5xx series support the x86-64 bit instruction set and DDR2-800 memory. They are rated for embedded use. The series has an integrated graphics processor built directly into the CPU to help improve performance. The models are targeted at nettops and low-end desktops. They do not support SpeedStep.

The Atom D510 dual-core processor runs at 1.66 GHz, with 1 MB of L2 cache and a TDP rating of 13 W.[29] The single-core Atom D410 runs at 1.66 GHz, with 512 KB of L2 cache and a TDP rating of 10 W.[30]

Tunnel Creek microprocessor

[edit]

Tunnel Creek is an embedded Atom processor used in the Queens Bay platform with the Topcliff PCH.

Lincroft microprocessor

[edit]

The Lincroft (Z6xx) with the Whitney Point PCH is included in the Oak Trail tablet platform. Oak Trail is an Intel Atom platform based on Moorestown. Both platforms include a Lincroft microprocessor, but use two distinct input/output Platform Controller Hubs (I/O-PCH), codenamed Langwell and Whitney Point respectively. Oak Trail was presented on 11 April 2011 and was to be released in May 2011.[needs update][31] The Z670 processor, part of the Oak Trail platform, delivers improved video playback, faster Internet browsing and longer battery life, "without sacrificing performance" according to Intel. Oak Trail includes support for 1080p video decoding as well as HDMI. The platform also has improved power efficiency and allows applications to run on various operating systems, including Android, MeeGo and Windows.

Stellarton microprocessor

[edit]

Stellarton is a Tunnel Creek CPU with an Altera Field Programmable Gate Array (FPGA).

Sodaville SoC

[edit]

See also: Intel Consumer Electronics

Sodaville is a consumer electronics Atom SoC.

Groveland SoC

[edit]

See also: Intel Consumer Electronics

Groveland is a consumer electronics Atom SoC.

Third generation cores

[edit]

The 32 nm shrink of Bonnell is called Saltwell.

Cedarview microprocessor

[edit]

Intel released their third-generation Cedar Trail platform (consisting of a range of Cedarview processors[32] and the NM10 southbridge chip) based on 32 nm process technology in the fourth quarter of 2011.[31] Intel stated that improvements in graphics capabilities, including support for 1080p video, additional display options including HDMI and DisplayPort, and enhancements in power consumption are to enable fanless designs with longer battery life.

The Cedar Trail platform includes two new CPUs, 32 nm-based N2800 (1.86 GHz) and N2600 (1.6 GHz), which replace the previous generation Pineview N4xx and N5xx processors. The CPUs also feature an integrated GPU that supports DirectX 9.

In addition to the netbook platform, two new Cedarview CPUs for nettops, D2500 and D2700, were released on 25 September 2011.[33]

In early March 2012, the N2800-based Intel DN2800MT motherboard[34] started to become available. Due to the use of a netbook processor, this Mini-ITX motherboard can reach idle power consumption as low as 7.1 W.[35]

Penwell SoC

[edit]

Penwell is an Atom SoC that is part of the Medfield MID/Smartphone platform.

Berryville SoC

[edit]

See also: Intel Consumer Electronics

Berryville is a consumer electronics Atom SoC.

Cloverview SoC

[edit]

Cloverview is an Atom SoC that is part of the Clover Trail tablet platform.

Centerton SoC

[edit]

In December 2012, Intel launched the 64-bit Centerton family of Atom CPUs, designed specifically for use in Bordenville platform servers.[36] Based on the 32 nm Saltwell architecture, Centerton adds features previously unavailable in most Atom processors, such as Intel VT virtualization technology, and support for ECC memory.[37]

Briarwood SoC

[edit]

Briarwood is an Atom SoC that is designed for a server platform.

Roadmap

[edit]

See also

[edit]

References

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Bonnell (microarchitecture)

View on Grokipedia
from Grokipedia
Bonnell is a CPU developed by for ultra-low-power x86 processors, specifically the initial Atom family, featuring an in-order dual-issue capable of executing up to two instructions per cycle while targeting sub-2 W power consumption on a 45 nm high-k metal gate CMOS process. Introduced in early , it was designed to deliver acceptable performance in mobile and embedded applications with a focus on energy efficiency, supporting and maintaining full compatibility with the x86 (ISA). Key design goals included minimizing power through techniques like a shallow 16- to 19-stage , simplified execution units with two ALUs and shared floating-point capabilities, and no dedicated hardware multiplier for integers, all while reviving elements of earlier in-order architectures like the P5 . The microarchitecture's consists of a 32 KiB 8-way set-associative instruction cache, a 24 KiB 6-way cache per core, and a unified 512 KiB (scalable to 128 KiB) 8-way L2 cache per core, optimized for low latency in power-constrained environments. Bonnell processors, such as the Atom Z5xx and N2xx series, operated at clock speeds up to 2.13 GHz with (TDP) ratings from 0.5 W to 2.5 W, achieving average active power around 220 mW and idle power below 80 mW, making them suitable for netbooks, mobile devices (MIDs), and early smartphones. Despite its efficiency, the in-order execution limited performance compared to out-of-order designs like 's Core microarchitecture, leading to a successor shrink called Saltwell on 32 nm in 2011.

Architecture

Core Pipeline

The Bonnell microarchitecture employs a straightforward in-order optimized for ultra-low power consumption in embedded and mobile applications. This comprises 16-19 stages, including 3 stages for instruction fetch, 3 for decode, 2 for dispatch, 1 for register read, 1 for address generation, 2 for data cache access, 1 for execution, 2 for and multithreading, and 1 for commit. The design avoids the complexity of deeper pipelines found in high-performance cores, enabling efficient heat distribution and reduced energy use while maintaining compatibility with the x86 instruction set. Central to the pipeline's operation is its dual-issue capability, which allows up to two x86 instructions per cycle to be decoded and translated into micro-operations (μops). These μops are then dispatched directly to execution units without reordering, reflecting Bonnell's strictly in-order execution model. The architecture eschews , , and advanced speculative mechanisms such as memory-level , prioritizing simplicity and predictability over peak throughput. This direct dispatch approach minimizes hardware overhead, contributing to the core's low and power envelope, though it limits performance in branch-heavy or dependent workloads. Branch prediction in Bonnell relies on a two-level adaptive mechanism to mitigate stalls, featuring a 12-bit global history register, a 4096-entry pattern history table (PHT), and a 128-entry target buffer (BTB) organized as 4-way set-associative with 32 sets. The predictor supports one not-taken per cycle or one taken every two cycles, with a misprediction penalty of up to 13 cycles. For branches not captured in the BTB, the defaults to simple static backward-taken/forward-not-taken , ensuring forward progress without complex recovery logic. This setup enables basic speculative fetching and execution along predicted paths, balancing minimal power draw with acceptable handling in typical low-power scenarios. Bonnell incorporates support for (simultaneous multithreading) in its core design, permitting two logical threads to share the pipeline, caches, and execution resources per physical core. This feature, enabled in multi-core configurations and select single-core variants like the Atom N270, allows each thread a maximum throughput of one instruction per cycle, enhancing utilization during latency-bound operations such as accesses. By duplicating thread-specific structures like the instruction queue and prefetch buffers while sharing the core pipeline, improves efficiency in lightly threaded workloads without significantly increasing power consumption.

Execution Resources

The Bonnell microarchitecture features a compact set of execution resources optimized for low-power operation, including two arithmetic logic units (ALUs), two floating-point () ALUs, and two generation units (AGUs). These units enable the processor to dispatch up to four micro-operations per cycle, balancing scalar and vector computations while minimizing area and energy use. The integer execution cluster includes two ALUs configured for specialized tasks to enhance efficiency in common workloads. One ALU is dedicated to handling jumps and branches, allowing rapid resolution of changes without stalling the . The other ALU focuses on shifts and general arithmetic/logical operations, such as additions, subtractions, and bitwise manipulations on 32-bit integers. This division reduces contention and supports a throughput of up to two simple integer operations per cycle. Floating-point operations are managed by two FP ALUs within a shared FP/SIMD cluster. One unit handles additions and multiplications, processing 64-bit scalar FP values with a latency of approximately 3-5 cycles and supporting one operation per cycle. The second unit addresses division and other remaining FP operations, which are non-pipelined and exhibit higher latency (up to 30-60 cycles for divisions). Notably, integer multiplication and division lack dedicated hardware and are instead routed through these FP units, introducing dependencies that can limit integer-heavy workloads. Two AGUs support load and store operations, each capable of generating 64-bit for accesses. These units facilitate micro-ops that fuse address calculation with ALU computations, such as load-add-store sequences, to reduce dispatch pressure and improve in -bound code. One AGU primarily handles loads, while the other focuses on stores, enabling concurrent operations. Bonnell lacks dedicated SIMD execution units beyond basic MMX support, relying instead on the FP cluster for vector instructions. SSE and operations utilize the 128-bit XMM registers but are emulated by splitting 128-bit instructions into two 64-bit micro-ops processed sequentially on the FP ALUs, resulting in halved throughput for packed data compared to scalar FP. This approach prioritizes power efficiency over vector performance, with no for wider SIMD extensions like AVX.

Cache and Memory System

The Bonnell microarchitecture employs a hierarchical cache system designed to minimize latency and power consumption in low-power embedded applications. Each core features a dedicated level-1 (L1) instruction cache of 32 KiB, organized as 8-way set associative with 64-byte cache lines, optimized for sequential instruction fetches. Complementing this, the per-core L1 cache provides 24 KiB of storage, configured as 6-way set associative with the same 64-byte line size and a write-back replacement policy, which supports non-temporal stores to bypass caching for patterns. These L1 caches incorporate 1-bit parity protection rather than full ECC, prioritizing area efficiency over error correction in embedded scenarios. At the next level, Bonnell includes a unified L2 cache of 512 KiB per core, implemented as 8-way set associative with 64-byte lines and inclusive of L1 contents to simplify coherence . This L2 cache supports ECC for and integrates tags, LRU replacement state, and data arrays into a single structure to reduce power and area. In low-power variants, the L2 size can be configured down to 128 KiB with reduced 2-way associativity to further optimize use without L3 caching present in the hierarchy. Hardware prefetchers operate for both the L1 data cache and L2, employing stride-based detection to anticipate accesses and reduce miss rates in predictable workloads. (Note: While WikiChip is secondary, it directly references the primary IEEE papers above for these details.) Bonnell's memory subsystem interfaces via a (FSB) operating at 400–667 MHz, using source-synchronous signaling in GTL mode for addresses and data to ensure reliable transfers in multi-chip configurations. Early desktop and mobile variants, such as the Diamondville processors, support DDR2-667 or DDR2-800 through an external -based controller, with single-channel configurations limited to 2–8 GiB depending on the platform. Later system-on-chip (SoC) implementations, including Lincroft and subsequent designs, integrate a directly on-die to support low-power DDR2 up to 800 MT/s, enhancing efficiency by eliminating external dependencies. This design choice reflects Bonnell's focus on embedded integration, where the absence of an L3 cache keeps the shallow to align with power constraints.

First generation cores

Silverthorne microprocessor

The Silverthorne microprocessor, codenamed for Intel's Atom Z5xx series, represented the initial implementation of the Bonnell microarchitecture in a single-core design optimized for ultra-low power consumption. Released in April 2008 and fabricated on a node, it featured a single core, with support on select models such as Z520 and above, enabling efficient operation in power-constrained environments. Clock speeds for Silverthorne processors ranged from 0.8 GHz to 2.0 GHz, paired with a 533 MHz (FSB) to balance performance and energy efficiency. (TDP) varied from 0.65 W for the lowest-end models to 2.4 W for higher-speed variants, allowing deployment in battery-limited systems without . These specifications supported basic x86 instruction execution, including MMX, SSE, , and extensions, but lacked compatibility, restricting it to 32-bit operating systems and applications. Targeted primarily at mobile internet devices (MIDs) and ultra-mobile PCs, Silverthorne pioneered Intel's entry into the and embedded markets, emphasizing scalability for portable where power efficiency outweighed raw . Its design facilitated integration with low-power chipsets, such as the Intel US15W System Controller Hub, to deliver a total platform TDP under 5 W, marking a significant step in enabling always-connected mobile experiences.

Diamondville microprocessor

The Diamondville microprocessor, codenamed for Intel's expansion of the Bonnell microarchitecture into nettop applications, was introduced in June 2008 on a 45 nm process node. It supported both single-core and dual-core configurations, with support allowing two threads on single-core models and four threads on dual-core variants. This marked an evolution from the single-core Silverthorne, emphasizing multi-core scalability for improved performance in low-power desktop-like systems while maintaining the in-order execution pipeline of Bonnell. Clock speeds ranged from 1.6 GHz to 1.66 GHz, paired with frequencies of 533 MHz to 667 MHz, and ratings between 2.5 W and 8 W to suit ultra-low-power nettops. Single-core models in the Atom N2xx series, such as the N270 (1.6 GHz, 533 MHz FSB, 2.5 W TDP) and N280 (1.66 GHz, 667 MHz FSB, 2.5 W TDP), featured 512 KiB of L2 cache and were 32-bit only. The dual-core Atom N330 (1.6 GHz, 533 MHz FSB, 8 W TDP) introduced support and included 1 MB of L2 cache total, with 512 KiB allocated per core. These processors powered early netbooks and nettops, including the series (e.g., models 901 and 1005HA with N270) and various mini-PCs, delivering basic computing for web browsing and light tasks at sub-10 W power envelopes. The addition of dual-core options and selective compatibility enhanced multitasking capabilities compared to prior single-core Atoms, targeting the emerging market for affordable, energy-efficient personal computing devices.

Power requirements

The first-generation Bonnell cores were engineered for ultra-low power operation, achieving an average power consumption of approximately 220 mW under load and below 80 mW at idle. These cores support the C6 deep sleep state, which retains critical architectural state in a 10.5 KiB SRAM array at reduced voltage, enabling significant energy savings during periods of inactivity with high residency rates of 80-90%. Thermal design power (TDP) for Bonnell variants spans 0.65 W to 8 W, accommodating single-core Silverthorne designs at the lower end and dual-core Diamondville configurations at the higher end. relies on dynamic voltage and (DVFS), which adjusts from 600 MHz at 0.75 V to 2 GHz at 1 V, alongside to power down unused L2 cache ways and reduce leakage. The architecture lacks advanced beyond these mechanisms, instead leveraging the node to enable sub-1 W operation in mobile-oriented Silverthorne implementations. Bonnell delivers comparative efficiency of approximately 2.4 DMIPS/MHz (based on N270 benchmarks), prioritizing over raw throughput to suit embedded and mobile applications. This focus on energy efficiency distinguishes it from higher-performance x86 contemporaries, aligning with its design goals for prolonged battery life in low-power devices.

Second generation cores

Pineview microprocessor

The Pineview microprocessor represents the second-generation implementation of the Bonnell microarchitecture, introduced by in December 2009 as part of the Pine Trail platform. Fabricated on a , it integrates the CPU cores, , and on a single die, enabling a more compact design compared to the discrete components in first-generation Atom processors. Available in single-core and dual-core configurations, the single-core variants support two threads via , while dual-core models support four threads, allowing for modest multitasking in low-power environments. The Pineview lineup includes the Atom N4xx series for mobile and the D4xx series for desktop nettops, with clock speeds ranging from 1.66 GHz to 1.83 GHz and a operating at 533–667 MHz. (TDP) varies from 6.5 W for models like the N450 and N475 to 13 W for nettop variants such as the D525, balancing performance with energy efficiency for fanless or passively cooled systems. support encompasses single-channel DDR2-667 (up to 2 GB) for N4xx processors and DDR3-800 (up to 2 GB) for select D4xx models, providing sufficient bandwidth for basic applications. A key feature of Pineview is its integrated Intel Graphics Media Accelerator (GMA) 3150, a DirectX 9-compatible GPU clocked at 200–400 MHz with two execution units, which handles display output and light multimedia tasks without requiring a separate graphics chip. This integration, paired with the Poulsbo system controller hub for I/O connectivity, reduces overall platform power consumption to under 10 W in typical netbook configurations and improves video decoding capabilities over prior generations through hardware acceleration for formats like MPEG-2 and VC-1. Designed primarily for entry-level netbooks and nettops, Pineview processors targeted budget-conscious consumers seeking portable , web browsing, and office productivity, with systems appearing in devices from manufacturers like and Acer starting in early 2010. The architecture's emphasis on integration and low TDP enabled thinner, lighter form factors while maintaining compatibility with the x86 instruction set, including MMX, SSE, , , and extensions for efficient handling of everyday workloads.

Tunnel Creek microprocessor

The Tunnel Creek , codenamed for the E600 series, was announced in April 2010 as a low-power, based on the Bonnell microarchitecture, fabricated on a . It operates at clock speeds ranging from 600 MHz to 1.6 GHz, with a (TDP) of approximately 3 W, enabling efficient performance in power-constrained environments. As part of 's Queens Bay platform, it targets embedded systems such as point-of-sale terminals and , supporting an extended temperature range from -40°C to 85°C for industrial reliability. Tunnel Creek features a Front Side Bus (FSB) interface for system connectivity, with base support limited to the 32-bit x86 architecture, though select implementations include x86-64 extensions. It incorporates 512 KiB of unified L2 cache and adheres to the core Bonnell instruction set, including MMX, SSE, SSE2, SSE3, and SSSE3, but excludes SSE4 instructions to maintain simplicity and low power consumption. This design shares the fundamental pipeline and execution resources with other second-generation Bonnell implementations like Pineview, emphasizing in-order execution for embedded workloads. Targeted at industrial applications requiring robust operation without integrated graphics, Tunnel Creek's architecture prioritizes minimal power draw and thermal resilience, making it suitable for unattended deployments in retail and systems. Its Queens Bay integration facilitates scalable embedded solutions, with the processor's FSB enabling compatibility with external chipsets for I/O expansion.

Lincroft microprocessor

The Lincroft , codenamed for the Intel Z600 series, represents a system-on-chip (SoC) implementation of the Bonnell microarchitecture tailored for ultra-mobile devices. Fabricated on a , it features a single in-order core with support, operating at base clock speeds ranging from 800 MHz to 1.5 GHz across variants, and a (TDP) between 1.3 W and 3 W to prioritize battery efficiency in portable form factors. Released in May as part of Intel's Moorestown platform, Lincroft integrates key components including the PowerVR SGX 535-based Graphics Media Accelerator (GMA) 600 for basic 3D rendering and video decode up to , alongside a single-channel DDR2-800 supporting up to 2 GB of RAM. The full Moorestown platform, encompassing Lincroft paired with the Langwell I/O hub, became available to original equipment manufacturers (OEMs) in late , with consumer devices shipping in early 2011. Designed primarily for mobile internet devices (MIDs) and early tablets, Lincroft powers the Oak Trail variant of Moorestown, emphasizing thin, lightweight designs with extended battery life through aggressive and low-frequency modes down to 600 MHz. The Langwell companion chip enhances connectivity by integrating support for (802.11n), cellular (HSPA), , and GPS, enabling seamless wireless operation without discrete modules in many configurations. This integration marked a shift toward more complete SoC solutions compared to prior discrete Atom implementations, targeting platforms like netbooks, slates, and handheld media players.

Stellarton microprocessor

The Stellarton microprocessor, announced by on November 22, 2010, represents a specialized variant of the Bonnell microarchitecture integrated with (FPGA) technology for embedded systems. Fabricated on a , it features a single-core design based on the Atom E600 series (codenamed Tunnel Creek), with clock speeds reaching up to 1.3 GHz and a (TDP) of approximately 3 W. This configuration retains the core Bonnell traits, including in-order execution capable of issuing up to two instructions per cycle, support for MMX, SSE, , , and instructions, along with optional compatibility in select models. A key innovation in is its multi-chip package (MCP) integration with an Arria II GX FPGA, containing 60,214 logic elements, 312 DSP blocks, and 5.2 Mb of embedded memory, connected via a PCIe interface for high-speed data transfer between the CPU and reconfigurable logic. This design enables customizable acceleration for tasks such as signal processing or custom I/O, making it suitable for industrial control systems, portable medical devices, vision systems, and VoIP equipment that require tailored hardware extensions. The FPGA portion allows users to implement user-defined interfaces, enhancing flexibility in embedded applications without altering the standard x86 ecosystem. Production of the Stellarton was limited in volume, targeting low-quantity deployments starting in January 2011, with unit pricing between $61 and $106 for orders of 1,000 pieces, reflecting its niche role in customizable embedded solutions rather than high-volume consumer markets.

Sodaville SoC

The Sodaville SoC, also known as the Intel Atom CE4100 series, was launched in September 2009 as a media-focused system-on-chip built on the using the Bonnell microarchitecture. It features a single-core design operating at up to 1.2 GHz with 512 KB of L2 cache and a (TDP) of approximately 7 W, enabling efficient performance in low-power embedded environments. This configuration supports DDR2 (with DDR3 compatibility in select variants) and is designed for 32-bit x86 execution, providing compatibility with a wide range of architecture software. Key to its media-centric role, the Sodaville integrates for HD video decoding, capable of handling up to two simultaneous streams in formats such as MPEG-4 (including certification) and featuring decode support. The on-chip graphics are powered by the Intel GMA 500, which includes advanced 3D capabilities with OpenGL ES 2.0 support, suitable for rendering TV widgets, streaming video, and basic 3D gaming in consumer devices. Connectivity options encompass USB 2.0 ports and SATA-300 for storage, while the accompanying (PCH), such as the EG20T, adds for networked applications. Targeted primarily at consumer electronics like Internet-connected TVs, set-top boxes, Blu-ray players, and IPTV devices, the Sodaville platform reduces system complexity by integrating components such as a NAND flash controller, display processor, transport processor, and a dedicated security processor alongside companion chips for enhanced storage and networking. This design lowers overall chip count and costs, facilitating the delivery of content, 10 playback, and high-definition media experiences in embedded systems.

Groveland SoC

The Groveland SoC, codenamed for Intel's Atom CE4200 processor, represents a second-generation system-on-chip integration of the Bonnell microarchitecture tailored for platforms. Announced on September 14, 2010, at the Intel Developer Forum, it utilizes a 45 nm manufacturing process to deliver efficient in compact, low-power designs. Built around a Bonnell CPU core clocked at 1.2 GHz, the Groveland SoC incorporates the Graphics Media Accelerator 600 (GMA 600), which leverages a PowerVR SGX535 graphics core for 2D/3D rendering and hardware-accelerated video decoding. It supports DDR3 memory via a dual-channel controller and includes integrated HD audio processing alongside extensive I/O options such as multiple USB ports, PCIe interfaces, 1.4a output, and MoCA for home networking. These features enable seamless handling of high-definition content, including H.264 encoding and stereo 3D video playback. As a platform-on-chip solution, Groveland offers enhanced integration over the preceding Sodaville SoC (CE4100) through expanded I/O connectivity and advanced power management for compliance, facilitating features like and ad insertion in media streams. Supporting the instruction set with extensions, it targets all-in-one media players, , smart TVs, and home gateways, enabling "sync-and-go" functionality for networked consumer devices.

Third generation cores

Cedarview microprocessor

The Cedarview microprocessor, codenamed for Intel's third-generation Atom processors, represents a 32 nm shrink of the Bonnell microarchitecture known as Saltwell, aimed at enhancing efficiency for and low-end applications. Released in the fourth quarter of 2011, these processors were manufactured using Intel's Hi-K process to reduce power consumption while maintaining compatibility with existing x86 software. The lineup includes the Atom N2000 series for mobile and D2000 series for nettops, featuring dual-core designs with Technology to support up to four threads. Clock speeds range from 1.6 GHz for entry-level models like the N2600 to 2.13 GHz for higher-end variants such as the D2700, with (TDP) ratings spanning 3.5 W to 10 W depending on the SKU. Integrated graphics in Cedarview processors utilize the (GMA) 3600 series, based on the PowerVR SGX 545 core, which offers improved shader performance over prior generations through support for 9.0c, 3.0, and hardware-accelerated video decode for formats like H.264 and MPEG-2. The N2000 series employs the GMA 3600 at up to 400 MHz, while the D2000 series uses the faster GMA 3650 clocked at up to 640 MHz, enabling better multimedia handling in power-constrained devices. Memory support is limited to single-channel DDR3-800 or DDR3-1066, with maximum capacities of 2 GB for lower-power models and 4 GB for others, prioritizing low latency over bandwidth for basic computing tasks. The Cedar Trail platform incorporating Cedarview processors introduced enhancements like USB 3.0 support via the chipset, alongside AES-NI instructions for accelerated encryption in compatible workloads, though adoption was limited by the era's software ecosystem. Targeted at entry-level laptops and netbooks, Cedarview delivered approximately 28% higher CPU performance compared to the preceding Pineview generation at comparable power levels, primarily through the process shrink and architectural tweaks that allowed modest clock increases without exceeding thermal envelopes. This efficiency focus extended battery life in portable devices, making it suitable for web browsing, light office productivity, and media playback, though it lagged behind contemporary AMD Fusion APUs in multi-threaded scenarios.

Penwell SoC

The Penwell system-on-chip (SoC), codenamed for Intel's Medfield platform, represented a key advancement in by integrating x86 architecture into smartphones and low-power tablets. Fabricated on a 32 nm high-k , it utilized the Saltwell core—a refined derivative of the Bonnell microarchitecture—optimized for ultra-low power consumption in battery-constrained environments. Launched in the first quarter of 2012, Penwell delivered enhanced through process shrinkage, enabling sustained performance in mobility scenarios without the thermal overhead of larger systems. At its heart, the Penwell SoC embodied the Intel Atom Z2460 processor, featuring a single computational core with technology to support two threads simultaneously. This configuration operated at a base clock of 1.6 GHz, while maintaining a (TDP) of approximately 3 W to prioritize battery life over raw speed. Integrated graphics were handled by a PowerVR SGX540 GPU running at 400 MHz, capable of rendering displays and accelerating common mobile workloads like video playback and basic gaming. Connectivity was bolstered by support for LTE and modems, including compatibility with Intel's XMM 6260 HSPA+ modem, facilitating high-speed wireless data in urban environments. Memory and peripheral integration further tailored Penwell for seamless assembly. It incorporated a dual-channel LPDDR2-800 , supporting up to 2 GB of low-power DRAM with a bandwidth of 6.4 GB/s, ideal for multitasking in resource-limited OS environments. interfaces included dual MIPI CSI ports for multi-megapixel camera sensors and dual MIPI DSI lanes for high-resolution displays up to 1366x768 resolution, alongside 1.3a output for external connectivity. These features minimized external components, reducing overall device cost and power draw. Penwell targeted Android-based smartphones, powering devices like the Lenovo K800—Intel's inaugural commercial x86 smartphone released in China during mid-2012. This 4.5-inch 720p handset demonstrated the SoC's viability for premium mobile experiences, including smooth UI navigation and multimedia consumption, while paving the way for broader x86 adoption in ARM-dominated markets. Despite limited market penetration due to ecosystem challenges, Penwell's design underscored Intel's strategic push toward integrated, power-efficient SoCs for emerging mobile platforms.

Berryville SoC

The Berryville SoC, announced in March 2012, is Intel's Atom CE5300 media processor series based on the 32 nm Saltwell , targeted at applications such as set-top boxes, smart TVs, and (NAS) devices. It features a dual-core design with support for up to four threads, operating at clock speeds of 1.2 GHz (CE5315) or 1.6 GHz (CE5335), with a (TDP) of approximately 3.5 W. Branded under the Intel Atom CE5300 series, this system-on-chip (SoC) integrates the CPU, graphics, and media processing components to enable streaming and synchronization in embedded media environments. The Berryville SoC includes integrated 2D/3D graphics acceleration with support for hardware video decode (e.g., H.264 up to ), along with a DDR3 supporting up to 2 GB at 1066 MT/s. Connectivity options include 1.4, LVDS, USB 2.0, and Ethernet MAC, facilitating integration into media gateways and IP set-top boxes. It supports extensions (Intel VT-x) for secure multi-OS environments and is optimized for low-power operation in always-on devices. Targeted at the consumer media market, Berryville powered early and solutions, emphasizing multimedia performance and power efficiency over general computing. Its design enabled features like streaming and basic , though it saw limited adoption compared to ARM-based competitors in the embedded space.

Cloverview SoC

The Cloverview SoC, released in September 2012, represents Intel's tablet-oriented implementation of the 32 nm Saltwell as part of the Clover Trail platform. It features a dual-core CPU configuration supporting for up to four threads, with clock speeds reaching 1.8 GHz in its primary variant, the Atom Z2760. The is approximately 3 W, enabling extended battery life in portable devices while integrating essential peripherals for touch-enabled computing. Part of the Atom Z27xx series, Cloverview incorporates an enhanced PowerVR SGX545 graphics core clocked at 533 MHz, providing for video decode and improved capabilities compared to prior generations. This GPU delivers performance suitable for Windows tablet workloads, including basic gaming and UI rendering. Additionally, it includes dedicated touch controller integration for gestures, supporting up to 10-point input, which streamlines design for devices. The SoC also features connectivity options such as , , and NFC, alongside multiple display outputs including and MIPI-DSI for external monitors up to resolution. Cloverview supports dual-channel LPDDR2-800 memory up to 2 GB, prioritizing low-power operation over higher-speed alternatives to maintain efficiency in battery-constrained environments. Optimized for full , the platform enables x86 application compatibility and leverages hardware features like Secure Key for enhanced security in consumer scenarios. It powered several early Windows tablets, including the VivoTab Smart, ThinkPad Tablet 2, and Acer Iconia W510, targeting users seeking convertible hybrids with support and productivity tools.

Centerton SoC

The Centerton SoC, part of Intel's Atom S1200 processor series, represents a low-power system-on-chip (SoC) designed specifically for embedded server applications. Released in December 2012 and fabricated on a using the Saltwell microarchitecture, it features a dual-core configuration with Technology enabling four threads total. The series includes three variants: the S1220 and S1240 models operating at 1.6 GHz, and the S1260 at 2.0 GHz, all with a (TDP) as low as 6 W to support dense, energy-efficient deployments. Unlike consumer-oriented Atom processors, Centerton omits integrated to prioritize server-grade functionality and power savings. Centerton's memory subsystem includes an integrated controller supporting single-channel DDR3 or DDR3L at speeds up to MT/s, with a maximum capacity of 8 GB and full error-correcting (ECC) capability for enhanced —providing single-bit error correction and double-bit error detection. This ECC support, combined with features like a patrol scrub engine for proactive maintenance and advanced error reporting (AER), addresses reliability demands in server environments where risks are high. The SoC also incorporates Intel VT-x extensions, allowing efficient partitioning of workloads across virtual machines without significant overhead. For connectivity, Centerton provides up to eight lanes of (PCIe) 2.1 in configurable root ports (e.g., x8, 2x x4, or 4x x2), alongside 3.0 ports for storage interfaces and USB 2.0 support, enabling integration into compact systems without external chipsets. These I/O capabilities, bolstered by reliability features such as a and thermal monitoring, make it well-suited for microservers and storage appliances, where low power consumption (under 10 W TDP across models) facilitates high-density racks while maintaining server-class uptime. Targeted at applications like web hosting, network switching, and entry-level storage, Centerton aimed to compete in the emerging microserver market by offering x86 compatibility and in a smartphone-like power envelope.

Briarwood SoC

The Briarwood SoC represents a storage-optimized refresh of 's low-power Atom processor line for embedded microserver applications, leveraging the 32 nm Saltwell microarchitecture. Announced in April 2013 at the Intel Developer Forum in , it builds on the preceding Centerton design by offering improved power efficiency and additional on-chip resources tailored for storage workloads, such as enhanced GPIO and peripheral integration. Fabricated on a node, the Briarwood SoC features a dual-core configuration based on the Saltwell cores, with clock speeds up to 2.0 GHz depending on the SKU in the S12x9 series. Thermal design power (TDP) ranges from 6 W to 9 W, enabling operation in thermally constrained environments up to a maximum of 102°C. Unlike consumer-oriented Atom SoCs, it omits an integrated to prioritize compute and I/O efficiency. As part of the Intel Atom S12x9 series, Briarwood integrates a single-channel DDR3 supporting ECC configurations up to 8 GB at speeds of 1066 MT/s or 1333 MT/s, along with expanded GPIO pins (up to 30) for flexible peripheral connectivity in storage arrays. It includes support for PCIe 2.0 interfaces (up to 8 lanes), USB 2.0, and ports, with optimizations for and SAN/NAS systems. Security is provided through the Execute Disable Bit for basic , with thermal monitoring via a digital sensor per thread. Targeted at storage appliances and microservers, the Briarwood SoC emphasizes in dense setups, such as SAN/NAS systems, where its low TDP and integrated peripherals reduce system complexity and power draw compared to discrete component designs.

Development and legacy

History and roadmap

The Bonnell microarchitecture was developed between 2004 and 2008 as Intel's initial foray into low-power x86 processors, aiming to compete in the emerging market for mobile internet devices (MIDs) and embedded systems. This effort, which began as a ground-up x86 design project in 2004 focused on low power consumption, built on Intel's high-k metal gate process technology to achieve ultra-low power consumption while maintaining x86 compatibility, marking a departure from higher-performance architectures like Core. In 2006, Intel's sale of its ARM-based processor division further emphasized its commitment to x86 for embedded markets. The design prioritized simplicity and efficiency, with development accelerating amid growing demand for portable . Bonnell debuted in April 2008 alongside the Silverthorne processor, Intel's first Atom-branded CPU, targeted at MIDs and nettops on a 45 nm process. The initial roadmap from 2008 to 2011 outlined a progression: first-generation 45 nm implementations for MIDs and nettops, followed by second-generation variants integrating integrated graphics processing (IGP) and system-on-chip (SoC) designs for netbooks and tablets, and a third-generation 32 nm shrink to expand into broader embedded applications. This evolution was heavily influenced by the 2008-2009 netbook boom, which drove rapid adoption of low-cost, power-efficient x86 devices and prompted Intel to accelerate SoC integrations for thinner form factors. Key milestones included the Menlow platform in 2008, a launched reference design for MIDs featuring Silverthorne and the Poulsbo chipset, which served as a precursor but was rebranded to Centrino Atom. Moorestown followed in 2010, introducing the Lincroft SoC based on Bonnell for smartphones and tablets, with significant power reductions over prior generations. Cedar Trail arrived in late 2011 as the 32 nm iteration, enhancing capabilities for netbooks and embedded devices. Internal codenames like Oak Trail, intended for tablet SoCs, faced delays and shifted from late 2010 plans to an early 2011 release, reflecting challenges in ecosystem readiness and driver development.

Discontinuation and successors

The Bonnell microarchitecture was discontinued in 2013, coinciding with the final production runs of its third-generation implementations in cores like Cedarview and Penwell. Intel accepted last orders for key Cedarview processors, such as the Atom D2550 and D2560, until May 23, 2014, with shipments concluding by November 7, 2014. Earlier variants, including Pineview-based models, had reached end-of-life as early as 2012. By 2016, full end-of-life status had been achieved for most Bonnell variants, ending official support and servicing. Bonnell's successor was the microarchitecture, launched in May 2013 on Intel's and deployed in platforms such as Bay Trail for consumer devices and Avoton for servers. Unlike Bonnell's in-order design, Silvermont introduced , branch prediction enhancements, and wider execution units, resulting in up to three times the overall performance at equivalent power levels compared to Bonnell-based Atoms. Bonnell significantly shaped the low-power x86 landscape by powering the surge from 2008 to 2010, delivering sub-$300 devices with acceptable battery life and compatibility that broadened access to portable computing. Its emphasis on ultra-low voltage operation and integrated features influenced ongoing Atom advancements, including the 14 nm Airmont cores in and cores in , which refined efficiency for embedded and mobile applications. As of 2025, no Bonnell production remains active, with all lines transitioned to successors; however, legacy embedded systems continue to utilize surviving units in industrial and niche deployments.

References

  1. https://ieeexplore.ieee.org/document/4735552/
  2. https://perfmon-events.intel.com/atom.html
  3. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z540-z530-z520-z510-z500-45-nm-technology-datasheet.pdf
  4. https://cdrdv2-public.intel.com/671378/335279-performance-monitoring-events-guide.pdf
  5. https://www.agner.org/optimize/microarchitecture.pdf
  6. https://en.wikichip.org/wiki/intel/microarchitectures/bonnell
  7. https://ieeexplore.ieee.org/document/4735552
  8. https://ieeexplore.ieee.org/document/4672105
  9. https://www.intel.com/content/dam/doc/product-brief/mobile-computing-atom-intel-atom-processor-brief.pdf
  10. https://www.intel.com/pressroom/archive/reference/Moorestown_backgrounder.pdf
  11. https://www.techpowerup.com/cpu-specs/atom-z530.c1423
  12. https://arstechnica.com/gadgets/2008/04/new-atom-cpu-marks-intels-baby-steps-into-embedded-world/
  13. https://www.tweaktown.com/news/9255/intel_announces_five_atom_processors/index.html
  14. http://onnocenter.or.id/wiki/index.php/Intel_Atom
  15. https://ark.intel.com/content/www/us/en/ark/products/35036/intel-atom-processor-n270-512k-cache-1-60-ghz-533-mhz-fsb.html
  16. https://en.wikichip.org/wiki/intel/atom/330
  17. https://www.intel.com/pressroom/archive/releases/2008/20080302comp.htm
  18. https://news.softpedia.com/news/Intel-s-Pineview-Processors-Debut-New-Netbooks-Due-Out-in-January-130289.shtml
  19. https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/atom-netbooks-brief.pdf
  20. https://www.notebookcheck.net/Intel-Atom-N450-Notebook-Processor.23722.0.html
  21. https://www.techpowerup.com/cpu-specs/atom-n450.c1412
  22. https://www.techpowerup.com/gpu-specs/gma-3150.c1794
  23. https://www.pcper.com/2009/12/intel-launches-updated-atom-platform-with-pine-trail-technology/
  24. https://www.intel.com/pressroom/archive/releases/2010/20100413comp.htm
  25. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-e6xx-series-datasheet.pdf
  26. https://download.intel.com/newsroom/kits/idf/2010_fall/pdfs/Day2_Tunnel_Creek_Factsheet.pdf
  27. https://downloads.bl4ckb0x.de/download.intel.com/pressroom/kits/events/idfspr_2010/pdfs/Tech_Insight-Tunnel_Creek.pdf
  28. https://en.wikichip.org/wiki/intel/atom/z600
  29. https://en.wikichip.org/wiki/intel/cores/lincroft
  30. https://www.techpowerup.com/cpu-specs/atom-z600.c1427
  31. https://technical.city/en/cpu/Atom-Z600
  32. https://en.wikichip.org/wiki/intel/platforms/oak_trail
  33. https://en.wikichip.org/wiki/intel/platforms/moorestown
  34. https://www.intel.com/pressroom/archive/releases/2008/20081019comp.htm
  35. https://phys.org/news/2009-02-lg-intel-collaborate-future-mobile.html
  36. https://www.intc.com/news-events/press-releases/detail/705/intel-expands-customer-choice-with-first-configurable
  37. https://halfhill.com/mpr/2010/M50_Intel-Stellarton.pdf
  38. https://www.intel.com/pressroom/archive/releases/2009/20090924comp_b.htm
  39. https://www.techpowerup.com/cpu-specs/atom-ce4100.c1438
  40. https://www.drivermax.com/driver-download/0/Network%2BAdapters/Intel/Intel%28R%29%2BPlatform%2BController%2BHub%2BEG20T%2BGigabit%2BEthernet%2BController%2B-%2B8802
  41. https://en.wikichip.org/wiki/intel/cores/groveland
  42. https://www.intc.com/news-events/press-releases/detail/725/intel-opens-software-app-store-offers-new-intel-atom-chips
  43. https://www.eetimes.com/intel-details-embedded-soc-moves/
  44. https://en.wikichip.org/wiki/intel/microarchitectures/saltwell
  45. https://www.techpowerup.com/145083/intel-readies-32-nm-cedar-view-atom-processors-for-late-2011
  46. https://www.intel.com/content/www/us/en/products/sku/58916/intel-atom-processor-n2600-1m-cache-1-6-ghz/specifications.html
  47. https://www.intel.com/content/www/us/en/products/sku/65470/intel-atom-processor-d2550-1m-cache-1-86-ghz/specifications.html
  48. https://www.notebookcheck.net/Intel-Graphics-Media-Accelerator-GMA-3600.60198.0.html
  49. https://www.intel.com/content/dam/doc/datasheet/atom-d2000-n2000-vol-1-datasheet.pdf
  50. https://pcper.com/2011/12/intel-releases-new-cedar-trail-atom-processors/
  51. https://old.hotchips.org/wp-content/uploads/hc_archives/hc24/HC24-7-SOC/HC24.29.730-Medfield-Zahir-Intel.pdf
  52. https://www.intel.com/content/www/us/en/products/sku/70098/intel-atom-processor-z2460-512k-cache-up-to-1-60-ghz/specifications.html
  53. https://www.notebookcheck.net/Intel-Atom-Z2460-Notebook-Processor.69533.0.html
  54. https://www.realworldtech.com/medfield/3/
  55. https://www.theverge.com/2012/1/10/2697615/lenovo-to-make-the-first-intel-powered-medfield-phone
  56. https://www.gsmarena.com/lenovo_k800-4445.php
  57. https://www.cnx-software.com/2012/03/21/intel-announces-atom-ce5300-media-processor-for-stbs-and-smart-tvs/
  58. https://www.techpowerup.com/180932/intel-introduces-atom-ce5300-soc-for-consumer-nas-servers
  59. https://www.notebookcheck.net/Intel-unveils-the-Atom-CE5300-media-chip.71957.0.html
  60. https://www.slashgear.com/intel-unveils-new-berryville-atom-ce5300-media-processor-20219160/
  61. https://www.newelectronics.co.uk/content/news/intel-media-processor-targets-next-gen-set-top-boxes/
  62. https://community.synology.com/enu/forum/17/post/61715
  63. https://www.intel.com/content/www/us/en/products/sku/70105/intel-atom-processor-z2760-1m-cache-1-80-ghz/specifications.html
  64. https://www.techpowerup.com/cpu-specs/atom-z2760.c1437
  65. https://www.notebookcheck.net/Intel-Atom-Z2760-Notebook-Processor.82818.0.html
  66. https://www.techpowerup.com/gpu-specs/intel-cloverview.g904
  67. https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/atom-z2760-datasheet.pdf
  68. https://download.intel.com/newsroom/kits/atom/z2760/pdfs/Intel-Atom-Z2760_FactSheet.pdf
  69. https://www.eweek.com/mobile/atom-z2760-clover-trail/
  70. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-processor-s1200-datasheet-vol-1.pdf
  71. https://www.intc.com/news-events/press-releases/detail/533/intel-delivers-the-worlds-first-6-watt-server-class
  72. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-processor-s1200-datasheet-vol-2.pdf
  73. https://hothardware.com/news/intel-unveils-new-atom-and-xeon-processors-and-future-rack-scale-architecture-at-idf-beijing
  74. https://www.theregister.com/2013/04/10/intel_server_chip_preview_idf_beijing/
  75. https://www.cpu-world.com/news_2012/2012111401_Specifications_of_Briarwood_Atom_processors.html
  76. https://www.guru3d.com/story/intel-atom-briarwood-specifications-surface/
  77. https://www.qsan.com/en/newspage/qsan-announces-new-16g-fibre-channel-storage-solutions
  78. https://www.zdnet.com/article/inside-intels-atom/
  79. https://www.intel.com/pressroom/archive/releases/2008/20080401comp.htm
  80. https://www.zdnet.com/article/will-intels-atom-overhaul-fuel-another-netbook-boom/
  81. https://www.intel.com/pressroom/kits/events/ces2008/CES_FactSheet.pdf
  82. https://www.intel.com/pressroom/archive/releases/2010/20100504comp.htm
  83. https://www.theregister.com/2011/08/18/intel_cedar_trail_atom_delay/
  84. https://www.bbc.com/news/technology-13038481
  85. https://www.cpu-world.com/CPUs/Atom/Intel-Atom%20D2550.html
  86. https://ark.intel.com/content/www/us/en/ark/products/series/62426/intel-atom-processor-d-series.html
  87. https://www.anandtech.com/show/6936/intels-silvermont-architecture-revealed-getting-serious-about-mobile/4
  88. https://www.wired.com/2009/02/mf-netbooks/
Add your contribution
Related Hubs
User Avatar
No comments yet.