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EPROM
EPROM
EPROM
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An EPROM: the Texas Instruments TMS27C040, a CMOS chip with 4 megabits of storage and 8-bit output (shown here in a 600-mil ceramic dual-in-line package). The TMS27C040 operates at 5 volts, but must be programmed at 13 volts.[1]
Computer memory and data storage types
General
Volatile
RAM
Historical
Non-volatile
ROM
NVRAM
Early-stage NVRAM
Analog recording
Optical
In development
Historical

An EPROM (rarely EROM), or erasable programmable read-only memory, is a type of programmable read-only memory (PROM) chip that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to strong ultraviolet (UV) light source (such as from a mercury-vapor lamp). EPROMs are easily recognizable by the transparent fused quartz (or on later models, resin) window on the top of the package, through which the silicon chip is visible, and which permits exposure to ultraviolet light during erasing.[2] It was invented by Dov Frohman in 1971.[3]

Operation

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An Intel 1702A EPROM, one of the earliest EPROM types (1971), 256 by 8 bit. The small quartz window admits UV light for erasure.

Development of the EPROM memory cell started with investigation of faulty integrated circuits where the gate connections of transistors had broken. Stored charge on these isolated gates changes their threshold voltage.

Following the invention of the MOSFET (metal–oxide–semiconductor field-effect transistor) by Mohamed Atalla and Dawon Kahng at Bell Labs, presented in 1960, Frank Wanlass studied MOSFET structures in the early 1960s. In 1963, he noted the movement of charge through oxide onto a gate. While he did not pursue it, this idea would later become the basis for EPROM technology.[4]

In 1967, Dawon Kahng and Simon Min Sze at Bell Labs proposed that the floating gate of a MOSFET could be used for the cell of a reprogrammable ROM (read-only memory).[3] Building on this concept, Dov Frohman of Intel invented EPROM in 1971,[3] and was awarded U.S. patent 3,660,819 in 1972. Frohman designed the Intel 1702, a 2048-bit EPROM, which was announced by Intel in 1971.[3]

Each storage location of an EPROM consists of a single field-effect transistor. Each field-effect transistor consists of a channel in the semiconductor body of the device. Source and drain contacts are made to regions at the end of the channel. An insulating layer of oxide is grown over the channel, then a conductive (silicon or aluminum) gate electrode is deposited, and a further thick layer of oxide is deposited over the gate electrode. The floating-gate electrode has no connections to other parts of the integrated circuit and is completely insulated by the surrounding layers of oxide. A control gate electrode is deposited and further oxide covers it.[5]

To retrieve data from the EPROM, the address represented by the values at the address pins of the EPROM is decoded and used to connect one word (usually an 8-bit byte) of storage to the output buffer amplifiers. Each bit of the word is a 1 or 0, depending on the storage transistor being switched on or off, conducting or non-conducting.

A cross-section of a floating-gate transistor

The switching state of the field-effect transistor is controlled by the voltage on the control gate of the transistor. Presence of a voltage on this gate creates a conductive channel in the transistor, switching it on. In effect, the stored charge on the floating gate allows the threshold voltage of the transistor to be programmed.

Storing data in the memory requires selecting a given address and applying a higher voltage to the transistors. This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode. When the high voltage is removed, the electrons are trapped on the electrode.[6] Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades.

The programming process is not electrically reversible. To erase the data stored in the array of transistors, ultraviolet light is directed onto the die. Photons of the UV light cause ionization within the silicon oxide, which allows the stored charge on the floating gate to dissipate. Since the whole memory array is exposed, all the memory is erased at the same time. The process takes several minutes for UV lamps of convenient sizes; sunlight would erase a chip in weeks, and indoor fluorescent lighting over several years.[7] Generally, the EPROMs must be removed from equipment to be erased, since it is not usually practical to build in a UV lamp to erase parts in-circuit. Electrically Erasable Programmable Read-Only Memory (EEPROM) was developed to provide an electrical erase function and has now mostly displaced ultraviolet-erased parts.

Details

[edit]
Atmel AT27C010 - an OTP EPROM

As the quartz window is expensive to make, OTP (one-time programmable) chips were introduced; here, the die is mounted in an opaque package so it cannot be erased after programming – this also eliminates the need to test the erase function, further reducing cost. OTP versions of both EPROMs and EPROM-based microcontrollers are manufactured. However, OTP EPROM (whether separate or part of a larger chip) is being increasingly replaced by EEPROM for small sizes, where the cell cost isn't too important, and flash for larger sizes.

A programmed EPROM retains its data for a minimum of ten to twenty years,[8] with many still retaining data after 35 or more years, and can be read an unlimited number of times without affecting the lifetime. The erasing window must be kept covered with an opaque label to prevent accidental erasure by the UV found in sunlight or camera flashes. Old PC BIOS chips were often EPROMs, and the erasing window was often covered with an adhesive label containing the BIOS publisher's name, the BIOS revision, and a copyright notice. Often this label was foil-backed to ensure its opacity to UV.

Erasure of the EPROM begins to occur with wavelengths shorter than 400 nm. Exposure time for sunlight of one week or three years for room fluorescent lighting may cause erasure. The recommended erasure procedure is exposure to UV light at 253.7 nm of at least 15 Ws/cm2, usually achieved in 20 to 30 minutes with the lamp at a distance of about 2.5 cm.[9]

Erasure can also be accomplished with X-rays:

Erasure, however, has to be accomplished by non-electrical methods, since the gate electrode is not accessible electrically. Shining ultraviolet light on any part of an unpackaged device causes a photocurrent to flow from the floating gate back to the silicon substrate, thereby discharging the gate to its initial, uncharged condition (photoelectric effect). This method of erasure allows complete testing and correction of a complex memory array before the package is finally sealed. Once the package is sealed, information can still be erased by exposing it to X radiation in excess of 5*104 rads,[a] a dose which is easily attained with commercial X-ray generators.[10]

In other words, to erase your EPROM, you would first have to X-ray it and then put it in an oven at about 600 degrees Celsius (to anneal semiconductor alterations caused by the X-rays). The effects of this process on the reliability of the part would have required extensive testing so they decided on the window instead.[11]

EPROMs have a limited but large number of erase cycles; the silicon dioxide around the gates accumulates damage from each cycle, making the chip unreliable after several thousand cycles. EPROM programming is slow compared to other forms of memory. Because higher-density parts have little exposed oxide between the layers of interconnects and gate, ultraviolet erasing becomes less practical for very large memories. Even dust inside the package can prevent some cells from being erased.[12]

Application

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For large volumes of parts (thousands of pieces or more), mask-programmed ROMs are the lowest cost devices to produce. However, these require many weeks lead time to make, since the artwork or design in an IC mask layer or photomask must be altered to store data on the ROMs. Initially, it was thought that the EPROM would be too expensive for mass production use and that it would be confined to development only. It was soon found that small-volume production was economical with EPROM parts, particularly when the advantage of rapid upgrades of firmware was considered.

Some microcontrollers, from before the era of EEPROMs and flash memory, use an on-chip EPROM to store their program. Such microcontrollers include some versions of the Intel 8048, the Freescale 68HC11, and the "C" versions of the PIC microcontroller. Like EPROM chips, such microcontrollers came in windowed (expensive) versions that were used for debugging and program development. The same chip came in (somewhat cheaper) opaque OTP packages for production. Leaving the die of such a chip exposed to light can also change behavior in unexpected ways when moving from a windowed part used for development to a non-windowed part for production.

EPROM generations, sizes and types

[edit]

The first generation 1702 devices were fabricated with the p-MOS technology. They were powered with VCC = VBB = +5 V and VDD = VGG = -9 V in Read mode, and with VDD = VGG = -47 V in Programming mode.[13][14]

The second generation 2704 / 2708 devices switched to n-MOS technology and to three-rail VCC = +5 V, VBB = -5 V, VDD = +12 V power supply with VPP = 12 V and a +25 V pulse in Programming mode.

The third generation 2716 / 2732 devices upgraded to an evolved n-MOS technology that required only a single-rail VCC = +5 V power supply for read operations, and a single VPP = +25 V[15] programming voltage without pulse. The unneeded VBB and VDD pins were reused for additional address bits allowing larger capacities (2716 / 2732) in the same 24-pin package, and even larger capacities with larger packages. Later the decreased cost of the CMOS technology allowed the same devices to be fabricated using it, adding the letter "C" to the device numbers (27xx(x) are n-MOS and 27Cxx(x) are CMOS).

While parts of the same size from different manufacturers are compatible in read mode, different manufacturers added different and sometimes multiple programming modes leading to subtle differences in the programming process. This prompted larger capacity devices to introduce a "signature mode", allowing the manufacturer and device to be identified by the EPROM programmer. It was implemented by forcing +12 V on pin A9 and reading out two bytes of data. However, as this was not universal, programmer software also would allow manual setting of the manufacturer and device type of the chip to ensure proper programming.[16]

EPROM Type Year Size — bits Size — bytes Length (hex) Last address (hex) Technology
1702, 1702A 1971 2 Kbit 256 100 FF PMOS
2704 1975 4 Kbit 512 200 1FF NMOS
IM6654 4 Kbit 512 200 1FF CMOS
2708 1975 8 Kbit 1 KB 400 3FF NMOS
2716, 27C16, TMS2716, 2516 1977 16 Kbit 2 KB 800 7FF NMOS/CMOS
2732, 27C32, 2532 1979 32 Kbit 4 KB 1000 FFF NMOS/CMOS
2764, 27C64, 2564 64 Kbit 8 KB 2000 1FFF NMOS/CMOS
27128, 27C128 128 Kbit 16 KB 4000 3FFF NMOS/CMOS
27256, 27C256 256 Kbit 32 KB 8000 7FFF NMOS/CMOS
27512, 27C512 512 Kbit 64 KB 10000 FFFF NMOS/CMOS
27C010, 27C100 1 Mbit 128 KB 20000 1FFFF CMOS
27C020 2 Mbit 256 KB 40000 3FFFF CMOS
27C040, 27C400, 27C4001 4 Mbit 512 KB 80000 7FFFF CMOS
27C080 8 Mbit 1 MB 100000 FFFFF CMOS
27C160 16 Mbit 2 MB 200000 1FFFFF CMOS
27C320, 27C322 32 Mbit 4 MB 400000 3FFFFF CMOS
EEPROM 8kbit
K573RF1
EPROM 8kbit - detail of 4 bits
[edit]
  • A 32 KB (256 Kbit) EPROM. The -12 suffix indicates this device has a 120 nanosecond access time.
    A 32 KB (256 Kbit) EPROM. The -12 suffix indicates this device has a 120 nanosecond access time.
  • This 8749 Microcontroller stores its program in an internal EPROM.
    This 8749 Microcontroller stores its program in an internal EPROM.
  • NEC 02716, 16 KBit EPROM
    NEC 02716, 16 KBit EPROM
  • Piggyback microcontroller from MOSTEK with attached EPROM
    Piggyback microcontroller from MOSTEK with attached EPROM

See also

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Notes

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References

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Bibliography

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

EPROM

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EPROM, or erasable programmable , is a type of that retains its data without power and can be programmed multiple times by applying to store information, followed by erasure using ultraviolet light through a built-in window. Invented by Dov Frohman at in 1971, it emerged from observations during quality control testing of SRAM chips, where trapped electrons in layers suggested a mechanism for non-volatile storage that could be cleared with UV exposure. The first commercial EPROM, 's 1702 chip, stored 2048 bits (256 bytes) and was announced that year, marking a shift from one-time programmable ROMs to reusable alternatives that accelerated prototyping in early development. At its core, EPROM operates using floating-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), where programming traps electrons on an isolated gate to represent data bits, altering the transistor's for reading; erasure via intense UV (typically 253.7 nm ) for 10-20 minutes dissipates this charge across the entire chip, resetting it to a blank state. Unlike later electrically erasable variants, EPROM requires physical removal from the circuit and exposure in an erasure unit, limiting its use to bulk reprogramming rather than selective byte-level changes, with typically lasting 10 to 20 years under normal conditions and unlimited read cycles. This design provided key advantages in the 1970s and 1980s, including cost-effectiveness for low-volume production and storage in embedded systems, as it avoided the need for custom mask sets in ROM fabrication. EPROM played a pivotal role in the microprocessor era by enabling engineers to iterate designs rapidly—reducing prototyping time from weeks to hours—fueling the growth of 's business alongside products like the 8080 processor and supporting applications in calculators, peripherals, and early personal computers. By the late , it inspired refinements such as (electrically erasable PROM), invented at in 1978, which eliminated the UV step but introduced wear limits from electrical stress. Though largely supplanted by in the 1990s for its block-level erasure and higher density, EPROM's legacy endures in understanding evolution and remains relevant in niche legacy systems or educational contexts.

Overview

Definition and Principles

Erasable Programmable Read-Only Memory (EPROM) is a type of non-volatile that retains stored data without an external and can be programmed electrically while being erased through exposure to (UV) light. It was invented by Dov Frohman-Bentchkowsky at in 1971. Unlike mask ROM, which is permanently programmed during the manufacturing process using photolithographic masks to define fixed connections, EPROM enables field programmability, allowing users to erase and reprogram the device multiple times in practical settings. At its core, EPROM operates using an array of floating-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), where each memory cell consists of a single transistor with an isolated polysilicon floating gate embedded within the gate oxide layer. Binary data is represented by the presence or absence of trapped electrons on the floating gate: an unprogrammed cell (logical '1') has few trapped electrons, resulting in a low threshold voltage that permits channel conduction under normal read conditions, while a programmed cell (logical '0') has electrons injected onto the floating gate, raising the threshold voltage and blocking conduction. Programming injects these electrons via channel hot-electron injection, where high voltages applied to the gate and drain accelerate electrons from the channel into the floating gate, typically taking several hundred milliseconds per byte. Data stability is maintained by the thick gate oxide layer (approximately 100-200 nm), which electrically isolates the floating gate and minimizes charge leakage through quantum tunneling, enabling retention times of 10 years or more under normal conditions. The fundamental principle governing data storage in EPROM is the shift in the transistor's threshold voltage due to the stored charge on the floating gate. This shift, denoted as ΔVth\Delta V_{th}, is given by the equation ΔVth=−QstoredCox,\Delta V_{th} = -\frac{Q_{stored}}{C_{ox}}, where QstoredQ_{stored} is the charge trapped on the floating gate (negative for electrons) and CoxC_{ox} is the capacitance of the gate oxide layer. To derive this, consider the floating gate as a capacitive node coupled to the control gate and channel; the trapped charge QstoredQ_{stored} induces an offset voltage across the oxide, which adds to the base threshold voltage VTOV_{TO} of the transistor, effectively shifting the voltage required to invert the channel by ΔVth\Delta V_{th} (with the sign convention yielding a positive shift for electron injection). For typical EPROM devices, this results in a shift from about 1 V (erased) to 8 V (programmed), distinguishing the logical states during readout. In contrast to later variants like EEPROM, which employ thin oxides for electrical erasure via Fowler-Nordheim tunneling, EPROM relies on UV-induced photoemission for charge removal, necessitating physical exposure through a quartz window.

Historical Development

The EPROM was developed at Corporation in the early 1970s amid the growing need for flexible memory solutions in microprocessor-based systems. In 1971, engineer Dov Frohman-Bentchkowsky invented the technology while investigating charge trapping issues in the Intel 1101 (SRAM) during quality control tests. He recognized that electrons trapped in the layer could provide non-volatile storage and proposed using light to erase the charge, leading to the floating-gate design. That same year, announced the first commercial EPROM, the , a 2048-bit (256-byte) device demonstrated at the International Solid-State Circuits Conference (ISSCC). The marked a significant advancement over one-time programmable PROMs and mask ROMs, enabling engineers to iterate and logic designs rapidly without costly mask changes, which typically took weeks. This reusability accelerated the prototyping of early microprocessors like the and 8080, contributing to the explosive growth of the semiconductor industry in the 1970s. Subsequent generations increased capacities and densities, with the technology remaining a cornerstone until the rise of electrically erasable variants in the late 1970s.

Operation

Programming Mechanism

The programming of an EPROM involves channel hot electron (CHE) injection to trap negative charge on the floating gate of individual memory transistors, thereby altering their to represent stored data. To initiate programming for a specific bit, a —typically ranging from 12 to 25 V depending on the device—is applied to the control gate, while the drain is biased at approximately 6 to 7 V, and the source and substrate are grounded. This configuration generates a high lateral in the channel near the drain junction, causing electrons in the channel current to accelerate and gain exceeding 3.1 eV, the barrier height at the silicon-silicon dioxide interface. A fraction (about 10^{-3} to 10^{-4}) of these "hot" electrons then inject perpendicularly into the floating gate, where they are permanently trapped by the surrounding insulating oxide layers, increasing the transistor's from around 2-3 V (erased state, logic 1) to over 5-7 V (programmed state, logic 0). The process requires applying voltage pulses of 1 to 10 ms duration per bit, often repeated up to 25 times if verification shows insufficient charge injection. EPROM chips are programmed using dedicated external devices known as EPROM programmers, which incorporate zero-insertion-force (ZIF) sockets to securely hold the chip without pin damage. These programmers sequentially each memory location via the chip's and pins, applying the precise high-voltage to the appropriate control lines (e.g., V_PP for programming voltage) while maintaining standard supply voltage (V_CC) at 5-6.25 V during verification. Following each , the programmer performs a read-verify cycle at low voltage to measure the cell's threshold shift and confirm , iterating as needed until the programmed state is achieved or a maximum retry limit (e.g., 10-25 attempts) is exceeded to prevent overstress. This byte-oriented or word-oriented ensures reliable writing across the entire array, though total programming time can span seconds to minutes for larger capacities. The injected electrons remain trapped on the floating gate until ultraviolet erasure, rendering the programmed non-volatile and stable for 10-20 years or more under normal conditions. However, excessive programming pulses can induce risks such as localized degradation or trap generation due to sustained high and hot carrier stress, potentially leading to increased leakage currents, reduced , or diminished erase uniformity in subsequent cycles. Programmers mitigate this through built-in limits on pulse counts and verification thresholds.

Erasure and Reading Processes

The erasure of an EPROM is achieved by exposing the chip to (UV) light at a of 253.7 nm through its transparent window, which allows the light to reach the die. This process generates photoelectrons within the floating gate structure, effectively neutralizing the trapped charge and resetting all bits to the erased state, typically logic "1". The required integrated UV dose is approximately 15 watt-seconds per square centimeter, which corresponds to an exposure time of 15 to 20 minutes under a standard UV source with an intensity of 12,000 to 15,000 µW/cm² positioned about 1 inch from the chip. Erasure affects the entire memory array simultaneously, with no capability for selective bit or byte-level erasure. During normal operation, reading data from an EPROM occurs at standard TTL-compatible voltages using a single 5 V (VCC = 5 V ±10%), with no high voltages required as in programming. The process relies on sense amplifiers to detect the of each floating-gate : an uncharged gate (erased "1") results in a low (around 2-3 V), allowing the to conduct and produce a logic high output, while a charged gate (programmed "0") raises the threshold (over 5-7 V), preventing conduction and yielding a logic low. Access times for reading typically range from 200 to 350 ns, enabling rapid data retrieval suitable for systems. A key aspect of the reading process is the read cycle, which begins with address decoding to select the target location via row and column lines: the row decoder activates the appropriate word line to gate the , while the column decoder enables the bit lines for the desired outputs. Once chip enable (CE) and output enable (OE) signals go low with stable addresses, the sense amplifiers are clocked to detect and amplify the currents, buffering the logic levels for output after a delay of 60 to 120 ns from OE assertion or 200 to 350 ns from address setup. This sequence ensures non-destructive readout, preserving the stored charge on the floating gates. Erasure limitations include the need to remove any protective labels and expose the quartz window directly, which risks contamination from dust or handling if not performed in a clean environment, potentially affecting subsequent programming reliability. Additionally, partial or under-erasure is ineffective and can lead to misleading verification results, as incompletely neutralized charges may pass basic tests but cause data errors in operation, necessitating full exposure for consistent results.

Design and Construction

Physical Structure

The physical structure of an EPROM chip is characterized by its internal architecture, which features a dense of floating-gate metal-oxide-semiconductor (MOS) transistors arranged in a grid-like NOR configuration. Each cell comprises a single floating-gate , where the floating gate— a polysilicon layer isolated from the channel—is surrounded by a thick layer, typically 30-35 nm (300-350 Å) in thickness, to promote stable charge retention over extended periods by minimizing electron tunneling. The control gates of these transistors connect to word lines (row address lines), enabling row-wise selection, while the drains link to bit lines (column address lines) for handling, with source regions often shared among cells in the to optimize space. This layout supports the non-volatile storage essential to EPROM functionality. Externally, EPROM chips are housed in dual in-line packages (DIP), either for durability or for cost-effectiveness, with a prominent transparent window centered over the die to allow (UV) light penetration for bulk erasure. Standard pinouts vary by capacity; for instance, larger chips like 64 Kbit devices commonly use a 28-pin DIP format, allocating pins for Vcc (power), Vpp (programming voltage), address inputs (A0-A15), data I/O (D0-D7), output enable (OE), and chip enable (CE). The window, measuring approximately 5-10 mm in , is sealed with a removable UV-opaque label to block and prevent unintended erasure, and many designs include a thin overlay on the for diffused protection against direct handling damage. The evolution of EPROM die sizes reflects broader scaling trends, with early 1970s models like the 1702 employing an 8 µm process node, yielding die areas on the order of several square millimeters due to metal-gate NMOS technology. By the 1990s, advancements reduced process nodes to approximately 1 µm using self-aligned polysilicon gates, shrinking die areas dramatically—often to under 1 mm² for multi-megabit capacities—while preserving the quartz-windowed package form factor for compatibility.

Materials and Manufacturing

EPROM fabrication relies on established materials to enable charge storage and UV erasability. The primary substrate is p-type (100)-oriented with a resistivity of 5-50 ohm-cm, providing the base for MOS transistor structures. (SiO₂) serves as the (typically 300-350 Å thick) and field oxide (0.8-1.2 μm thick), acting as an insulator between the substrate and gates while supporting charge trapping. forms the floating gate (2000-2600 Å thick) and control gate (4000-5000 Å thick), doped for conductivity to facilitate tunneling during programming. Aluminum, alloyed with 0.8-1.2% and 0.6-1.2 μm thick, provides interconnections for signal routing. The package incorporates a window, transparent to UV wavelengths below 400 nm, allowing erasure without disassembly. The manufacturing process follows CMOS N-well technology for modern devices, beginning with wafer preparation and to define N-wells and active areas. dopes the substrate— for p-type regions (1-4×10¹³/cm² at 25-50 keV) and for n-type (4-6×10¹⁵/cm² at 70-100 keV)—forming the channels and junctions. grows the , followed by low-pressure (LPCVD) of the first layer for the floating gate, which is patterned via . The inter-poly oxide (400-600 Å) and second poly layer are then deposited and defined, with additional implants for source/drain regions. Metal layers are sputtered and patterned using , followed by passivation with phosphosilicate glass (PSG) and oxynitride. Wafers are backgrinded to 500-600 μm, tested, singulated into dies, wire-bonded to leads, and encapsulated in or housings with the window. Early EPROMs, such as the Intel 1701, employed NMOS processes for simplicity, but production shifted to in later generations to achieve lower power dissipation and higher density. Reliability hinges on oxide integrity, verified through electrical testing to ensure minimal leakage and support exceeding 10 years at standard temperatures. The gate oxide's thickness and quality prevent charge loss, while manufacturing controls like defect screening maintain for hundreds of program/erase cycles. Erasure requires precise UV dosage control, typically 15 W-s/cm² at 253.7 nm wavelength, to fully discharge floating gates without inducing oxide damage or shifts. Overexposure risks degrading the SiO₂ layers, reducing long-term retention.

Variants and Evolution

Generations and Capacity Progression

The evolution of EPROM technology closely paralleled advancements in semiconductor manufacturing, with capacity densities increasing exponentially in line with principles, roughly doubling every 18-24 months through reductions in cell size and process node scaling. The initial commercial EPROM, Intel's introduced in 1971, offered 2048 bits (256 × 8 organization) using PMOS technology on a process exceeding 10 µm, marking the shift from one-time programmable ROMs to erasable variants. By 1974, the Intel 2708 improved to 8,192 bits (1,024 × 8) with NMOS fabrication on an approximately 8 µm process, enabling byte-wide data access suited for emerging 8-bit microcomputers and facilitating faster prototyping in systems like early personal computers. From 1977 to 1980, capacities progressed to 16 Kbits with devices like the TMS2716 (2,048 × 8), fabricated on 6-8 µm processes, as improvements allowed denser floating-gate cell packing without altering the core UV-erasable . This era saw the transition from word-oriented to predominantly byte-wide configurations, enhancing compatibility with buses and broadening adoption in embedded applications. In the early , standardized pinouts for the 27xxx EPROM series in 28-pin DIP packages, promoting interoperability across manufacturers and accelerating market growth by standardizing packages for densities up to 256 Kbits. The 1980s brought further scaling, with 64 Kbit devices like the 2764 (8,192 × 8) on 2-3 µm processes by mid-decade, followed by 1 Mbit capacities in the late 1980s, exemplified by the AT27C010 (131,072 × 8) using on 1-1.5 µm nodes, which reduced power consumption and improved reliability. Cell size reductions, driven by finer and optimized floating-gate geometries, were primary enablers, shrinking from over 100 µm² in early devices to under 10 µm² by the decade's end. Experimental efforts explored storage to boost density beyond binary states, though these remained limited in production EPROMs due to programming complexity. Entering the 1990s, EPROM densities reached 4-16 Mbits, as in NEC's 16 Mbit device on a 0.6 µm process in 1990, benefiting from sub-micron scaling that quadrupled effective capacity per die area compared to counterparts. Mainstream production waned around 2000, supplanted by electrically erasable for its superior reprogrammability and cost-efficiency at higher densities, though EPROMs persisted in niche UV-erasable roles. Overall, capacities advanced from 2 Kbits to peaks near 32 Mbits, underscoring a of sustained innovation until flash dominance.
Year RangeRepresentative DeviceCapacity (bits)Approximate Process NodeKey Advancement
1971-19742K to 8K>8 µm (PMOS/NMOS)Introduction of erasable floating-gate cells; byte-wide access
1977-1980TI TMS271616K6-8 µmDenser NMOS integration for prototyping
1980s64K to 1M2-1 µm ()JEDEC pinout ; power-efficient scaling
1990s4M to 16M1-0.6 µmSub-micron nodes enabling multi-megabit densities

Types and Specialized Forms

EPROMs are primarily categorized into ultraviolet (UV)-erasable variants and one-time programmable (OTP) forms, with the former featuring a quartz window in ceramic packaging to allow erasure via UV exposure, while the latter omits this window for cost efficiency and permanent programming. The standard UV-erasable EPROM, exemplified by the 27C series from manufacturers like AMD and Intel, supports repeated reprogramming after erasure with ultraviolet light at a dosage of approximately 15 W-seconds/cm², making it suitable for development and prototyping where flexibility is needed. In contrast, OTP EPROMs, also based on the same floating-gate architecture, are housed in opaque plastic packages without the erasure window, rendering them non-erasable after programming and ideal for high-volume production to reduce manufacturing costs by 20-30% compared to windowed versions. Specialized forms of EPROM include windowless variants optimized for embedded applications, where the absence of the window prevents accidental erasure and enhances reliability in sealed environments, such as in automotive or modules. Multi-chip modules incorporating EPROM dies alongside other components, like logic or RAM, emerged in the late for compact system-on-package designs, though they remained less common due to the dominance of single-chip solutions. Early experimental bipolar PROMs, developed prior to widespread MOS adoption around 1975, utilized fuse-based programming but were rare and quickly supplanted by more efficient MOS floating-gate technology. Packaging variants of EPROMs evolved to support diverse mounting and density needs, with the (DIP) serving as the foundational through-hole option in 28- to 48-pin configurations for prototyping and legacy systems. Surface-mount alternatives like the plastic leaded chip carrier (PLCC) in 32- and 44-pin formats offered easier automated assembly, while thin small-outline packages (TSOP) in 32-pin versions enabled higher board densities in portable devices by reducing footprint by up to 50% compared to DIP. Pin-compatible families, such as the 27xxx series (e.g., 2716 to 27C080), maintained consistent 24- or 32-pin footprints across capacities from 2K to 1M bits, facilitating straightforward upgrades without circuit redesign. In the , OTP EPROMs captured a significant portion of the market in consumer devices for small to medium production runs, often comprising over 40% of shipments in embedded applications like remote controls and appliances, due to their balance of reprogrammability during testing and permanence in final products. Unlike UV-erasable EPROMs, OTP variants lack any erasure mechanism, relying solely on high-voltage programming pulses to set floating gates irreversibly, which simplified supply chains but limited post-deployment modifications.

Applications and Legacy

Primary Uses

EPROMs found widespread application in firmware storage for early personal computers during the 1980s and 1990s, particularly as chips in systems like the PC, where the system board supported socketed 8K x 8 EPROM modules to hold essential code for , I/O drivers, and bootstrap loaders. These chips enabled developers to program and update low-level system software without requiring permanent mask ROMs, facilitating prototyping and revisions in the nascent PC market. In embedded systems, such as household appliances and industrial controllers from the same era, EPROMs stored code for tasks like device initialization and control logic, leveraging their non-volatile nature to retain programming across power cycles. In niche modern contexts, EPROMs persist in legacy industrial controls where compatibility with older equipment demands their radiation-tolerant properties, as demonstrated by studies showing EPROMs exhibiting superior hardness against total ionizing dose compared to some variants. They also continue in other radiation-exposed environments, such as , due to reversible radiation effects after erasure and . Among hobbyists, EPROMs are used for vintage hardware or custom projects. Prototyping remains a key role, allowing engineers to test in socketed configurations before committing to production. EPROMs were often integrated as socketed components in systems for field updates, permitting on-site erasure via UV exposure and reprogramming without full hardware replacement, and frequently paired with RAM for hybrid memory architectures in resource-constrained designs. Throughout the 1980s, EPROMs were prominent in 8-bit microcomputers, with home systems like the Commodore 64 using socketed ROMs that could be replaced with EPROMs for customization, enabling flexible storage up to 128K densities. By the 2000s, however, EPROMs were largely supplanted by flash memory in consumer devices due to the latter's electrical erasability and higher densities, marking the end of their prevalence in mainstream electronics.

Advantages, Limitations, and Comparisons

EPROMs provide high reliability due to their non-volatile nature, with times typically ranging from 10 to 20 years under standard operating conditions, making them suitable for long-term storage applications. They are also cost-effective for low-volume production, as they eliminate the need for expensive mask sets required in mask ROM fabrication, allowing flexible updates without significant upfront investment. Compared to mask ROM, EPROMs offer simple through electrical programming followed by UV erasure, enabling iterative development and prototyping at reduced costs. Despite these strengths, EPROMs have notable limitations, including bulky packaging due to the required window for UV exposure, which increases size and cost relative to windowless alternatives. The manual UV erasure process is time-consuming, often requiring 10 to 20 minutes of exposure to , and necessitates specialized equipment, preventing in-system reprogramming. Additionally, the window is sensitive to damage , fingerprints, or scratches, which can block UV and render the device unerasing. Programming cycles are limited to approximately 100-1000 due to cumulative stress on the , beyond which reliability degrades, though UV erasure cycles are effectively unlimited. During read operations, power consumption ranges from 50 to 100 mW, which is higher than some modern non-volatile memories. In comparisons, EPROMs surpass PROMs by allowing reprogramming via UV erasure, whereas PROMs are one-time programmable only, offering greater flexibility for design changes. Relative to EEPROMs, EPROMs are less expensive and achieve higher densities at similar technology nodes but require external UV erasure instead of electrical byte-level erasing, making EEPROMs preferable for frequent, in-system updates despite their higher cost per bit. Against , EPROMs lack block-level electrical erasure and in-system programmability, with flash enabling faster erasure (<1 second) and more cycles (>10^6), contributing to EPROM's obsolescence by the as density and cost curves favored flash for higher volumes.

References

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