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Skylake (microarchitecture)
Skylake (microarchitecture)
Skylake (microarchitecture)
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Skylake
Intel Core i7-6700K with four physical cores
General information
LaunchedAugust 5, 2015; 10 years ago (2015-08-05)
DiscontinuedMarch 4, 2019; 6 years ago (2019-03-04) (desktop processors)
Marketed byIntel
Designed byIntel
Common manufacturer
  • Intel
CPUID code0406e3h, 0506e3h
Product code
  • 80662 (mainstream and mobile Xeon E3)
  • 80673 (enthusiast and server)
Performance
Max. CPU clock rateUp to 5.0 GHz
Cache
L1 cache64 KB per core (32 KB instructions + 32 KB data)
L2 cache256 KB per core
(1 MB per core for Skylake-X, SP, and W)
L3 cacheUp to 38.5 MB shared
L4 cache128 MB of eDRAM (on Iris Pro models)
Architecture and classification
Technology node14 nm bulk silicon 3D transistors (Tri-Gate)
MicroarchitectureSkylake
Instruction setx86-16, IA-32, x86-64
Extensions
Physical specifications
Cores
  • 2–28
Sockets
Products, models, variants
Product code name
  • SKL
Brand name
    • Core i3
    • Core i5
    • Core i7
    • Core i9
    • Core X-Series
    • Core m3
    • Core m5
    • Core m7
    • Xeon
    • Celeron
    • Pentium
History
PredecessorBroadwell (tick/process)
Successors
  • Kaby Lake (optimization, desktop, laptop, low-end server, and mobile workstation)
  • Cascade Lake (HEDT, workstation, and mid- to high-end server)
  • Palm Cove (process)
Support status
Client: Unsupported as of December 30, 2022 for iGPU
Xeon E3 v5: Unsupported as of December 30, 2022 for iGPU
Other Xeon: supported

Skylake[6][7] is Intel's codename for its sixth generation Core microprocessor family that was launched on August 5, 2015,[8] succeeding the Broadwell microarchitecture.[9] Skylake is a microarchitecture redesign using the same 14 nm manufacturing process technology[10] as its predecessor, serving as a tock in Intel's tick–tock manufacturing and design model. According to Intel, the redesign brings greater CPU and GPU performance and reduced power consumption. Skylake CPUs share their microarchitecture with Kaby Lake, Coffee Lake, Whiskey Lake, and Comet Lake CPUs.

Skylake is the last Intel platform on which Windows earlier than Windows 10 are officially supported by Microsoft,[11] although enthusiast-created modifications are available that disabled the Windows Update check and allowed Windows 8.1 and earlier to continue to receive Windows Updates on this and later platforms.[12][13][14]

Some of the processors based on the Skylake microarchitecture are marketed as sixth-generation Core.[15][16][17]

Intel officially declared end of life and discontinued Skylake LGA 1151 CPUs (except i3-6100, i5-6500, and Xeon E3 v5) on March 4, 2019.[18]

Development history

[edit]

Skylake's development, as with previous processors such as Banias, Dothan, Conroe, Sandy Bridge, and Ivy Bridge, was primarily undertaken by Intel Israel at its engineering research center in Haifa, Israel.[19] The final design was largely an evolution of Haswell, with minor improvements to performance and several power-saving features being added.[20] A major priority of Skylake's design was to design a microarchitecture for envelopes as low as 4.5W to embed within tablet computers and notebooks in addition to higher-power desktop computers and servers.[21]

In September 2014, Intel announced the Skylake microarchitecture at the Intel Developer Forum in San Francisco, and that volume shipments of Skylake CPUs were scheduled for the second half of 2015. The Skylake development platform was announced to be available in Q1 2015. During the announcement, Intel also demonstrated two computers with desktop and mobile Skylake prototypes: the first was a desktop testbed system, running the latest version of 3DMark, while the second computer was a fully functional laptop, playing 4K video.[22]

An initial batch of Skylake CPU models (i5-6600K and i7-6700K) was announced for immediate availability during the Gamescom on August 5, 2015,[23] unusually soon after the release of its predecessor, Broadwell, which had suffered from launch delays.[24] Intel acknowledged in 2014 that moving from 22 nm (Haswell) to 14 nm (Broadwell) had been its most difficult process to develop yet, causing Broadwell's planned launch to slip by several months;[25] yet, the 14 nm production was back on track and in full production as of Q3 2014.[26] Industry observers had initially believed that the issues affecting Broadwell would also cause Skylake to slip to 2016, but Intel was able to bring forward Skylake's release and shorten Broadwell's release cycle instead.[27][28] As a result, the Broadwell architecture had an unusually short run.[27]

Overclocking of unsupported processors

[edit]

Officially Intel supported overclocking of only the K and X versions of Skylake processors. However, it was later discovered that other non-K chips could be overclocked by modifying the base clock value – a process made feasible by the base clock applying only to the CPU, RAM, and integrated graphics on Skylake. Through beta UEFI firmware updates, some motherboard vendors, such as ASRock (which prominently promoted it under the name Sky OC) allowed the base clock to be modified in this manner.[29][30]

When overclocking unsupported processors using these UEFI firmware updates, several issues arise:

  • C-states are disabled, therefore the CPU will constantly run at its highest frequency and voltage
  • Turbo-boost is disabled
  • Integrated graphics are disabled
  • AVX2 instruction performance is poor, approximately 4-5 times slower due to the upper 128-bit half of the execution units and data buses not being taken out of their power saving states
  • CPU core temperature readings are incorrect

These issues are partly caused by the power management of the processor needing to be disabled for base clock overclocking to work.[31]

In February 2016, however, an ASRock firmware update removed the feature. On February 9, 2016, Intel announced that it would no longer allow such overclocking of non-K processors, and that it had issued a CPU microcode update that removes the function.[32][33][34] In April 2016, ASRock started selling motherboards that allow overclocking of unsupported CPUs using an external clock generator.[35][36]

Operating system support

[edit]

In January 2016, Microsoft announced that it would end support of Windows 7 and Windows 8.1 on Skylake processors effective July 17, 2017; after this date, only the most critical updates for the two operating systems would be released for Skylake users if they have been judged not to affect the reliability of the OS on older hardware (until July 31, 2019; August 2019 critical update requires at least Windows 10), and Windows 10 would be the only Microsoft Windows platform officially supported on Skylake and on later Intel CPU microarchitectures beginning with Skylake's successor Kaby Lake. Terry Myerson stated that Microsoft had to make a large investment in order to reliably support Skylake on older versions of Windows, and that future generations of processors would require further investments. Microsoft also stated that due to the age of the platform, it would be challenging for newer hardware, firmware, and device driver combinations to properly run under Windows 7.[37][38]

On March 18, 2016, in response to criticism over the move, primarily from enterprise customers, Microsoft announced revisions to the support policy, changing the cutoff for support and non-critical updates to July 17, 2018, and stating that Skylake users would receive all critical security updates for Windows 7 and 8.1 through the end of extended support.[39][40] In August 2016, citing "a strong partnership with our OEM partners and Intel", Microsoft stated that it would continue to fully support 7 and 8.1 on Skylake through the end of their respective lifecycles.[41][42] In addition, an enthusiast-created modification was released that disabled the Windows Update check and allowed Windows 8.1 and earlier to continue to be updated on this and later platforms.[43]

As of Linux kernel 4.10, Skylake mobile power management is supported with most Package C states supported seeing some use. Linux 4.11 enables Frame-Buffer Compression for the integrated graphics chipset by default, which lowers power consumption.[44]

Skylake is fully supported on OpenBSD 6.2 and later, including accelerated graphics.[45]

For Windows 11, only the high-end Skylake-X processors are officially listed as compatible.[46] All other Skylake processors are not officially supported due to security concerns.[47] However, it is still possible to manually upgrade using an ISO image (as Windows 10 users on those processors will not be offered to upgrade to Windows 11 via Windows Update), or perform a clean installation as long as the system has Trusted Platform Module (TPM) 2.0 enabled,[48] but the user must accept that they will not be entitled to receive updates, and that damage caused by using Windows 11 on an unsupported configuration are not covered by the manufacturer's warranty.[49][50]

Features

[edit]
Skylake i7-6700K
Skylake i7-6700K: bottom view

Like its predecessor, Broadwell, Skylake is available in five variants, identified by the suffixes S (SKL-S), X (SKL-X), H (SKL-H), U (SKL-U), and Y (SKL-Y). SKL-S and SKL-X contain overclockable K and X variants with unlocked multipliers.[51] The H, U and Y variants are manufactured in ball grid array (BGA) packaging, while the S and X variants are manufactured in land grid array (LGA) packaging using a new socket, LGA 1151 (LGA 2066 for Skylake X).[52] Skylake is used in conjunction with Intel 100 Series chipsets, also known as Sunrise Point.[53]

The major changes between the Haswell and Skylake architectures include the removal of the fully integrated voltage regulator (FIVR) introduced with Haswell.[54] On the variants that will use a discrete Platform Controller Hub (PCH), Direct Media Interface (DMI) 2.0 is replaced by DMI 3.0, which allows speeds of up to 8 GT/s.

Skylake's U and Y variants support one DIMM slot per channel, while H and S variants support two DIMM slots per channel.[52] Skylake's launch and sales lifespan occur at the same time as the ongoing SDRAM market transition, with DDR3 SDRAM memory gradually being replaced by DDR4 SDRAM. Rather than working exclusively with DDR4, the Skylake microarchitecture remains backward compatible by interoperating with both types of memory. Accompanying the microarchitecture's support for both memory standards, a new SO-DIMM type capable of carrying either DDR3 or DDR4 memory chips, called UniDIMM, was also announced.[55]

Skylake's few P variants have a reduced on-die graphics unit (12 execution units enabled instead of 24 execution units) over their direct counterparts; see the table below. In contrast, with Ivy Bridge CPUs the P suffix was used for CPUs with completely disabled on-die video chipset.

Other enhancements include Thunderbolt 3.0, Serial ATA Express, Iris Pro graphics with Direct3D feature level 12_1 with up to 128 MB of L4 eDRAM cache on certain SKUs.[56] The Skylake line of processors retires VGA support,[57] while supporting up to three monitors connected via HDMI 1.4, DisplayPort 1.2 or Embedded DisplayPort (eDP) interfaces.[58] HDMI 2.0 (4K@60 Hz) is only supported on motherboards equipped with Intel's Alpine Ridge Thunderbolt controller.[59]

The Skylake instruction set changes include Intel MPX (Memory Protection Extensions) and Intel SGX (Software Guard Extensions). Future Xeon variants will also have Advanced Vector Extensions 3.2 (AVX-512F).[3][4]

Skylake-based laptops were predicted to use wireless technology called Rezence for charging, and other wireless technologies for communication with peripherals. Many major PC vendors agreed to use this technology in Skylake-based laptops; however, no laptops were released with the technology as of 2019.[60][61]

The integrated GPU of Skylake's S variant supports on Windows DirectX 12 Feature Level 12_1, OpenGL 4.6 with latest Windows 10 driver update[62] (OpenGL 4.5 on Linux[63]) and OpenCL 3.0 standards. The Quick Sync video engine now includes support for VP9 (GPU accelerated decode only), VP8 and HEVC (hardware accelerated 8-bit encode/decode and GPU accelerated 10-bit decode), and supports for resolutions up to 4096 × 2048.[64][65][66]

Intel also released unlocked (capable of overclocking) mobile Skylake CPUs.[67]

Unlike previous generations, Skylake-based Xeon E3 no longer works with a desktop chipset that supports the same socket, and requires either the C232 or the C236 chipset to operate.

Started from Skylake, Intel had removed IDE mode (of SATA controller) and EHCI controller from its client platform chipsets.

Known issues

[edit]

Short loops with a specific combination of instruction use may cause unpredictable system behavior on CPUs with hyperthreading. A microcode update was issued to fix the issue.[68]

Skylake is vulnerable to Spectre attacks.[69] In fact, it is more vulnerable than other processors because it uses indirect branch speculation not just on indirect branches but also when the return prediction stack underflows.

The latency for the spinlock PAUSE instruction has been increased dramatically (from the usual 10 cycles to 141 cycles in Skylake), which can cause performance issues with older programs or libraries using pause instructions.[70] Intel documents the increased latency as a feature that improves power efficiency.[71]

Architecture changes compared to Broadwell microarchitecture

[edit]

CPU

[edit]

GPU

[edit]

I/O

[edit]

Other

[edit]

Configurations

[edit]

Skylake processors are produced in seven main families: Y, U, H, S, X, W, and SP. Multiple configurations are available within each family:[52]

Feature Family
 Y   U   H   T   S   R   X   W   SP 
Max cores 2 4 18 28
Integrated L4 cache (eDRAM) • • •
Low-power mobile/embedded systems • • • •
Socket BGA LGA 1151 LGA 2066 LGA 3647
LPDDR3 SDRAM • • •
DDR3L SDRAM • • • • • •
DDR4 SDRAM • • • • • • •
128 GB to 1.5 TB of physical RAM • • •+
28 to 44 PCIe 3.0 lanes • • •

List of Skylake processor models

[edit]

Mainstream desktop processors

[edit]
Core i7-6700 die shot

Common features of the mainstream desktop Skylake CPUs:

  • DMI 3.0 and PCIe 3.0 interfaces
  • Dual-channel memory support in the following configurations: DDR3L-1600 1.35 V (32 GB maximum) or DDR4-2133 1.2 V (64 GB maximum). DDR3 is unofficially supported through some motherboard vendors[96][97][98]
  • 16 PCIe 3.0 lanes
  • The Core-branded processors support the AVX2 instruction set. The Celeron and Pentium-branded ones support only SSE4.1/4.2
  • 350 MHz base graphics clock rate
Processor
branding
and model 		Cores
(threads) 		Clock rate (GHz) GPU Cache TDP Socket Release
date 		Release
price
(USD)
Base Turbo Boost 2.0 Model EUs Max
freq.
(GHz) 		L2 L3 L4
(eDRAM)
1 2 [citation needed] 4 [citation needed]

Core i7 6700K 4 (8) 4.0 4.2 4.0 4.0 HD 530 24 1.15[99] 1 MB 8 MB — 91 W LGA 1151 August 5, 2015 $339
6785R 3.3 3.9 3.8 3.5 Iris Pro 580 72 128 MB 65 W BGA 1440 May 3, 2016 $370
6700 3.4 4.0 3.9 3.7 HD 530 24 — LGA 1151 September 1, 2015 $303
6700T 2.8 3.6 3.5 3.4 35 W $303
Core i5 6600K 4 (4) 3.5 3.9 3.8 3.6 6 MB 91 W August 5, 2015 $242
6685R 3.2 3.8 3.7 3.3 Iris Pro 580 72 128 MB 65 W BGA 1440 May 3, 2016 $288
6600 3.3 3.9 3.8 3.6 HD 530 24 — LGA 1151 September 1, 2015 $213
6585R 2.8 3.6 3.5 3.1 Iris Pro 580 72 1.1 128 MB BGA 1440 May 3, 2016 $255
6500 3.2 3.3 HD 530 24 1.05 — LGA 1151 September 1, 2015 $192
6600T 2.7 3.5 3.4 3.3 1.1 35 W Q3 2015 $213
6500T 2.5 3.1 3.0 2.8 $192
6402P 2.8 3.4 3.4 3.2 HD 510 12 0.95 65 W December 27, 2015 $182
6400T 2.2 2.8 2.7 2.5 HD 530 24 35 W Q3 2015
6400 2.7 3.3 3.3 3.1 65 W August 5, 2015
Core i3 6320 2 (4) 3.9 — 1.15 512 KB 4 MB 51 W Q3 2015 $149
6300 3.8 $138
6100 3.7 1.05 3 MB October 2015 $117
6300T 3.3 0.95 4 MB 35 W $138
6100T 3.2 3 MB $117
6098P 3.6 HD 510 12 1.050 54 W December 27, 2015
Pentium G4520 2 (2) 3.6 HD 530 24 51 W October 2015 $86
G4500 3.5 $75
G4500T 3.0 0.95 35 W Q3 2015
G4400 3.3 HD 510 12 1.0 54 W October 2015 $64
G4400T 2.9 0.95 35 W Q3 2015
G4400TE 2.4 Q4 2015 $70
Celeron G3920 2.9 2 MB 51 W $52
G3900 2.8 $42
G3900TE 2.3 35 W
G3900T 2.6

High-end desktop processors (Skylake-X)

[edit]

Common features of the high-performance Skylake-X CPUs:

  • In addition to the AVX2 instruction set, they also support the AVX-512 instructions
  • No built-in iGPU (integrated graphics processor)
  • Turbo Boost Max Technology 3.0 for up to two/four threads workloads for CPUs that have eight cores and more (7820X, 7900X, 7920X, 7940X, 7960X, 7980XE, and all ninth generation chips)[100]
  • A different cache hierarchy (when compared to client Skylake CPUs or previous architectures)
Core i7-7820X die shot
Seventh-generation Skylake-X high-end desktop CPUs
Processor
branding
and model 		Cores
(threads) 		Clock rate (GHz) Cache PCIe
lanes 		Memory
support 		Socket TDP Release
date 		Release
price
(USD)
Base Turbo L2 L3
2.0 3.0

Core i9[101] 7980XE 18 (36) 2.6 4.2 4.4 18 MB 24.75 MB 44
PCIe 3.0 		DDR4-2666
quad-channel 		LGA 2066 165 W Sep 25, 2017[102] $1999
7960X 16 (32) 2.8 16 MB 22 MB $1699
7940X 14 (28) 3.1 4.3 14 MB 19.25 MB $1399
7920X 12 (24) 2.9 12 MB 16.5 MB 140 W Aug 28, 2017 $1189
7900X 10 (20) 3.3 4.5 10 MB 13.75 MB Jun 19, 2017 $999
Core i7 7820X 8 (16) 3.6 8 MB 11 MB 28
PCIe 3.0 		$599
7800X 6 (12) 3.5 4.0 — 6 MB 8.25 MB DDR4-2400
quad-channel 		$389
Ninth-generation Skylake-X high-end desktop CPUs
Processor
branding and model 		Cores
(threads) 		Clock rate (GHz) Cache PCIe
lanes 		Memory
support 		Socket TDP Release
date 		Release
price
(USD)
Base Turbo Boost L2 L3
2.0 3.0

Core i9[103] 9990XE[104] 14 (28) 4.0 5.0 5.0 14 MB 19.25 MB 44
PCIe 3.0 		DDR4-2666
quad-channel 		LGA 2066 255 W Jan 3, 2019 OEM
9980XE 18 (36) 3.0 4.4 4.5 18 MB 24.75 MB 165 W Oct 9, 2018[105] $1979
9960X 16 (32) 3.1 16 MB 22 MB $1684
9940X 14 (28) 3.3 14 MB 19.25 MB $1387
9920X 12 (24) 3.5 12 MB $1189
9900X 10 (20) 3.5 10 MB $989
9820X 3.3 4.1 4.2 16.5 MB $889
Core i7 9800X 8 (16) 3.8 4.4 4.5 8 MB $589

Xeon high-end desktop processors (Skylake-X)

[edit]
  • Marketed as a Xeon
  • Uses the C621 chipset
  • Xeon W-3175X was the only Xeon with a multiplier officially unlocked for overclocking until the introduction of Sapphire Rapids-WS Xeon CPUs in 2023.[106]
Model sSpec
number 		Cores
(threads) 		Clock rate Turbo Boost
all-core/2.0
(/max. 3.0) 		L2
cache 		L3
cache 		TDP Socket I/O bus Memory Release date Part
number(s) 		Release
price (USD)
Xeon W-3175X
  • SRF6L (H0)
 28 (56) 3.1 GHz 3.8/4.3 GHz 28 × 1 MB 38.50 MB
255 W
LGA 3647 DMI 3.0 6 × DDR4-2666 January 30, 2019
  • CD8067304237800
  • BX80673W3175X
 $2999

Mobile processors

[edit]

For mobile workstation processors, see Server processors

Processor
branding and
model 		Cores
(threads) 		CPU
clock
rate 		CPU Turbo clock rate GPU GPU clock rate Cache Max.
PCIe
lanes 		TDP cTDP Release date Price
(USD)
Single
core 		Dual
core [citation needed] 		Quad
core [citation needed] 		Base Turbo L3 L4
(eDRAM) 		Up Down

Core i7 6970HQ 4 (8) 2.8 GHz 3.7 GHz ? Iris Pro 580 350 MHz 1050 MHz 8 MB 128 MB 16 45 W — 35 W Q1 2016 $623
6920HQ 2.9 GHz 3.8 GHz 3.6 GHz 3.4 GHz HD 530 — September 1, 2015 $568
6870HQ 2.7 GHz 3.6 GHz ? Iris Pro 580 1000 MHz 128 MB Q1 2016 $434
6820HQ 3.4 GHz 3.2 GHz HD 530 1050 MHz — September 1, 2015 $378
6820HK
6770HQ 2.6 GHz 3.5 GHz ? Iris Pro 580 950 MHz 6 MB 128 MB Q1 2016 $434
6700HQ 3.3 GHz 3.1 GHz HD 530 1050 MHz — September 1, 2015 $378
6660U 2 (4) 2.4 GHz 3.4 GHz 3.2 GHz — Iris 540 300 MHz 4 MB 64 MB 12 15 W 9.5 W Q1 2016 $415
6650U 2.2 GHz Q3 2015
6600U 2.6 GHz — HD 520 — 25 W 7.5 W September 1, 2015 $393
6567U 3.3 GHz 3.6 GHz 3.4 GHz Iris 550 1100 MHz 64 MB 28 W — 23 W Q3 2015 TBD
6560U 2.2 GHz 3.2 GHz 3.1 GHz Iris 540 1050 MHz 15 W 9.5 W
6500U 2.5 GHz 3.1 GHz 3.0 GHz HD 520 — 7.5 W September 1, 2015 $393
Core i5 6440HQ 4 (4) 2.6 GHz 3.5 GHz 3.3 GHz 3.1 GHz HD 530 350 MHz 950 MHz 6 MB 16 45 W 35 W $250
6360U 2 (4) 2.0 GHz 3.1 GHz 2.9 GHz — Iris 540 300 MHz 1000 MHz 4 MB 64 MB 12 15 W 9.5 W Q3 2015 $304
6350HQ 4 (4) 2.3 GHz 3.2 GHz ? Iris Pro 580 350 MHz 900 MHz 6 MB 128 MB 16 45 W 35 W Q1 2016 $306
6300HQ 3.0 GHz 2.8 GHz HD 530 950 MHz — September 1, 2015 $250
6300U 2 (4) 2.4 GHz 3.0 GHz 2.9 GHz — HD 520 300 MHz 1000 MHz 3 MB 12 15 W 7.5 W $281
6287U 3.1 GHz 3.5 GHz 3.3 GHz Iris 550 1100 MHz 4 MB 64 MB 28 W 23 W Q3 2015 $304
6267U 2.9 GHz 3.3 GHz 3.1 GHz 1050 MHz 23 W
6260U 1.8 GHz 2.9 GHz 2.7 GHz Iris 540 950 MHz 15 W 9.5 W $304
6200U 2.3 GHz 2.8 GHz HD 520 1000 MHz 3 MB — 7.5 W September 1, 2015 $281
Core i3 6167U 2.7 GHz — — Iris 550 64 MB 28 W 23 W Q3 2015 $304
6157U 2.4 GHz Q3 2016
6100H 2.7 GHz HD 530 350 MHz 900 MHz — 35 W — September 1, 2015 $225
6100U 2.3 GHz HD 520 300 MHz 1000 MHz 15 W 7.5 W $281
6006U 2.0 GHz 900 MHz — November, 2016 $281
Core m7 6Y75 1.2 GHz 3.1 GHz 2.9 GHz HD 515 300 MHz 1000 MHz 4 MB 10 4.5 W 7 W 3.5 W September 1, 2015 $393
Core m5 6Y57 1.1 GHz 2.8 GHz 2.4 GHz 900 MHz $281
6Y54 2.7 GHz
Core m3 6Y30 0.9 GHz 2.2 GHz 2.0 GHz 850 MHz 3.8 W
Pentium 4405U 2.1 GHz — — HD 510 950 MHz 2 MB 15 W — 10 W Q3 2015 $161
4405Y 1.5 GHz HD 515 800 MHz 6 W 4.5 W
Celeron G3902E 2 (2) 1.6 GHz — HD 510 350 MHz 950 MHz 16 25 W — Q1 2016 $107
G3900E 2.4 GHz 35 W
3955U 2.0 GHz 300 MHz 900 MHz 10 15 W 10 W Q4 2015
3855U 1.6 GHz

Workstation processors

[edit]
Model sSpec
number 		Cores
(threads) 		Clock rate Turbo Boost
all-core/2.0
(/max. 3.0) 		L2
cache 		L3
cache 		TDP Socket I/O bus Memory Release date Part
number(s) 		Release
price (USD)
Xeon W-2195
  • SR3RX (M0)
 18 (36) 2.3 GHz 3.2/4.3 GHz 18 × 1 MB 24.75 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303805901
 $2553
Xeon W-2191B
  • SR3RW (H0)
 18 (36) 2.3 GHz 3.2/4.3 GHz 18 × 1 MB 24.75 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 December 21, 2017 OEM for Apple[107][108]
Xeon W-2175
  • SR3W2 (M0)
 14 (28) 2.5 GHz 3.3/4.3 GHz 14 × 1 MB 19.25 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 October 15, 2017
  • CD8067303842300
 $1947
Xeon W-2170B
  • SR3W3 (H0)
 14 (28) 2.5 GHz 3.3/4.3 GHz 14 × 1 MB 19.25 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 December 21, 2017 OEM for Apple[107][108]
Xeon W-2155
  • SR3LR (U0)
 10 (20) 3.3 GHz 4.0/4.5 GHz 10 × 1 MB 13.75 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303533703
 $1440
Xeon W-2150B
  • SR3LS (H0)
 10 (20) 3 GHz 4.0/4.5 GHz 10 × 1 MB 13.75 MB
120 W
LGA 2066 DMI 3.0 4 × DDR4-2666 December 21, 2017 OEM for Apple[107][108]
Xeon W-2145
  • SR3LQ (U0)
 8 (16) 3.7 GHz 4.3/4.5 GHz 8 × 1 MB 11.00 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303533601
 $1113
Xeon W-2140B
  • SR3LK (H0)
 8 (16) 3.2 GHz 3.9/4.2 GHz 8 × 1 MB 11.00 MB
120 W
LGA 2066 DMI 3.0 4 × DDR4-2666 December 21, 2017 OEM for Apple[107][108]
Xeon W-2135
  • SR3LN (U0)
 6 (12) 3.7 GHz 4.4/4.5 GHz 6 × 1 MB 8.25 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303533403
 $835
Xeon W-2133
  • SR3LL (U0)
 6 (12) 3.6 GHz 3.8/3.9 GHz 6 × 1 MB 8.25 MB
140 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303533204
 $617
Xeon W-2125
  • SR3LM (U0)
 4 (8) 4 GHz 4.4/4.5 GHz 4 × 1 MB 8.25 MB
120 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303533303
 $444
Xeon W-2123
  • SR3LJ (U0)
 4 (8) 3.6 GHz 3.7/3.9 GHz 4 × 1 MB 8.25 MB
120 W
LGA 2066 DMI 3.0 4 × DDR4-2666 August 29, 2017
  • CD8067303533002
 $294
Xeon W-2104
  • SR3LH (U0)
 4 (4) 3.2 GHz N/A 4 × 1 MB 8.25 MB
120 W
LGA 2066 DMI 3.0 4 × DDR4-2400 August 29, 2017
  • CD8067303532903
 $255
Xeon W-2102
  • SR3LG (U0)
 4 (4) 2.9 GHz N/A 4 × 1 MB 8.25 MB
120 W
LGA 2066 DMI 3.0 4 × DDR4-2400 August 29, 2017
  • CD8067303532802
 $202

Server processors

[edit]

E3 series server chips all consist of System Bus 9 GT/s, maximum memory bandwidth of 34.1 GB/s dual channel memory. Unlike its predecessor, the Skylake Xeon CPUs require C230 series (C232/C236) or C240 series (C242/C246) chipset to operate, with integrated graphics working only with C236 and C246 chipsets. Mobile counterparts uses CM230 and CM240 series chipsets.

Skylake E3-12xx and E3 15xx v5 SKUs
Target
segment 		Cores
(threads) 		Processor
branding and model 		GPU Clock rate Cache TDP Release
date 		Release
price (USD)
tray / box 		Motherboard
CPU Graphics L3 L4 (eDRAM) Socket Interface Memory
Normal Turbo Normal Turbo

Server 4 (8) Xeon E3 v5 1280v5 — 3.7 GHz 4.0 GHz — 8 MB — 80 W Q4 2015 $612 / — LGA
1151 		DMI 3.0
PCIe 3.0
DDR4
2133/1866
or
DDR3L
1333/1600
with ECC
1275v5 HD P530 3.6 GHz 350 MHz 1.15 GHz $339 / —
1270v5 — 3.6 GHz — $328 / $339
1260Lv5 2.9 GHz 3.9 GHz 45 W $294 / —
1245v5 HD P530 3.5 GHz 350 MHz 1.15 GHz 80 W $284 / —
1240v5 — 3.5 GHz — $272 / $282
1240Lv5 2.1 GHz 3.2 GHz 25 W $278 / —
1230v5 3.4 GHz 3.8 GHz 80 W $250 / $260
4 (4) 1235Lv5 HD P530 2.0 GHz 3.0 GHz 350 MHz 1.15 GHz 25 W $250 / —
1225v5 3.3 GHz 3.7 GHz 80 W $213 / —
1220v5 — 3.0 GHz 3.5 GHz — $193 / —
Mobile
workstation 		4 (8) 1575Mv5 Iris Pro P580 3.0 GHz 3.9 GHz 350 MHz 1.1 GHz 128 MB 45 W Q1 2016 $1207 / — BGA
1440
DDR4-2133
LPDDR3-1866
DDR3L-1600
with ECC
1545Mv5 2.9 GHz 3.8 GHz 1.05 GHz $679 / —
1535Mv5 HD P530 — Q3 2015 $623 / —
1505Mv5 2.8 GHz 3.7 GHz $434 / —
Embedded 1505Lv5 2.0 GHz 2.8 GHz 1.0 GHz 25 W Q4 2015 $433 / —

Skylake-SP (14 nm) Scalable Performance

[edit]
  • Xeon Platinum supports up to eight sockets. Xeon Gold supports up to four sockets. Xeon Silver and Bronze support up to two sockets.
    • −M: 1536 GB RAM per socket instead of 768 GB RAM for non−M SKUs
    • −F: integrated OmniPath fabric
    • −T: High thermal-case and extended reliability
  • Support for up to 12 DIMMs of DDR4 memory per CPU socket.
  • Xeon Platinum, Gold 61XX, and Gold 5122 have two AVX-512 FMA units per core. Xeon Gold 51XX (except 5122), Silver, and Bronze have a single AVX-512 FMA unit per core.

Xeon Bronze and Silver (dual processor)

[edit]
  • Xeon Bronze 31XX has no HT or Turbo Boost support.
  • Xeon Bronze 31XX supports DDR4-2133 MHz RAM. Xeon Silver 41XX supports DDR4-2400 MHz RAM.
  • Xeon Bronze 31XX and Xeon Silver 41XX support two UPI links at 9.6 GT/s.
Model sSpec
number 		Cores
(threads) 		Clock rate Turbo Boost
all-core/2.0
(/max. 3.0) 		L2
cache 		L3
cache 		TDP Socket I/O bus Memory Release date Part
number(s) 		Release
price (USD)
Xeon Silver 4116
  • SR3HQ (M0)
 12 (24) 2.1 GHz 2.4/3.0 GHz 12 × 1 MB 16.50 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303567200
  • BX806734116
 $1002
$1012
Xeon Silver 4116T
  • SR3MQ (M0)
 12 (24) 2.1 GHz 2.4/3.0 GHz 12 × 1 MB 16.50 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 Q3 2017
  • CD8067303645400
 $1112
Xeon Silver 4114
  • SR3GK (U0)
 10 (20) 2.2 GHz 2.5/3.0 GHz 10 × 1 MB 13.75 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303561800
  • BX806734114
 $694
$704
Xeon Silver 4114T
  • SR3MM (U0)
 10 (20) 2.2 GHz 2.5/3.0 GHz 10 × 1 MB 13.75 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 Q3 2017
  • CD8067303645300
 $773
Xeon Silver 4112
  • SR3GN (U0)
 4 (8) 2.6 GHz 2.9/3.0 GHz 4 × 1 MB 8.25 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303562100
  • BX806734112
 $473
$483
Xeon Silver 4110
  • SR3GH (U0)
 8 (16) 2.1 GHz 2.4/3.0 GHz 8 × 1 MB 11.00 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303561400
  • BX806734110
 $501
$511
Xeon Silver 4109T
  • SR3GP (U0)
 8 (16) 2 GHz 2.3/3.0 GHz 8 × 1 MB 11.00 MB
70 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303562200
 $501
Xeon Silver 4108
  • SR3GJ (U0)
 8 (16) 1.8 GHz 2.1/3.0 GHz 8 × 1 MB 11.00 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303561500
  • BX806734108
 $417
$427
Xeon Bronze 3106
  • SR3GL (U0)
 8 (8) 1.7 GHz N/A 8 × 1 MB 11.00 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2133 11 July 2017
  • CD8067303561900
  • BX806733106
 $306
$316
Xeon Bronze 3104
  • SR3GM (U0)
 6 (6) 1.7 GHz N/A 6 × 1 MB 8.25 MB
85 W
LGA 3647 2 × 9.6 GT/s UPI 6 × DDR4-2133 11 July 2017
  • CD8067303562000
  • BX806733104
 $223
$213

Xeon Gold (quad processor)

[edit]
  • Xeon Gold 51XX and F SKUs has two UPIs at 10.4 GT/s. Xeon Gold 61XX has three UPIs at 10.4 GT/s.
  • Xeon Gold 51XX support DDR4-2400 MHz RAM (except 5122). Xeon Gold 5122 and 61XX support DDR4-2666 MHz RAM.
Model sSpec
number 		Cores
(threads) 		Clock rate Turbo Boost
all-core/2.0
(/max. 3.0) 		L2
cache 		L3
cache 		TDP Socket I/O bus Memory Release date Part
number(s) 		Release
price (USD)
Xeon Gold 6161
  • SR3G7 (H0)
 22 (44) 2.2 GHz 2.7/3.0GHz 22 × 1 MB 30.25 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 2017
  • CD8067303532100
Xeon Gold 6154
  • SR3J5 (H0)
 18 (36) 3 GHz 3.7/3.7GHz 18 × 1 MB 24.75 MB
200 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303592700
 $3543
Xeon Gold 6152
  • SR3B4 (H0)
 22 (44) 2.1 GHz 2.8/3.7GHz 22 × 1 MB 30.25 MB
140 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303406000
  • BX806736152
 $3655
$3661
Xeon Gold 6150
  • SR37K (H0)
 18 (36) 2.7 GHz 3.4/3.7GHz 18 × 1 MB 24.75 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303328000
 $3358
Xeon Gold 6149 16 (32) 3.1 GHz 16 × 1 MB MB LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 OEM
Xeon Gold 6148
  • SR3B6 (H0)
 20 (40) 2.4 GHz 3.1/3.7GHz 20 × 1 MB 27.50 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303406200
  • BX806736148
 $3072
$3078
Xeon Gold 6148F
  • SR3KJ (H0)
 20 (40) 2.4 GHz 3.1/3.7GHz 20 × 1 MB 27.50 MB
150 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593800
 $3227
Xeon Gold 6146
  • SR3MA (H0)
 12 (24) 3.2 GHz 3.9/4.2GHz 12 × 1 MB 24.75 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303657201
 $3286
Xeon Gold 6145
  • SR3G4 (H0)
 20 (40) 2 GHz 2.7/3.7GHz 20 × 1 MB 27.50 MB
145 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 2017
  • CD8067303528200
Xeon Gold 6144
  • SR3MB (H0)
 8 (16) 3.5 GHz 4.1/4.2GHz 8 × 1 MB 24.75 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 Q3 2017
  • CD8067303657302
 $2925
Xeon Gold 6142M
  • SR3B1 (H0)
 16 (32) 2.6 GHz 3.3/3.7GHz 16 × 1 MB 22.00 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405700
 $5949
Xeon Gold 6142F
  • SR3KH (H0)
 16 (32) 2.6 GHz 3.3/3.7GHz 16 × 1 MB 22.00 MB
160 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593700
 $3101
Xeon Gold 6142
  • SR3AY (H0)
 16 (32) 2.6 GHz 3.3/3.7GHz 16 × 1 MB 22.00 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405400
  • BX806736142
 $2946
$2952
Xeon Gold 6140
  • SR3AX (H0)
 18 (36) 2.3 GHz 3.0/3.7GHz 18 × 1 MB 24.75 MB
140 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405200
  • BX806736140
 $2445
$2451
Xeon Gold 6140M
  • SR3AZ (H0)
 18 (36) 2.3 GHz 3.0/3.7GHz 18 × 1 MB 24.75 MB
140 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405500
 $5448
Xeon Gold 6138
  • SR3B5 (H0)
 20 (40) 2 GHz 2.7/3.7GHz 20 × 1 MB 27.50 MB
125 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303406100
  • BX806736138
 $2612
$2618
Xeon Gold 6138F
  • SR3KK (H0)
 20 (40) 2 GHz 2.7/3.7GHz 20 × 1 MB 27.50 MB
135 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593900
 $2767
Xeon Gold 6138T
  • SR3J7 (H0)
 20 (40) 2 GHz 2.7/3.7GHz 20 × 1 MB 27.50 MB
125 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303592900
 $2742
Xeon Gold 6136
  • SR3B2 (H0)
 12 (24) 3 GHz 3.6/3.7GHz 12 × 1 MB 24.75 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405800
 $2460
Xeon Gold 6134
  • SR3AR (H0)
 8 (16) 3.2 GHz 3.7/3.7GHz 8 × 1 MB 24.75 MB
130 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303330302
  • BX806736134
 $2214
$2220
Xeon Gold 6134M
  • SR3AS (H0)
 8 (16) 3.2 GHz 3.7/3.7GHz 8 × 1 MB 24.75 MB
130 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303330402
 $5217
Xeon Gold 6132
  • SR3J3 (H0)
 14 (28) 2.6 GHz 3.3/3.7GHz 14 × 1 MB 19.25 MB
140 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303592500
 $2111
Xeon Gold 6130
  • SR3B9 (H0)
 16 (32) 2.1 GHz 2.8/3.7GHz 16 × 1 MB 22.00 MB
125 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303409000
  • BX806736130
 $1900
Xeon Gold 6130F
  • SR3KD (H0)
 16 (32) 2.1 GHz 2.8/3.7GHz 16 × 1 MB 22.00 MB
125 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593300
 $2049
Xeon Gold 6130T
  • SR3J8 (H0)
 16 (32) 2.1 GHz 2.8/3.7GHz 16 × 1 MB 22.00 MB
125 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593000
 $1988
Xeon Gold 6128
  • SR3J4 (H0)
 6 (12) 3.4 GHz 3.7/3.7GHz 6 × 1 MB 19.25 MB
115 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303592600
  • BX806736128
 $1691
$1697
Xeon Gold 6126
  • SR3B3 (H0)
 12 (24) 2.6 GHz 3.3/3.7GHz 12 × 1 MB 19.25 MB
125 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405900
 $1776
Xeon Gold 6126F
  • SR3KE (H0)
 12 (24) 2.6 GHz 3.3/3.7GHz 12 × 1 MB 19.25 MB
135 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593400
 $1931
Xeon Gold 6126T
  • SR3J9 (H0)
 12 (24) 2.6 GHz 3.3/3.7GHz 12 × 1 MB 19.25 MB
125 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303593100
 $1865
Xeon Gold 5122
  • SR3AT (H0)
 4 (8) 3.6 GHz 3.7/3.7GHz 4 × 1 MB 16.50 MB
105 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303330702
  • BX806735122
 $1221
$1227
Xeon Gold 5120
  • SR3GD (M0)
 14 (28) 2.2 GHz 2.6/3.2GHz 14 × 1 MB 19.25 MB
105 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303535900
  • BX806735120
 $1555
$1561
Xeon Gold 5120T
  • SR3GC (M0)
 14 (28) 2.2 GHz 2.6/3.2GHz 14 × 1 MB 19.25 MB
105 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303535700
 $1727
Xeon Gold 5119T
  • SR3MN (M0)
 14 (28) 1.9 GHz 2.3/3.2GHz 14 × 1 MB 19.25 MB
85 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303567703
 $1555
Xeon Gold 5118
  • SR3GF (M0)
 12 (24) 2.3 GHz 2.7/3.2GHz 12 × 1 MB 16.50 MB
105 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303536100
 $1273
Xeon Gold 5117
  • SR37S (M0)
 14 (28) 2 GHz 2.3/2.8GHz 14 × 1 MB 19.25 MB
105 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303317801
 $1286
Xeon Gold 5117F
  • SR3KM (M0)
 14 (28) 2 GHz 2.3/2.8GHz 14 × 1 MB 19.25 MB
113 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303680501
Xeon Gold 5115
  • SR3GB (M0)
 10 (20) 2.4 GHz 2.8/3.2GHz 10 × 1 MB 13.75 MB
85 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2400 11 July 2017
  • CD8067303535601
 $1221
  • Intel Skylake Xeon gold processor
    Intel Skylake Xeon gold processor
  • Intel Skylake Xeon gold processor, delidded
    Intel Skylake Xeon gold processor, delidded
  • Die shot
    Die shot

Xeon Platinum (octal processor)

[edit]
  • Xeon Platinum non-F SKUs have three UPIs at 10.4 GT/s. Xeon Platinum F-SKUs have two UPIs at 10.4 GT/s.
  • Xeon Platinum supports DDR4-2666 MHz RAM.
Model sSpec
number 		Cores
(threads) 		Clock rate Turbo Boost
all-core/2.0
(/max. 3.0) 		L2
cache 		L3
cache 		TDP Socket I/O bus Memory Release date Part
number(s) 		Release
price (USD)
Xeon Platinum 8180
  • SR377 (H0)
 28 (56) 2.5 GHz 3.2/3.8 GHz 28 × 1 MB 38.50 MB
205 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303314400
 $10,009
Xeon Platinum 8180M
  • SR37T (H0)
 28 (56) 2.5 GHz 3.2/3.8 GHz 28 × 1 MB 38.50 MB
205 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303192101
 $13,011
Xeon Platinum 8176
  • SR37A (H0)
 28 (56) 2.1 GHz 2.8/3.8 GHz 28 × 1 MB 38.50 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303314700
 $8790
Xeon Platinum 8176F
  • SR3MK (H0)
 28 (56) 2.1 GHz 2.8/3.8 GHz 28 × 1 MB 38.50 MB
173 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 Q3, 2017
  • CD8067303694600
 $8874
Xeon Platinum 8176M
  • SR37U (H0)
 28 (56) 2.1 GHz 2.8/3.8 GHz 28 × 1 MB 38.50 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303133605
 $11,722
Xeon Platinum 8173M
  • SR37Q (H0)
 28 (56) 2 GHz 2.7/3.5 GHz 28 × 1 MB 38.50 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 2017
  • CD8067303172400
Xeon Platinum 8170
  • SR37H (H0)
 26 (52) 2.1 GHz 2.8/3.7 GHz 26 × 1 MB 35.75 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303327601
  • BX806738170
 $7405
$7411
Xeon Platinum 8170M
  • SR3BD (H0)
 26 (52) 2.1 GHz 2.8/3.7 GHz 26 × 1 MB 35.75 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303319201
 $10,409
Xeon Platinum 8168
  • SR37J (H0)
 24 (48) 2.7 GHz 3.4/3.7 GHz 24 × 1 MB 33.00 MB
205 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303327701
 $5890
Xeon Platinum 8167M
  • SR3A0 (H0)
 26 (52) 2 GHz 2.4/2.4 GHz 26 × 1 MB 35.75 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 2017
  • CD8067303180701
Xeon Platinum 8164
  • SR3BB (H0)
 26 (52) 2 GHz 2.7/3.7 GHz 26 × 1 MB 35.75 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303408800
  • BX806738164
 $6114
$6120
Xeon Platinum 8163
  • SR3G1 (H0)
 24 (48) 2.4 GHz 2.7/3.1 GHz 24 × 1 MB 33.00 MB
165 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 2017
  • CD8067303527200
Xeon Platinum 8160
  • SR3B0 (H0)
 24 (48) 2.1 GHz 2.8/3.7 GHz 24 × 1 MB 33.00 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303405600
  • BX806738160
 $4702
$4708
Xeon Platinum 8160F
  • SR3B8 (H0)
 24 (48) 2.1 GHz 2.8/3.7 GHz 24 × 1 MB 33.00 MB
160 W
LGA 3647 2 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303406600
 $4856
Xeon Platinum 8160M
  • SR3B8 (H0)
 24 (48) 2.1 GHz 2.8/3.7 GHz 24 × 1 MB 33.00 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303406600
 $7704
Xeon Platinum 8160T
  • SR3J6 (H0)
 24 (48) 2.1 GHz 2.8/3.7 GHz 24 × 1 MB 33.00 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303592800
 $4936
Xeon Platinum 8158
  • SR3B7 (H0)
 12 (24) 3 GHz 2.7/3.7 GHz 12 × 1 MB 24.75 MB
150 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303406500
 $7007
Xeon Platinum 8156
  • SR3AV (H0)
 4 (8) 3.6 GHz 3.3/3.7 GHz 4 × 1 MB 16.50 MB
105 W
LGA 3647 3 × 10.4 GT/s UPI 6 × DDR4-2666 11 July 2017
  • CD8067303368800
 $7007
Xeon Platinum 8153
  • SR3BA (H0)
 16 (32) 2 GHz 2.3/2.8 GHz 16 × 1 MB 22.00 MB
125 W
LGA 3647 3 × 10.4 GT/s QPI 6 × DDR4-2666 11 July 2017
  • CD8067303408900
 $3115

See also

[edit]

References

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Skylake (microarchitecture)

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Skylake is the codename for Intel's microarchitecture that powers the sixth-generation Core microprocessor family for client devices and the Xeon Scalable processor family for servers and workstations, launched in August 2015 as the successor to the Broadwell microarchitecture. Fabricated on a 14 nm process technology, it features a refined out-of-order execution engine with larger buffers for deeper speculation, enhanced front-end throughput supporting up to 6 μops per cycle via the Decoded Stream Buffer in client variants, and improved branch prediction capabilities. The Skylake design emphasizes balanced performance across integer, floating-point, and vector workloads, with key advancements including a hierarchical cache system—32 KB L1 data cache per core (8-way associative, 4-cycle latency), 256 KB L2 cache per core in client configurations (4-way, 12 cycles), and up to 8 MB shared L3 cache (16-way, ~44 cycles)—optimized for higher bandwidth and reduced latency compared to predecessors. In server implementations (Skylake-SP), it scales to 28 cores per socket with 1 MB L2 per core, a non-inclusive last-level cache of 1.375 MB per core, and support for instructions (including extensions like AVX512BW and AVX512DQ) to accelerate data-intensive tasks such as and . Notable improvements include doubled L2 bandwidth over Broadwell, hardware merging to eliminate partial register stalls, and enhanced memory subsystem supporting up to 2666 MHz DDR4 across six channels in servers, enabling up to 1.5x gains in integer workloads and 1.95x in vector operations. Skylake also integrates advanced power management like Speed Shift and security features such as SGX, while its longevity—serving as the basis for variants through 2021—made it one of 's most enduring architectures.

Development and Release

Design Goals and Planning

The development of Skylake was driven by Intel's objective to deliver a significant instructions per clock (IPC) uplift of approximately 10-15% compared to the preceding Broadwell microarchitecture, primarily through enhancements such as wider execution units and refined branch prediction mechanisms. This targeted improvement aimed to boost overall computational efficiency without relying on aggressive clock speed increases, allowing for better performance in diverse workloads. The architecture was positioned as a "tock" in Intel's tick-tock model, emphasizing a full microarchitectural redesign on the established 14nm process node to optimize density and transistor performance over Broadwell's initial 14nm implementation. A core focus of Skylake's planning was to balance high performance with power efficiency and cost-effectiveness across desktops, mobile ultrabooks, and server environments, enabling scalability from low-power 4.5W tablets to high-end 91W processors. This multi-segment approach addressed growing demands for integrated solutions that supported emerging standards like DDR4 memory and USB 3.1 while maintaining competitive pricing through process refinements that reduced power consumption by up to 22% in select scenarios. The project was led by Intel's R&D center in , , with key contributions from architects like Shlomit Weiss, who played a pivotal role in the CPU core design and overall microarchitectural integration. For the integrated GPU aspects, Intel's Visual Computing Group handled the Gen9 development, ensuring advancements in media processing and graphics capabilities to meet the era's and light gaming needs. Strategically, Skylake was crafted to solidify 's dominance in the x86 market against competitors like , whose and architectures lagged in IPC and efficiency during 2015, by leveraging 14nm optimizations for higher sustained clocks and better yield rates that lowered production costs. This shift from the 22nm Haswell era enabled Intel to extend the 14nm node's viability, focusing on architectural tweaks rather than node transitions to deliver reliable volume production for broad market adoption.

Timeline and Manufacturing Process

The development of the Skylake microarchitecture was shaped by ongoing challenges in Intel's 14 nm process technology, which had previously delayed the rollout of the Broadwell microarchitecture due to low initial yields and defect density issues. These maturation hurdles limited Broadwell to niche mobile applications, positioning Skylake as the first widespread consumer implementation of the 14 nm FinFET process. Skylake was first publicly showcased through partner announcements at 2015 in June, with desktop variants officially launching on August 5, 2015, starting with unlocked models like the Core i5-6600K and i7-6700K. Mobile processors arrived shortly after in September 2015, expanding availability to laptops and ultrabooks with series such as Skylake-U and Skylake-H. The server-oriented Skylake-SP variant, part of the Scalable family, followed in July 2017, supporting up to 28 cores per socket. Skylake processors were fabricated on Intel's 14 nm FinFET process at multiple facilities, including Fab 28 in , and Fab 32 in . The consumer die measured 122 mm², accommodating up to four cores, while initial yields started low but improved significantly by late 2015, enabling broader .

Architectural Changes from Broadwell

CPU Core Enhancements

Skylake introduced a wider front-end compared to Broadwell, enabling higher instruction throughput in the initial stages. The micro-operation (μop) cache in Skylake supports fetching up to 6 μops per cycle, a significant increase from Broadwell's 4-wide μop cache, which helps sustain higher instruction supply rates for common code loops and reduces pressure on the decoders. Additionally, the legacy decoders can emit up to 5 μops per cycle in Skylake, compared to 4 in Broadwell, allowing for better handling of instruction decode bottlenecks when the μop cache misses. These enhancements contribute to an overall increase in (IPC) by improving front-end efficiency. Branch prediction in Skylake employs an advanced TAGE (TAgged GEometric) predictor, building on Broadwell's implementation with increased capacity and improved accuracy for complex patterns such as long repetitive sequences and indirect branches. This results in fewer mispredictions, with the penalty for a branch misprediction remaining around 15-20 cycles but occurring less frequently due to the predictor's enhancements. Skylake's branch target buffer (BTB) features a two-level structure with 128-entry L1 and 4K-entry L2, supporting up to 1 taken or 2 not-taken branches per cycle, which aids in maintaining front-end momentum. The engine in Skylake features a 4-wide dispatch/rename and 4-wide retirement unit, the same widths as Broadwell but with a larger reorder buffer for deeper . It includes 4 arithmetic logic units (ALUs) across execution ports 0, 1, 5, and 6, providing balanced throughput similar to Broadwell's configuration. Skylake features three generation units (AGUs), with two capable of loads on ports 2 and 3 and one dedicated to stores on port 4, the same as Broadwell, enabling better overlap of calculations for memory operations. The reorder buffer size increases to 224 entries from Broadwell's 192, supporting deeper windows. Memory access resources in Skylake include two dedicated load ports (execution ports 2 and 3) and one store port (port 4), sustaining up to two 32-byte loads and one 32-byte store per cycle for a total of 64 bytes load bandwidth, matching Broadwell but integrated with the wider engine for improved utilization. This configuration supports 256-bit vector loads efficiently, enhancing bandwidth for data-intensive workloads without changes to the fundamental port count from Broadwell. Skylake's floating-point execution incorporates fused multiply-add (FMA) units on ports 0 and 1, delivering 2x 256-bit AVX2 FMA operations per cycle with a 4-cycle latency, an optimization over Broadwell's 5-cycle FMA latency while maintaining the same peak throughput. This allows for up to 32 floating-point operations per cycle in AVX2 workloads, emphasizing vectorized compute efficiency in the core.

Integrated GPU Improvements

Skylake introduces the Gen9 , a significant from Broadwell's Gen8, featuring low-power execution units (EUs) optimized for integrated GPUs in client processors. Each EU in Gen9 supports up to seven threads with enhanced SIMD capabilities, including native 32-bit floating-point atomics and improved 16-bit float operations, enabling better compute efficiency for and media workloads. Configurations vary by model: GT1 variants like HD 510 include 12 EUs, GT2 models such as HD 530 and Iris 540 feature 24 EUs, while high-end Iris Pro 580 employs 72 EUs paired with 128 MB of for superior performance in demanding scenarios. This supports hardware-accelerated 4K video decoding via HEVC (H.265) Main 10 profile at 10-bit , allowing efficient playback of high-dynamic-range content without excessive CPU overhead. Gen9 enhances pixel throughput through architectural refinements, including an increased number of sub-slices per slice—up to three in GT2 and higher configurations compared to two in Gen8—and upgraded texture sampling units that double the sampling rate to four texels per clock in certain modes. These changes, combined with larger per-slice L3 caches (up to 768 KB) and optimized thread scheduling with fine-grained preemption, deliver up to 50% better overall graphics performance relative to Broadwell's equivalent configurations in benchmarks like . For instance, the Iris Pro 580 achieves substantially higher frame rates in 11 titles at resolutions when compared to Broadwell's Iris Pro 6200, benefiting from both EU scaling and reduced latency in the . Texture units now natively handle NV12 formats and min/max filtering, improving efficiency for modern rendering techniques without relying on software fallbacks. Quick Sync Video receives key enhancements in Skylake, introducing full hardware acceleration for H.265 (HEVC) encoding in the Main profile at 8-bit depth, enabling faster video transcoding for 4K content with lower power draw than software-only methods. This fixed-function media engine processes up to 4:2:0 chroma subsampling at 2160p resolutions, supporting lookahead variable bitrate control for better quality-to-efficiency balance in applications like streaming and content creation. Additionally, Gen9 GPUs conform to DirectX 12 Feature Level 12_1 on Windows, providing tiled resources, conservative rasterization, and typed UAV loads for advanced shader programming, which broadens compatibility with contemporary games and compute APIs. A notable integration advancement is the shared last-level cache (LLC), often referred to as eLLC in high-end variants, which allocates up to 8 MB of coherent cache between the CPU cores and GPU, minimizing data transfer latency to system memory. In Iris Pro models, this shared LLC works alongside the dedicated to form a multi-tiered caching system, where the GPU can access CPU data directly, boosting scenarios like and AI by reducing DRAM bandwidth pressure. This design contrasts with prior generations by implementing non-inclusive caching policies that enhance coherence for shared (SVM) operations.

I/O and Memory Subsystem Changes

Skylake's integrated (IMC) supports dual-channel DDR4-2133 configurations, enabling a maximum capacity of 64 GB using non-ECC UDIMMs or SODIMMs. While consumer models like the Core i7-6700K do not support ECC, server-oriented variants such as the E3 v5 series include ECC compatibility for enhanced in enterprise environments. The IMC incorporates advanced scheduling features, including just-in-time command scheduling, command overlap, and , which optimize access patterns to reduce latency and boost bandwidth over Broadwell's implementation. These enhancements allow for better handling of memory-intensive workloads by improving prefetch and minimizing idle times on the memory bus. The uncore subsystem in Skylake features a ring bus interconnect that connects the CPU cores, last-level cache (LLC), , and integrated GPU, scaling bandwidth proportionally with core count for improved multi-core efficiency. This design distributes LLC slices—one per core—across the ring, enabling low-latency data sharing and better overall system throughput compared to prior generations. In quad-core configurations typical of client processors, the ring operates at effective frequencies aligned with the core clock, supporting up to 10-12 cores in later derivatives without significant degradation in inter-core communication. Skylake pairs with the 100 Series chipsets (Sunrise Point), such as the Z170 for enthusiast platforms, which integrate up to 20 additional PCIe 3.0 lanes beyond the CPU's 16 lanes for expanded peripheral connectivity, including high-speed storage and graphics cards. These chipsets also introduce USB 3.1 Gen 2 support, delivering up to 10 Gbps transfer rates for compatible devices, a step up from the prevalent in Broadwell-era platforms. This combination enhances I/O scalability for desktops and laptops, facilitating faster data movement between the CPU and external components. The integrated GPU's display engine receives upgrades in Skylake, supporting eDP 1.4 for embedded displays and 2.0 outputs, which enable simultaneous at 60 Hz across up to three monitors. This capability stems from the Gen9 architecture's improved multi-display pipeline, allowing configurations like dual 4K over and without external hardware, surpassing Broadwell's limitations in high-resolution multi-monitor scenarios.

Other Architectural Modifications

Skylake increased the size of the shared L3 cache to 8 MB in quad-core client configurations, up from 6 MB in the preceding Broadwell architecture, while adopting a non-inclusive that avoids duplicating data present in the private L2 caches. This shift to non-inclusivity, combined with an expanded per-core L2 cache in certain variants, enhances overall cache hit rates by reducing redundancy and minimizing evictions from lower-level caches. In high-core-count implementations such as Skylake-X for high-end desktop and Skylake-SP for servers, an advanced interconnect replaces the traditional ring bus topology to facilitate scalable communication among cores. This design supports configurations of up to 28 cores per socket in server variants, providing higher bandwidth and lower latency for inter-core data transfers while maintaining power efficiency. Skylake continues support for (TSX), incorporating Restricted Transactional Memory (RTM) as a mechanism to enable hardware-accelerated transactional execution with improved reliability through abort handling and fallback paths. The benefits from die layout optimizations on the 14 nm FinFET process, including refined structures and placement strategies that reduce static power leakage and enhance overall energy efficiency compared to Broadwell.

Key Features

Performance and Instruction Set Extensions

Skylake provides full-speed support for AVX2 instructions, enabling 256-bit vector operations across integer and floating-point domains without the throughput penalties seen in prior microarchitectures. This includes dedicated hardware for gather and scatter operations, such as VPGATHERDD and VPSCATTERDD, which facilitate efficient handling of irregular data access patterns in vectorized applications like scientific simulations and data analytics. The microarchitecture introduces Intel Memory Protection Extensions (MPX), a set of instructions designed to enforce bounds checking on pointer arithmetic at runtime, thereby mitigating vulnerabilities common in software. MPX augments existing x86 instructions with new opcodes like BNDLDX and BNDMOV, allowing compilers to insert hardware-accelerated checks with low overhead in many workloads. Skylake enhances SSE and AVX instruction throughput through refined execution pipelines, including improved macro-fusion and port utilization that serve as foundational elements for later vector instructions (VNNI) in subsequent architectures. These optimizations yield up to 1.5x (IPC) gains in highly vectorized workloads compared to scalar code, particularly in domains like image processing and primitives. Skylake demonstrates performance uplifts over Broadwell, reflecting broader IPC improvements enabled by wider decode capabilities that accommodate these extensions.

Power Management and Efficiency

Skylake incorporates Enhanced Intel SpeedStep Technology (EIST), which enables dynamic voltage and (DVFS) to balance performance and energy consumption by adjusting the processor's operating frequency and voltage based on workload demands. This is complemented by the Energy Performance Preference (EPP) feature, accessible via the IA32_HWP_REQUEST (MSR), allowing the operating system to specify a preference curve that influences hardware-controlled frequency decisions for optimized energy efficiency in varying scenarios. Idle power management in Skylake relies on advanced C-states, ranging from C1 (processor halt) to deeper states like C6 for core power gating and up to C10 in mobile variants, where context retention occurs at sub-1 mW per core to minimize leakage during prolonged inactivity. These states facilitate package-level power reduction by synchronizing with system activity, such as graphics frame boundaries, ensuring rapid resumption without significant latency penalties—typically under 50 µs for C6 wake-up. For active workloads, Skylake employs Turbo Boost Technology 2.0, which dynamically increases core frequencies up to 4.2 GHz on single-core bursts for desktop models like the Core i7-6700K while adhering to the 91 W TDP envelope through thermal and power monitoring. This is enhanced by per-core P-states (PCPs), enabling fine-grained, independent voltage and frequency adjustments across cores, which can reduce average power consumption by 4-35% in mixed workloads compared to uniform chip-level scaling by tailoring operations to individual core utilization. The Running Average Power Limit (RAPL) interface integrates these mechanisms by enforcing long-term (e.g., 28-second window) and short-term power caps, such as 91 W sustained and up to 141 W transient for desktops, to prolong turbo durations while preventing thermal throttling and supporting battery life in mobile configurations. Overall, these features contribute to Skylake's improved , with mobile variants achieving connected-standby power as low as 10-20 mW for the platform in optimized idle scenarios.

Security and Virtualization Support

Skylake incorporates Intel Virtualization Technology (VT-x) with Extended Page Tables (EPT) and unrestricted guest mode, facilitating efficient hardware-assisted . EPT enables direct mapping of guest physical addresses to host physical addresses, reducing overhead from shadow paging and allowing virtual machines to achieve near-native performance by minimizing VM exits for . The unrestricted guest mode further enhances this by permitting 64-bit guest execution without requiring the host to emulate certain privileged states, supporting seamless operation of unmodified guest operating systems in virtual environments. A key security innovation in Skylake is (SGX), which provides hardware-enforced trusted execution environments known as enclaves. SGX allows applications to isolate sensitive code and data within these enclaves, protecting them from access or modification by the operating system, , , or other higher-privilege software, even in compromised systems. Enclaves are created and managed through dedicated instructions like ECREATE and EENTER, with memory encrypted using a processor-derived key to ensure confidentiality and integrity during execution. This feature is particularly useful for securing cryptographic operations or proprietary algorithms in cloud or multi-tenant environments. Skylake enhances cryptographic performance through AES New Instructions (AES-NI), offering up to 4x throughput for AES and decryption compared to pure software implementations on prior architectures, by accelerating key expansion, round computations, and inverse operations for 128-, 192-, and 256-bit keys. To bolster kernel-level protection, Skylake supports Supervisor Mode Execution Prevention (SMEP) and (SMAP). SMEP prevents the execution of user-mode pages in supervisor mode, mitigating exploits that attempt to hijack kernel by injecting malicious code into user-accessible memory. SMAP extends this by blocking supervisor-mode loads and stores to user-mode pages unless explicitly allowed via the , further separating kernel and user address spaces to prevent accidental or malicious data leaks and corruption. These features, enabled via CR4 bits, are integral to for defending against attacks.

Known Issues and Limitations

Hardware Bugs and Errata

Skylake processors are vulnerable to the Spectre and Meltdown security vulnerabilities, which exploit flaws in mechanisms to potentially leak sensitive data across security boundaries. These issues, disclosed in early 2018, affect Skylake due to its branch prediction and designs, enabling side-channel attacks that could read kernel memory from user space in the case of Meltdown or poison branch predictions for Spectre variants. Skylake is also affected by later vulnerabilities, including Microarchitectural Data Sampling (MDS, disclosed 2019), which leaks data via store buffers and line fill buffers, and Gather Data Sampling (Downfall, disclosed 2023), exploiting AVX/AVX2 gather instructions for cross-core data leakage. Mitigations for these, including MDS and Downfall, involve updates and OS patches, with potential performance impacts of up to 10-20% in affected workloads. released updates in January 2018 for Spectre/Meltdown, often in combination with operating system patches like kernel page table isolation, though full protection required coordinated software and hardware responses. A notable hardware defect in Skylake, documented as erratum SKL150, involves enabled configurations where complex microarchitectural conditions—such as short loops under 64 instructions using both AH/BH/CH/DH registers and corresponding wide registers—can lead to incorrect instruction execution, resulting in or unpredictable system behavior. This bug, observed primarily in synthetic and specific computational scenarios, was fixed through a update delivered via in mid-2017, restoring correct behavior without disabling . Early desktop Skylake processors exhibited unexpected current limit throttling due to conservative ICCTMAX and power limit settings (PL1/), causing frequency reductions and performance degradation under heavy multi-threaded loads despite adequate cooling. This issue, affecting models like the Core i7-6700K, was resolved via updates from motherboard vendors in late 2015 and early 2016, adjusting limits to allow full Turbo Boost performance. The integrated controller in Skylake's 100 Series chipset (e.g., Z170) exhibited intermittent disconnects and detection failures, particularly after system resume from sleep states or during high-load transfers, stemming from errata like overwritten status bits or hangs in the xHCI controller. These issues, affecting device enumeration and stability, were addressed in subsequent chipset stepping revisions and workarounds, with recommending updated drivers for resolution. Intel's specification updates for Skylake detail numerous errata, including SKL091, which impacts monitoring counters for latency measurements, potentially reporting inaccurate divider operation timings in tools relying on these events. Other documented issues encompass AVX execution slowdowns post-power state transitions (SKL048) and speculative branch target injection vulnerabilities (SKX104 in server variants), all mitigated via or updates where possible, ensuring overall platform reliability through ongoing support.

Thermal and Power Delivery Problems

High TDP variants of the Skylake microarchitecture, such as those in the Skylake-X family, presented significant challenges for power delivery and management. Processors like the Core i9-7900X featured a 140 W TDP rating, which demanded robust (VRM) designs on motherboards to handle sustained loads without inducing throttling. Inadequate VRM cooling or capacity could lead to current limits—such as a design current of 73 A—triggering frequency reductions under heavy multi-threaded workloads, as Intel defined these parameters to specify VRM load and cooling needs. This was exacerbated by the use of instead of between the die and integrated , resulting in inefficient and higher operating temperatures even at stock settings. Mobile implementations of Skylake, particularly in ultra-low power SKUs, faced thermal constraints that limited performance boosts. Variants configured for up to 28 W TDP, such as certain U-series processors, often reached junction temperatures (Tj) of 100 °C under prolonged loads, marking the maximum safe operating limit and activating thermal throttling to prevent damage. These hotspots restricted the effectiveness of Turbo Boost, capping frequency increases and overall efficiency in thin-and-light laptops where cooling solutions were compact. Early (BGA) packages used in soldered mobile Skylake processors exhibited power delivery vulnerabilities, leading to instability at stock voltages. Insufficient regulation in laptop VRMs could cause voltage fluctuations during transient loads, resulting in crashes or reduced reliability without updates or enhanced power phases. Intel addressed these through integrated fully integrated (FIVR) refinements, but initial designs required careful system validation to maintain stability. To mitigate these issues, Skylake incorporated Intel's Thermal Monitoring Technologies, which enabled dynamic clock adjustments based on real-time temperature readings from digital thermal sensors. This allowed the processor to throttle frequencies proactively when approaching Tjmax, preserving performance while avoiding overheating, as detailed in 's architecture manuals for . Such mechanisms integrated with Enhanced Intel SpeedStep Technology to balance power draw and thermal headroom across variants.

Software and OS Support

Initial Compatibility and Drivers

Upon its launch in August 2015, the Skylake microarchitecture received initial software support optimized primarily for , as Microsoft optimized the operating system for its features like DirectX 12 and the Windows Display Driver Model 2.0 (WDDM 2.0), with limited compatibility on and 8.1. Intel provided dedicated graphics drivers for the integrated HD Graphics 530 series, starting with version 15.40, which enabled full GPU acceleration and hardware decoding for H.265/HEVC content. For distributions, full enablement of Skylake's features, including the Gen9 integrated , required kernel version 4.2 or later, which incorporated preliminary support in the i915 DRM driver for display output, , and basic rendering capabilities. Earlier kernels like 4.1 offered limited functionality, often necessitating manual configuration or patches for stability. enthusiasts faced significant compatibility challenges with macOS (10.11) on Skylake systems due to the locked (ME) firmware, which prevented easy kernel extensions and required custom bootloaders like with specific patches for CPU identification and initialization. Initial builds often resulted in kernel panics or incomplete hardware recognition until supplemental updates in late 2015. Early motherboard BIOS and UEFI implementations for Skylake's 100-series chipsets needed updates to support XMP profiles for DDR4 overclocking beyond the standard of 2133 MT/s, ensuring stable operation at higher speeds like 2666 or 3200 MT/s. Additionally, enabling Secure Boot in mode was essential for certification and booting, with initial firmware versions from manufacturers like and MSI including these options to comply with the platform's requirements.

Long-term Support and Updates

As of November 2025, support for the Skylake microarchitecture has transitioned into a focused on security and legacy compatibility, following the end of mainstream updates for associated operating systems. concluded general support for on October 14, 2025, marking the cessation of free driver and feature updates for Skylake-based systems running this OS. However, extended security updates (ESU) remain available, with the first year free for consumers in regions like the (EEA) until October 2026, and paid extensions providing critical patches for vulnerabilities until at least October 2028 for eligible editions, thereby extending Skylake's viability on . Additionally, continues to issue updates for Skylake processors to address security issues, such as transient execution attacks, ensuring ongoing protection against newly disclosed exploits without requiring full OS upgrades. In the Linux ecosystem, Skylake maintains robust long-term support through (LTS) kernels, with versions up to 6.12 and beyond providing full compatibility for features introduced in this . These LTS releases, such as Linux 6.1 (extended through 2026) and 6.6, receive ongoing bug fixes and security enhancements, allowing Skylake systems to run modern distributions without hardware limitations. The integration of Rust-for-Linux further bolsters this support, as Rust-based kernel components—now stable in kernels 6.8 and later—enhance driver reliability and on Skylake hardware, with backports available to LTS branches for broader adoption. Skylake's Transactional Synchronization Extensions (TSX), comprising Restricted Transactional Memory (RTM) and Hardware Lock Elision (HLE), faced deprecation following the discovery of Spectre-class vulnerabilities like ZombieLoad and Transactional Asynchronous Abort (TAA), which exploited in these features. responded with updates starting in 2019 and expanding through 2021, disabling TSX by default on Skylake and subsequent generations to mitigate risks, while introducing an MSR (TSX_CTRL) that forces RTM transaction aborts and optionally preserves HLE as a lighter alternative for lock elision in scenarios. This disablement prioritizes security over performance gains from TSX, with developers encouraged to adopt software-based synchronization or HLE-enabled modes where feasible, though full TSX functionality remains accessible via reconfiguration at the user's risk. Regarding newer operating systems, Skylake processors are not officially supported on due to Microsoft's stringent hardware requirements, including a minimum of 8th-generation CPUs and mandatory TPM 2.0 support for enhanced security features like virtualization-based security. While Skylake systems can technically run through unofficial bypass methods—such as registry modifications to skip TPM and CPU checks during installation—Microsoft has actively patched some exploits and emphasizes that unsupported hardware may lack optimized drivers, security updates, and stability. This official exclusion reflects broader trends in deprecating older microarchitectures to align with evolving security standards, though legacy users retain options via extended support.

Processor Configurations and Models

Desktop and High-End Desktop (Skylake-X)

The desktop implementations of the Skylake microarchitecture targeted consumer and enthusiast users, emphasizing improved single-threaded performance and support for DDR4 memory on the socket. The flagship model, the Core i7-6700K, featured 4 cores and 8 threads with a base frequency of 4.0 GHz and a maximum turbo frequency of 4.2 GHz; its unlocked multiplier enabled capabilities for enthusiasts seeking higher performance. For high-end desktop (HEDT) applications, Intel introduced the Skylake-X series on the LGA 2066 socket with the X299 chipset, supporting up to quad-channel DDR4 memory and offering greater core counts for multi-threaded workloads. This lineup included the Core i7-7800X with 6 cores and 12 threads, a base frequency of 3.5 GHz, and a maximum turbo frequency of 4.0 GHz, as well as models up to the Core i9-7980XE with 18 cores and 36 threads, a base frequency of 2.6 GHz, and a maximum turbo frequency of 4.2 GHz. Select desktop Skylake variants, such as the Skylake-R series (e.g., Core i7-6785R), integrated Intel Iris Pro Graphics 580 with 128 MB of eDRAM cache, which provided a significant performance uplift—approximately 20% in certain graphics benchmarks—over the standard HD Graphics 530 by reducing latency in texture-heavy applications. Thermal design power (TDP) across desktop Skylake processors varied to suit different use cases, ranging from 35 in low-power T-series models like the Core i7-6700T for compact systems to 91 in unlocked K-series processors; Skylake-X models extended this to 140 to accommodate their higher core counts and sustained multi-threaded performance. The X-series employed a (MCM) design to scale core counts efficiently while maintaining compatibility with consumer motherboards.

Mobile and Embedded Variants

Skylake mobile processors were optimized for laptops and ultrabooks, with configurations emphasizing low (TDP) for extended battery life and thermal constraints in thin designs. The U-series, exemplified by the Core i5-6200U, features 2 cores and 4 threads at a base frequency of 2.3 GHz, a 15W TDP, and integrated HD 520, enabling efficient performance in mainstream ultrabooks. Higher-performance H-series variants, such as the Core i7-6700HQ, scale to 45W TDP in gaming laptops, offering 4 cores and 8 threads with base frequencies up to 2.6 GHz and HD 530 for enhanced and gaming capabilities. For ultra-low-power fanless devices like tablets and 2-in-1 convertibles, the Y-series provides configurations at 4.5W TDP, as in the Core m3-6Y30 with 2 cores and 4 threads, a base frequency of 1.1 GHz, and HD Graphics 515, prioritizing always-on connectivity and silent operation. Premium mobile implementations support dual-channel LPDDR3-1866 memory to balance bandwidth and power efficiency, while low-end models like certain variants disable to further minimize consumption. Embedded variants of Skylake target IoT, industrial, and compact systems, often using soldered BGA packages for integration. Representative low-end options include the G3902E, a 2-core, 2-thread processor at 1.6 GHz with a 25W TDP and HD Graphics 510, packaged in BGA 1440 for reliable deployment in space-constrained environments. Mobile-derived embedded designs, such as those based on U-series in BGA 1356 packaging, extend Skylake's applicability to fanless embedded PCs, supporting similar power scaling from 15W while leveraging integrated platform controllers. These configurations incorporate power efficiency features like to meet the demands of always-on embedded applications.

Server and Workstation Processors (Skylake-SP)

The Scalable processors based on the Skylake-SP , launched in July 2017, target and environments, offering a range of core counts from 6 to 28 per socket to address diverse workloads such as , databases, and (HPC). These processors utilize the socket and support up to eight sockets interconnected via (UPI) links, with higher-end models featuring up to three UPI links per processor for scalable multi-socket configurations. The family is divided into four tiers—, , , and —each optimized for different performance and cost profiles, with all models supporting six-channel DDR4 memory and ECC for enterprise reliability. At the top end, Platinum processors like the Platinum 8180 deliver 28 cores operating at a 2.50 GHz base frequency (turbo up to 3.80 GHz), with a 205 W TDP and 38.5 MB of L3 cache, enabling robust multi-socket for demanding enterprise applications. and Platinum tiers emphasize HPC capabilities through full support, featuring two fused multiply-add (FMA) units per core that allow 512-bit vector operations for accelerated scientific simulations and data analytics. For entry-level dual-socket systems, and Silver processors provide cost-effective options; for instance, the Bronze 3106 offers 8 cores at 1.70 GHz base frequency with an 85 W TDP and 11 MB L3 cache, supporting DDR4-2133 speeds suitable for basic server tasks. Silver models, such as those in the 4100 series, step up to DDR4-2400 and include for better multi-threaded performance in mid-range workloads. A key innovation in Skylake-SP is the on-die mesh architecture, which replaces the previous ring bus to handle core counts exceeding 16 more efficiently by providing a 2D grid of interconnects for lower latency and higher bandwidth between cores, caches, and I/O. This design facilitates massive capacities, with up to 1.5 TB per socket using load-reduced DIMMs (LRDIMMs), allowing multi-socket systems—such as eight-socket configurations—to exceed 12 TB of total DDR4 for memory-intensive applications like in-memory databases. Overall, these features position Skylake-SP processors as foundational for scalable enterprise infrastructure, balancing power efficiency with performance in professional workstations and data centers.

Overclocking Capabilities

Official Overclocking Support

Intel officially supported on Skylake processors through specific unlocked models and compatible features, enabling users to exceed stock turbo boost frequencies while maintaining warranty coverage when adhering to recommended guidelines. The and KF series processors, such as the Core i7-6700K, include unlocked multipliers that allow manual adjustment of the core ratio in compatible / settings on Z170 motherboards. This feature permits significant performance gains, with representative overclocks reaching stable all-core speeds of 5.0 GHz or higher using high-end solutions, depending on quality and thermal management. In addition to multiplier adjustments, the Z170 chipset supports base clock (BCLK) , which scales the reference clock frequency—typically 100 MHz—affecting the CPU, integrated graphics, , and PCIe lanes proportionally. Users can achieve modest gains, such as 3-5% overall performance uplift, by increasing BCLK to 103-105 MHz while compensating for and other component stability through voltage tweaks and timing adjustments. This method provides flexibility for fine-tuning but requires careful validation to avoid system instability across all affected subsystems. Memory overclocking is facilitated by Intel's Extreme Memory Profile (XMP) 2.0 standard, integrated into Skylake's and Z170 implementations. XMP profiles enable one-click activation of DDR4 speeds beyond the standard of 2133 MT/s, commonly reaching 3000 MT/s or higher with dual-channel configurations, while adhering to safe DRAM voltage limits of 1.35 V to prevent degradation. This approach enhances bandwidth-sensitive workloads without manual configuration, though users must ensure compatibility with the processor's integrated for optimal results.

Unofficial Overclocking Methods

Unofficial overclocking methods for Skylake microarchitecture primarily targeted non-K series processors, which lack unlocked multipliers, by leveraging base clock (BCLK) adjustments on compatible Z170 chipset motherboards. This approach, enabled through vendor-specific modifications, allowed enthusiasts to increase the base clock beyond Intel's 100 MHz default, effectively scaling the CPU core speed while keeping the multiplier locked. The method relied on BIOS features like ASRock's "SKY OS" function, which decoupled BCLK changes from PCIe and chipset limitations that Intel had imposed to prevent such overclocking. For instance, on an ASRock Z170 motherboard with a Core i3-6100 (3.7 GHz base), users could raise BCLK to 127 MHz, achieving a 4.7 GHz all-core overclock—a 27% boost—while disabling the integrated GPU to maintain stability. Similarly, a Core i5-6600 reached 4.45 GHz with a 135 MHz BCLK on compatible boards, yielding approximately 35% higher clock speeds. Performance improvements included 24% gains in multi-threaded Cinebench scores and 25% in single-threaded tasks for the i3-6100, with memory bandwidth increasing by 18% to 35.6 GB/s. Implementation required Z170 motherboards from vendors like , MSI, or , often involving manual flashing to enable or retain BCLK controls. After initial updates in late 2015, Intel pressured manufacturers to remove these capabilities via microcode updates in subsequent , effectively locking non-K overclocking by mid-2016. Workarounds included downgrading to older versions (e.g., using tools like UEFI Updater to revert microcode to version 74) or retaining unmodified , though this risked compatibility with newer operating systems and security patches. Limitations of BCLK overclocking included its coarse granularity, as adjustments affected not only CPU speed but also PCIe lanes, controllers, and USB ports, often leading to instability beyond 130-135 MHz without fine-tuning voltages like VCCSA or VCCIO. Risks encompassed potential hardware damage from excessive voltages (e.g., core voltage exceeding 1.35V), system crashes, and voided warranties, as explicitly did not support on non-K processors. Even a dual-core G4400 could achieve 4.2 GHz (27% overclock) via 127 MHz BCLK, but such gains were uneven across workloads due to the architecture's sensitivity to clock domain changes.

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