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A logic circuit diagram for a 4-bit carry lookahead binary adder design using only the AND, OR, and XOR logic gates

A logic gate is a device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has, for instance, zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device[1] (see ideal and real op-amps for comparison).

The primary way of building logic gates uses diodes or transistors acting as electronic switches. Today, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).[2] They can also be constructed using vacuum tubes, electromagnetic relays with relay logic, fluidic logic, pneumatic logic, optics, molecules, acoustics,[3] or even mechanical or thermal[4] elements.

Logic gates can be cascaded in the same way that Boolean functions can be composed, allowing the construction of a physical model of all of Boolean logic, and therefore, all of the algorithms and mathematics that can be described with Boolean logic. Logic circuits include such devices as multiplexers, registers, arithmetic logic units (ALUs), and computer memory, all the way up through complete microprocessors,[5] which may contain more than 100 million logic gates.

Compound logic gates AND-OR-invert (AOI) and OR-AND-invert (OAI) are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.[6]

History and development

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The binary number system was refined by Gottfried Wilhelm Leibniz (published in 1705), influenced by the ancient I Ching's binary system.[7][8] Leibniz established that using the binary system combined the principles of arithmetic and logic.

The analytical engine devised by Charles Babbage in 1837 used mechanical logic gates based on gears.[9]

In an 1886 letter, Charles Sanders Peirce described how logical operations could be carried out by electrical switching circuits.[10] Early Electromechanical computers were constructed from switches and relay logic rather than the later innovations of vacuum tubes (thermionic valves) or transistors (from which later electronic computers were constructed). Ludwig Wittgenstein introduced a version of the 16-row truth table as proposition 5.101 of Tractatus Logico-Philosophicus (1921). Walther Bothe, inventor of the coincidence circuit,[11] got part of the 1954 Nobel Prize in physics, for the first modern electronic AND gate in 1924. Konrad Zuse designed and built electromechanical logic gates for his computer Z1 (from 1935 to 1938).

From 1934 to 1936, NEC engineer Akira Nakashima, Claude Shannon and Victor Shestakov introduced switching circuit theory in a series of papers showing that two-valued Boolean algebra, which they discovered independently, can describe the operation of switching circuits.[12][13][14][15] Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital computers. Switching circuit theory became the foundation of digital circuit design, as it became widely known in the electrical engineering community during and after World War II, with theoretical rigor superseding the ad hoc methods that had prevailed previously.[15]

In 1948, Bardeen and Brattain patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.[16] In 1957, Frosch and Derick were able to manufacture PMOS and NMOS planar gates.[17] Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.[18] Both types were later combined and adapted into complementary MOS (CMOS) logic by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.[19]

Symbols

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A synchronous 4-bit up/down decade counter symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]

There are two sets of symbols for elementary logic gates in common use, both defined in ANSI/IEEE Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from United States Military Standard MIL-STD-806 of the 1950s and 1960s.[20] It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.[21] The IEC standard, IEC 60617-12, has been adopted by other standards, such as EN 60617-12:1999 in Europe, BS EN 60617-12:1999 in the United Kingdom, and DIN EN 60617-12:1998 in Germany.

The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor.

IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.[21] These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another.

In the 1980s, schematics were the predominant method to design both circuit boards and custom ICs known as gate arrays. Today custom ICs and the field-programmable gate array are typically designed with Hardware Description Languages (HDL) such as Verilog or VHDL.

Type Distinctive shape
(IEEE Std 91/91a-1991)		 Rectangular shape
(IEEE Std 91/91a-1991)
(IEC 60617-12:1997)		 Boolean algebra between A and B Truth table
Single-input gates
Buffer

Buffer symbol

Buffer symbol

Input Output
A Q
0 0
1 1
NOT
(inverter)

NOT symbol

NOT symbol

or
Input Output
A Q
0 1
1 0
In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a bubble and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the positive logic convention or negative logic convention is being used (high voltage level = 1 or low voltage level = 1, respectively). The wedge is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called Direct Polarity Indication. See IEEE Std 91/91A and IEC 60617-12. Both the bubble and the wedge can be used on distinctive-shape and rectangular-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the bubble is meaningful.
Conjunction and disjunction
AND

AND symbol

AND symbol

or
Input Output
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
OR

OR symbol

OR symbol

or
Input Output
A B Q
0 0 0
0 1 1
1 0 1
1 1 1
Alternative denial and joint denial
NAND

NAND symbol

NAND symbol

or
Input Output
A B Q
0 0 1
0 1 1
1 0 1
1 1 0
NOR NOR symbol NOR symbol or
Input Output
A B Q
0 0 1
0 1 0
1 0 0
1 1 0
Exclusive or and biconditional
XOR XOR symbol XOR symbol or
Input Output
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
The output of a two input exclusive-OR is true only when the two input values are different, and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol.
XNOR XNOR symbol XNOR symbol or
Input Output
A B Q
0 0 1
0 1 0
1 0 0
1 1 1
Implication and Nonimplication
IMPLY[22][23] IMPLY symbol or
Input Output
A B Q
0 0 1
0 1 1
1 0 0
1 1 1
NIMPLY NIMPLY symbol or
Input Output
A B Q
0 0 0
0 1 0
1 0 1
1 1 0
IMPLY and NIMPLY are not commutative, meaning that changing the order of the operands may change the result. For instance, is false, but is true; likewise, is true, but is false.

De Morgan equivalent symbols

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By use of De Morgan's laws, an AND function is identical to an OR function with negated inputs and outputs. Likewise, an OR function is identical to an AND function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs.

This leads to an alternative set of symbols for basic gates that use the opposite core symbol (AND or OR) but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated.

A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor.

De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons.

Truth tables

[edit]

Output comparison of various logic gates:

1-input logic gates
Input Output
A Buffer Inverter
0 0 1
1 1 0
2-input logic gates
Input Output
A B AND NAND OR NOR XOR XNOR IMPLY NIMPLY
0 0 0 1 0 1 0 1 1 0
0 1 0 1 1 0 1 0 1 0
1 0 0 1 1 0 1 0 0 1
1 1 1 0 1 0 0 1 1 0

Universal logic gates

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Further information on the theoretical basis: Functional completeness

Charles Sanders Peirce (during 1880–1881) showed that NOR gates alone (or alternatively NAND gates alone) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.[24] The first published proof was by Henry M. Sheffer in 1913, so the NAND logical operation is sometimes called Sheffer stroke; the logical NOR is sometimes called Peirce's arrow.[25] Consequently, these gates are sometimes called universal logic gates.[26]

type NAND construction NOR construction
NOT
AND
NAND
OR
NOR
XOR
XNOR
IMPLY
NIMPLY

Data storage and sequential logic

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Animation of how an SR NOR gate latch works
Main article: Sequential logic

Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "latch" circuit. Latching circuitry is used in static random-access memory. More complicated designs that use clock signals and that change only on a rising or falling edge of the clock are called edge-triggered "flip-flops". Formally, a flip-flop is called a bistable circuit, because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called a sequential logic system since its output can be influenced by its previous state(s), i.e. by the sequence of input states. In contrast, the output from combinational logic is purely a combination of its present inputs, unaffected by the previous input and output states.

These logic circuits are used in computer memory. They vary in performance, based on factors of speed, complexity, and reliability of storage, and many different types of designs are used based on the application.

Manufacturing

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See also: Unconventional computing and Semiconductor device fabrication

Electronic gates

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A functionally complete logic system may be composed of relays, valves (vacuum tubes), or transistors.

Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-gain voltage amplifier, which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate.

The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.

For small-scale logic, designers now use prefabricated logic gates from families of devices such as the TTL 7400 series by Texas Instruments, the CMOS 4000 series by RCA, and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by programmable logic devices, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of programmable logic devices such as FPGAs has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed.

An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered.

The output of one gate can only drive a finite number of inputs to other gates, a number called the "fan-out limit". Also, there is always a delay, called the "propagation delay", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed synchronous circuits. Additional delay can be caused when many inputs are connected to an output, due to the distributed capacitance of all the inputs and wiring and the finite amount of current that each output can provide.

Logic families

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Main article: Logic family

There are several logic families with different characteristics (power consumption, speed, cost, size) such as: RDL (resistor–diode logic), RTL (resistor-transistor logic), DTL (diode–transistor logic), TTL (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors.

The simplest family of logic gates uses bipolar transistors, and is called resistor–transistor logic (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early integrated circuits. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in diode–transistor logic (DTL). Transistor–transistor logic (TTL) then supplanted DTL.

CMOS diagram of a NOT gate, also known as an inverter. MOSFETs are the most common way to make logic gates.

As integrated circuits became more complex, bipolar transistors were replaced with smaller field-effect transistors (MOSFETs); see PMOS and NMOS. To reduce power consumption still further, most contemporary chip implementations of digital systems now use CMOS logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation.

Other types of logic gates include, but are not limited to:[27]

Logic family Abbreviation Description
Diode logic DL
Tunnel diode logic TDL Exactly the same as diode logic but can perform at a higher speed.[failed verification]
Neon logic NL Uses neon bulbs or 3-element neon trigger tubes to perform logic.
Core diode logic CDL Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level.
4Layer Device Logic 4LDL Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required.
Direct-coupled transistor logic DCTL Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic.
Metal–oxide–semiconductor logic MOS Uses MOSFETs (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes PMOS logic, NMOS logic, complementary MOS (CMOS), and BiCMOS (bipolar CMOS).
Current-mode logic CML Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels.
Quantum-dot cellular automata QCA Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds.
Ferroelectric FET FeFET FeFET transistors can retain their state to speed recovery in case of a power loss.[28]

Three-state logic gates

[edit]
A three-state buffer can be thought of as a switch. If B is on, the switch is closed. If B is off, the switch is open.
Main article: Three-state logic

A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on buses of the CPU to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a multiplexer, which may be physically distributed over separate devices or plug-in cards.

In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit.

Non-electronic logic gates

[edit]

Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the Harvard Mark I, were built from relay logic gates, using electro-mechanical relays. Logic gates can be made using pneumatic devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.[29] Various types of fundamental logic gates have been constructed using molecules (molecular logic gates), which are based on chemical inputs and spectroscopic outputs.[30] Logic gates have been made out of DNA (see DNA nanotechnology)[31] and used to create a computer called MAYA (see MAYA-II). Logic gates can be made from quantum mechanical effects, see quantum logic gate. Photonic logic gates use nonlinear optical effects.

In principle any method that leads to a gate that is functionally complete (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates).

See also

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References

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Further reading

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[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Logic gate

View on Grokipedia
from Grokipedia
A logic gate is an elementary that implements a , taking one or more binary inputs (representing 0 or 1, false or true) and producing a single binary output based on a specific logical operation, serving as the foundational component of all digital systems. These gates operate using voltage levels to represent binary states, where low voltage typically denotes 0 and denotes 1, enabling the processing of in computers and other digital devices. The concept of logic gates originates from Boolean algebra, developed by George Boole in 1854 as a mathematical framework for logical operations using binary variables. In 1937, Claude Shannon's master's thesis at MIT demonstrated how Boolean algebra could be applied to electrical switching circuits, effectively establishing the theoretical basis for logic gates in electronic design and bridging mathematics with practical engineering. Early physical implementations used mechanical relays or vacuum tubes, but the invention of the in 1947 revolutionized the field, allowing for smaller, faster, and more efficient gates that form the basis of integrated circuits. There are seven basic types of logic gates: , NOT (inverter), NAND, NOR, XOR, and XNOR, each defined by its that specifies the output for all possible input combinations. For instance, an outputs 1 only if all inputs are 1, while an outputs 1 if at least one input is 1; the NOT gate inverts its single input. More complex gates like NAND and NOR are universal, meaning any can be constructed using only them, which simplifies in practice. Logic gates are interconnected to form combinational and sequential circuits, underpinning processors, units, and arithmetic logic units (ALUs) in modern computing hardware. Their scalability has driven , enabling the billions of transistors in contemporary microprocessors, and they remain essential in fields ranging from to hardware. Advances in materials, such as technology introduced in the , have reduced power consumption and increased speed, ensuring logic gates' continued relevance in nanoscale and explorations.

Fundamentals

Definition and principles

A logic gate is an idealized or physical electronic device that performs a on one or more binary inputs, producing a single binary output. These devices implement fundamental logical operations, such as conjunction (AND), disjunction (OR), and (NOT), serving as the basic units for processing binary signals in digital systems. The principles of logic gates are rooted in binary logic, a two-valued system where inputs and outputs represent truth values—typically denoted as true (1 or ) or false (0 or ). Each gate operates deterministically, computing its output based solely on the current input combination, without memory of prior states. In general, a logic gate realizes a f(x1,x2,…,xn)f(x_1, x_2, \dots, x_n), where x1x_1 through xnx_n are binary input variables (each 0 or 1), and the output is the result of applying the function to those inputs. These gates form the foundational building blocks of digital circuits, interconnecting to construct more complex logical structures. In and , logic gates enable essential functions such as arithmetic operations, control signals, and data routing by combining into larger circuits that perform sophisticated tasks. For instance, networks of gates can implement addition, decision-making, and information flow in processors and memory systems, underpinning the operation of modern digital devices. This binary decision-making capability, derived from , allows for the reliable manipulation of information in computational environments.

Basic logic gates

Basic logic gates form the foundational building blocks of digital circuits, performing fundamental operations on binary inputs to produce a single binary output. These gates operate on logic levels representing 0 (false or low) and 1 (true or high), and they are essential for implementing conditional logic in electronic systems. The primary basic gates include the , NOT, NAND, NOR, XOR, and XNOR, each with distinct input/output behaviors that enable the construction of more complex functions. While most gates accept two or more inputs, the NOT gate is unique in requiring only one. The outputs a logic 1 only if all of its inputs are 1; otherwise, it outputs 0. It typically has a minimum of two inputs but can be extended to multiple inputs for broader conjunction operations. This gate performs a function analogous to in binary arithmetic, where the output represents the product of inputs. For example, in a , an AND gate can ensure that multiple sensors (such as a door lock and a keycard reader) must all detect valid conditions before granting access. The outputs a logic 1 if at least one of its inputs is 1; it outputs 0 only if all inputs are 0. Like the , it supports a minimum of two inputs and can handle multiple inputs for disjunction logic. This inclusive OR function detects the presence of any true condition, differing from the exclusive variant (XOR) which requires exactly one true input. In applications such as alarm systems, an OR gate triggers an alert if any sensor detects an intrusion, like a door opening or breaking. The NOT gate, also known as an inverter, takes a single input and outputs the logical complement: 1 if the input is 0, and 0 if the input is 1. With only one input, it serves as the basic negation operator in digital logic. It is fundamental for inverting signals, such as flipping a control bit to deactivate a previously active function in simple switching circuits. The is the inverted form of the , outputting 0 only if all inputs are 1, and 1 otherwise. It requires a minimum of two inputs and, like the AND, supports multi-input configurations. As a universal gate, NAND can implement any when combined appropriately, making it versatile for compact circuit designs. The inverts the OR function, outputting 1 only if all inputs are 0, and 0 otherwise. It also has a minimum of two inputs and can be multi-input. NOR is similarly universal, capable of realizing all other logic functions, which contributes to its use in efficient implementations of complex logic. The outputs 1 if its inputs differ (one is 1 and the other is 0), and 0 if they are the same. It operates on exactly two inputs, as multi-input versions are typically constructed from pairs. XOR is key in applications like binary addition, where it generates the sum bit, and parity checking, where it detects an odd number of 1s in for error detection. The , or equivalence gate, inverts the XOR output, producing 1 if its two inputs are identical and 0 if they differ. It is used for equality comparisons, such as verifying matching bits in processes.

Representation

Graphical symbols

Graphical symbols for logic gates provide a standardized for representing digital circuits in schematics, allowing designers to abstract away physical implementations and focus on logical interconnections. These symbols emphasize input-output relationships and facilitate in documentation. The primary standards include the distinctive-shape symbols derived from earlier specifications like MIL-STD-806B and the rectangular-outline symbols defined in ANSI/IEEE Std 91-1984, which is compatible with IEC 60617-12 for broader adoption. Distinctive-shape symbols use unique geometric forms to intuitively convey gate functions, with inputs typically on the left and outputs on the right. The appears as a D-shaped (curved on the right), accepting multiple inputs that converge to a single output. The features a curved with pointed extensions on the input side, symbolizing addition-like . The NOT gate is depicted as a right-pointing with a small circle (bubble) at the output tip, indicating inversion. For multi-input versions, additional lines connect to the main body, such as three inputs joining the AND . These shapes, while mnemonic, have largely been supplanted by rectangular forms for compactness in complex diagrams. In contrast, rectangular-outline symbols employ uniform boxes to promote consistency, with the gate's operation denoted by an internal label or qualifier. Under ANSI/IEEE Std 91-1984, the is a containing the (&), the uses ≥1, and the NOT gate includes a flag-like extension or the numeral 1 with . Multi-input notations leverage dependency symbols, such as subscripted G for ANDed inputs (e.g., G1, G2) or V for ORed inputs, placed near the to indicate grouping without multiple lines. This approach supports hierarchical designs and is prevalent in modern schematics. Variations exist across standards to accommodate regional or historical preferences. IEC 60617-12 favors rectangular shapes exclusively, aligning closely with IEEE but using flags for instead of bubbles in some cases. Older European styles, like DIN 40700, occasionally appear in legacy documentation with slightly altered curvatures. Bubble notation—a small open circle—universally denotes inversion or active-low signals, placed at inputs for complemented logic (e.g., active-low enable) or outputs for negated results (e.g., NAND as AND with output bubble). An alternative triangular polarity indicator specifies active-low without inversion in positive-logic contexts, enhancing precision in mixed-signal diagrams. These elements ensure symbols remain versatile for schematic abstraction and .

Truth tables

Truth tables provide a tabular method to enumerate all possible input combinations for a logic gate and determine the corresponding output based on its logical function. For a gate with n binary inputs, the table consists of 2n rows, each representing a unique input combination, with columns dedicated to the input variables and the output. This exhaustive listing ensures complete coverage of the gate's behavior, using 0 to denote false and 1 to denote true. Intermediate columns may be included for complex expressions to break down the computation step by step. The NOT gate, which inverts a single input, has the simplest with two rows:
Input AOutput
01
10
This shows that the output is always the opposite of the input. For two-input gates, such as the , which produces an output of 1 only if both inputs are 1, the truth table is as follows:
Input AInput BOutput (A AND B)
000
010
100
111
The , outputting 1 if at least one input is 1, has this table:
Input AInput BOutput (A OR B)
000
011
101
111
The XOR () gate, which outputs 1 only when inputs differ, is represented by:
Input AInput BOutput (A XOR B)
000
011
101
110
These tables can extend to multi-input gates; for a three-input AND gate, which requires all inputs to be 1 for an output of 1, the table has 23 = 8 rows, with the output being 1 solely in the row where A=1, B=1, and C=1. Truth tables serve to verify a gate's functionality by matching observed outputs against expected values from the logical definition, aiding in error detection during design or implementation. They also facilitate high-level derivation of minimized expressions by identifying patterns in the output column, though detailed minimization requires additional techniques. In digital verification, tables confirm that a gate behaves as intended under all conditions, ensuring reliability in circuits. As an extension, Karnaugh maps offer a graphical visualization of truth table data arranged in a grid where adjacent cells represent input combinations differing by one bit, enabling simplification by grouping ones to form larger rectangles that correspond to product terms in the . This method, useful for gates with few inputs, complements s by providing an intuitive aid for verifying and optimizing gate behavior without exhaustive enumeration.

Advanced Concepts

Universal logic gates

A universal logic gate is one that, by itself, can be used to construct any possible , thereby forming a functionally complete set. The NAND and NOR gates qualify as universal because they inherently combine (AND) or disjunction (OR) with inversion (NOT), enabling the replication of all basic operations through appropriate interconnections. The NAND gate's universality is demonstrated by its ability to implement NOT, AND, OR, and more complex functions like XOR using only NAND gates. To create a NOT gate, connect both inputs of a NAND gate to the same signal AA; the output is A∧A‾=A‾\overline{A \land A} = \overline{A}. An follows by cascading a NAND gate with a NOT gate: the output of the NAND on inputs AA and BB feeds into the NOT, yielding A∧BA \land B. For an , apply De Morgan's theorem by first inverting the inputs (A‾\overline{A} and B‾\overline{B}, each via a NAND with tied inputs) and then applying NAND to those inverses: A‾∧B‾‾=A∨B\overline{\overline{A} \land \overline{B}} = A \lor B, requiring three NAND gates total. An can be built with four NAND gates: let M=A∧B‾M = \overline{A \land B}, then X1=A∧M‾X_1 = \overline{A \land M}, X2=B∧M‾X_2 = \overline{B \land M}, and output X1∧X2‾=A⊕B\overline{X_1 \land X_2} = A \oplus B. Similarly, the NOR gate serves as a universal gate through analogous constructions that leverage its disjunctive and inverting properties. A NOT gate is formed by tying both NOR inputs to AA, yielding A∨A‾=A‾\overline{A \lor A} = \overline{A}. An OR gate is simply a NOR followed by a NOT: A∨B‾‾=A∨B\overline{\overline{A \lor B}} = A \lor B. To build an AND gate, invert the inputs first (A‾\overline{A} and B‾\overline{B} via tied NORs), then apply NOR to those: A‾∨B‾‾=A∧B\overline{\overline{A} \lor \overline{B}} = A \land B, using three NOR gates. For XOR, five NOR gates are required, typically by constructing an XNOR with four NOR gates (dual to the NAND XOR) and adding a final NOT. The proof of universality for both NAND and NOR rests on their capacity to generate the primitive operations AND, OR, and NOT, which together form a complete basis for all Boolean functions. Since any Boolean expression can be rewritten in conjunctive or disjunctive normal form using these primitives, and each primitive is constructible from either NAND or NOR alone, any logic circuit can be realized using only that gate type. This functional completeness is verified through the explicit gate constructions outlined above, confirming that no other gate types are needed. Using universal gates like NAND and NOR offers advantages in and manufacturing, as they simplify fabrication by reducing the variety of gate types required, leading to more economical production and fewer potential points of failure.

De Morgan equivalents

provide a fundamental duality in , enabling the transformation of logical expressions involving AND and OR operations through . The first law states that the negation of the conjunction of two variables is equivalent to the disjunction of their negations: (A∧B)′=A′∨B′(A \land B)' = A' \lor B'. The second law states that the negation of the disjunction is equivalent to the conjunction of the negations: (A∨B)′=A′∧B′(A \lor B)' = A' \land B'. These laws can be verified through exhaustive comparisons, where both sides of each equation yield identical output values for all input combinations of A and B. In digital circuit representation, De Morgan's laws manifest as symbolic equivalents using inversion bubbles on gate inputs and outputs, illustrating the duality between AND and OR gates. For instance, an AND gate with inverted inputs and an inverted output is logically equivalent to an OR gate with non-inverted inputs, as the bubbles represent negations that align with the laws. Similarly, an OR gate with inverted inputs and inverted output equates to an AND gate without inversions. This bubble-pushing technique simplifies schematic diagrams by allowing designers to swap gate types while preserving functionality. These equivalents facilitate circuit optimization by enabling redesigns that reduce the number of or adapt to specific logic families, such as converting an AND-OR realization to a NAND-NAND . Consider a sum-of-products expression implemented as an AND-OR circuit; applying to negate and dualize the operations transforms it into a product-of-sums form suitable for NAND , often minimizing component count in two-level logic designs. The laws extend naturally to multiple variables, maintaining the pattern of duality under . For three , (A∧B∧C)′=A′∨B′∨C′(A \land B \land C)' = A' \lor B' \lor C' and (A∨B∨C)′=A′∧B′∧C′(A \lor B \lor C)' = A' \land B' \land C', allowing scalable transformations in complex expressions without altering the overall logic.

Circuit Applications

Combinational logic

circuits are digital circuits composed of interconnected logic gates where the output values are determined solely by the current input values, without any storage elements or feedback paths that would retain from previous . This ensures that the circuit behaves as a of its , producing outputs instantaneously upon input changes. In contrast, circuits incorporate memory components, allowing outputs to depend on both current and prior states. A fundamental example of a combinational circuit is the half-adder, which performs binary on two single-bit inputs, AA and BB, to produce a sum bit SS and a carry-out bit CoC_o. The sum is computed using an , S=A⊕BS = A \oplus B, while the carry is generated by an , Co=A⋅BC_o = A \cdot B. This simple structure adds the two bits without considering any incoming carry from a previous stage. The full-adder extends the half-adder to handle three inputs: AA, BB, and a carry-in bit CiC_i, producing sum SS and carry-out CoC_o. It can be implemented by cascading two half-adders—the first adding AA and BB to generate an intermediate sum and carry, which the second half-adder combines with CiC_i—followed by an OR gate to compute the final carry: S=(A⊕B)⊕CiS = (A \oplus B) \oplus C_i and Co=(A⋅B)+(A⊕B)⋅Ci+B⋅CiC_o = (A \cdot B) + (A \oplus B) \cdot C_i + B \cdot C_i. Alternatively, it uses two XOR gates, two AND gates, and one OR gate directly for the same functions. Full-adders serve as building blocks for multi-bit adders in arithmetic operations. Another key combinational circuit is the (MUX), which selects one of several input signals and forwards it to a single output line based on select signals. For a 2-to-1 MUX with inputs x0x_0, x1x_1, and select ss, the output Y=s‾⋅x0+s⋅x1Y = \overline{s} \cdot x_0 + s \cdot x_1, implemented using , and NOT gates. Larger MUXes, such as 4-to-1 with two select bits, use decoders internally to enable one input path via AND-OR logic. Multiplexers are versatile for data routing and implementing arbitrary functions by connecting variables to selects and constants to inputs. The design of combinational circuits typically begins with a specifying outputs for all input combinations, followed by conversion to a like sum-of-products (), where the output is expressed as an OR of AND terms (minterms) corresponding to rows where the output is 1. For instance, from a , minterms are identified—each a product of all input literals (variables or their complements)—and summed: F=∑miF = \sum m_i, where mim_i are the minterms. This expression is then realized with AND gates for products, OR gates for summation, and inverters as needed, often minimized using to reduce gate count. Combinational circuits find widespread applications in processors, including arithmetic logic units (ALUs) for operations like via chains of full-adders, as well as encoders that convert active inputs to binary codes and decoders that activate one of multiple outputs from a binary address. These components enable efficient and control signal generation without state retention.

Sequential logic

Sequential logic refers to digital circuits where the output depends not only on the current inputs but also on the previous state of the circuit, achieved through memory elements that incorporate feedback loops and often synchronized by clock signals. These circuits enable state transitions, allowing them to store information and respond to sequences of inputs over time, in contrast to which produces instantaneous outputs solely from current inputs. A fundamental building block of sequential logic is the SR latch, constructed using two cross-coupled NOR gates that provide feedback to maintain the output state. The SR latch has two inputs, Set (S) and Reset (R), and two complementary outputs, Q and Q-bar; when S=1 and R=0, Q=1 (set state); when S=0 and R=1, Q=0 (reset state); and when S=0 and R=0, the latch holds its previous state, while S=1 and R=1 is an invalid condition that should be avoided. For clocked operation, an enable input can be added to control when the latch responds to S and R. The D flip-flop extends this by providing edge-triggered storage, typically positive-edge triggered, where the output Q captures the value of the D input precisely at the rising of the clock and holds it until the next . This ensures synchronous behavior in larger systems, preventing race conditions from asynchronous changes. The JK flip-flop addresses limitations of the SR latch by adding toggle functionality; it uses J and K inputs where J=0 and K=0 holds the state, J=1 and K=0 sets Q=1, J=0 and K=1 resets Q=0, and J=1 and K=1 toggles Q to its complement on the clock , eliminating the invalid state. Sequential logic finds applications in counters, which increment or decrement a stored value on each clock pulse to track events or generate timing signals; shift registers, which move data bits serially or in parallel for tasks like data buffering and conversion; and finite state machines (FSMs), which model control logic by transitioning between defined states based on inputs and current state. Timing in sequential circuits is governed by clock signals that synchronize state changes, with setup time defined as the minimum duration the data input must be before the clock edge, and hold time as the minimum duration it must remain after the edge, to ensure reliable capture without . These parameters are critical for system reliability, as violations can lead to incorrect state transitions. Flip-flops serve as the core memory elements in static random-access memory (SRAM), where arrays of them store bits addressably, enabling fast read and write operations in computing systems.

Implementation

Electronic gates

Electronic logic gates are primarily implemented using semiconductor transistors, with complementary metal-oxide-semiconductor (CMOS) technology serving as the dominant approach due to its low power consumption and high noise immunity. In CMOS, basic gates like AND, OR, and NOT are constructed from pairs of n-channel (NMOS) and p-channel (PMOS) transistors arranged in complementary configurations. The simplest element, the NOT gate or inverter, consists of a single NMOS transistor connected in series with a PMOS transistor between the supply voltage (VDD) and ground, with the input applied to both gates and the output taken from their common drain connection. When the input is high (VDD), the NMOS turns on, pulling the output low (to ground), while the PMOS turns off; conversely, a low input turns the PMOS on, charging the output to VDD, and the NMOS off. More complex gates, such as NAND and NOR, extend this by paralleling PMOS transistors for NAND (or NMOS for NOR) and series-connecting the opposite type, enabling efficient realization of AND and OR functions through De Morgan's theorem. The performance of CMOS gates is influenced by fan-in (number of inputs) and fan-out (number of driven loads), which impact propagation delay due to increased capacitive loading. High fan-in raises internal capacitance, slowing switching, while excessive fan-out—typically limited to over 50 in CMOS before delay becomes prohibitive—requires buffering to maintain speed. Various logic families define the electronic characteristics of these gates, balancing speed, power, and margins. Transistor-transistor logic (TTL), using bipolar junction transistors, operates at 5V with a propagation delay of 1.5–33 ns, power dissipation of 1–22 mW per gate, of 10, and very good immunity (DC margins around 0.4V). , leveraging pairs, excels in low power (1 mW at 1 MHz, quiescent near 25 nW), excellent immunity (margins ~1.5V at 5V), exceeding 50, but slower propagation (1–200 ns at 3.3–5V). (ECL), also bipolar-based, prioritizes speed with 1–4 ns delays at -5.2V, but at higher power (4–55 mW) and of 25, with good immunity suitable for high-frequency applications. The following table compares key characteristics of these families:
FamilyVoltage (V)Propagation Delay (ns)Power Dissipation (mW/gate)Fan-outNoise Immunity
TTL51.5–331–2210Very Good
3.3–51–2001 (at 1 MHz)>50Excellent
ECL-5.21–44–5525Good
Three-state gates extend standard logic by adding an enable input to produce a high-impedance (Hi-Z) output state, allowing multiple gates to share a common bus without interference. A tri-state buffer, for instance, passes the input to the output when enabled (e.g., EN=1 for active-high), but enters Hi-Z when disabled (EN=0), effectively isolating the output as an open circuit to prevent loading or contention. This Hi-Z state is crucial for bidirectional data buses, where decoders select one driver at a time. The truth table for an active-high tri-state buffer extends the binary outputs:
Enable (EN)Input (IN)Output (OUT)
00Hi-Z
01Hi-Z
100
111
The symbol resembles a standard buffer with an additional enable line, often marked with a and control bubble if active-low. Scaling electronic gates into integrated circuits (ICs) enables compact, reliable designs, as exemplified by the 7400 series TTL chips. The 7400 IC integrates four independent 2-input NAND gates on a single 14-pin package, operating at 5V with low-power Schottky variants (74LS00) reducing while maintaining compatibility. This integration supports up to 10 per gate and has been foundational for combinational and sequential circuits since the .

Non-electronic gates

Non-electronic logic gates perform Boolean operations using physical principles beyond , such as mechanical motion, flows, propagation, biochemical reactions, or particle collisions. These implementations offer alternatives for specialized applications, particularly in environments hostile to traditional , like high-radiation zones or extreme temperatures, where they provide enhanced reliability through simpler, more robust mechanisms. Mechanical logic gates, often relay-based, employ electromechanical switches where input signals energize coils to open or close contacts, enabling AND operations via series connections (requiring all inputs active) and OR operations via parallel connections (activating with any input). Relays served as the core of early computing systems, such as the , which integrated over 3,500 relays in its to execute arithmetic and logical functions automatically. While relays introduce moving parts that can wear over time, their electromechanical nature allows operation in dusty or humid conditions where pure electronics might degrade. Fluidic logic gates leverage pneumatic or hydraulic flows to execute logic without mechanical or electrical components, relying on phenomena like the Coanda effect for wall attachment or vortex formation for amplification and switching. Vortex amplifiers, for instance, create swirl patterns that deflect or amplify fluid jets to perform OR/NOR and AND/NAND functions, with laminar proportional amplifiers providing gains up to 10 and bandwidths of 100-1000 Hz. These gates found practical use in control systems, such as roll rate stabilization for guided projectiles, where their all-fluid design—often using ceramics like Fotoceram—ensures operation in high-vibration, high-temperature (up to 550°C), and radiation-heavy environments without failure from ionizing effects. Optical logic gates utilize photonic switches to process signals, achieving functions like AND gates through constructive or destructive interference of beams in waveguides or photonic crystals. For example, phase-controllable metalenses can implement XOR and XNOR by modulating paths, enabling all-optical at speeds exceeding electronic limits due to light's velocity. Emerging in high-speed data processing, these gates support parallel operations in photonic integrated circuits, though challenges remain in scaling and integration with existing . Other non-electronic approaches include DNA-based gates, which exploit biochemical strand displacement reactions to realize , and more complex multi-input logic, producing fluorescent outputs from molecular inputs for parallel processing in biological contexts. Ballistic logic gates, as conceptualized in model, use elastic collisions of particles—analogous to billiard balls—to perform reversible operations like the , conserving momentum and energy for theoretically dissipation-free computation. A key advantage of non-electronic gates lies in their resilience to , radiation, and thermal extremes, as they avoid semiconductor vulnerabilities; for instance, and mechanical systems maintain functionality in nuclear or explosive settings with exceeding 600,000 hours in applications. However, they generally suffer speed limitations—relays switch in milliseconds, in hundreds of microseconds, and DNA reactions in minutes—compared to nanosecond-scale electronic gates, restricting them to niche roles like reliable control in harsh environments rather than general-purpose .

Historical Development

Early inventions

Theoretical foundations for logic gates were established in 1854 with George Boole's publication of An Investigation of the Laws of Thought, which formalized as a mathematical system for logical operations using binary variables and operations like AND, OR, and NOT. This work provided the abstract framework essential for later gate designs, treating logic as algebraic manipulation rather than verbal reasoning. In the 1880s, philosopher and logician advanced practical realizations by constructing electromechanical logic machines. These devices used electromagnetic relays and switches to execute Boolean operations, such as disjunctive syllogisms, demonstrating how electrical circuits could mechanize logical inference. Peirce's designs, including a relay-based logic engine built with student Allan Marquand, highlighted the potential for scalable electrical logic implementation. A pivotal development occurred in 1918 with the Eccles-Jordan trigger circuit, invented by William Henry Eccles and Frank Wilfred Jordan. This vacuum tube-based bistable multivibrator used two triode tubes in a feedback configuration to store binary states, forming the foundational element for flip-flops in circuits and enabling memory functions in early electronic systems. Building on this, Claude Shannon's 1937 master's thesis, A Symbolic Analysis of and Switching Circuits, rigorously applied to telephone networks, proving that complex switching functions could be synthesized from simple gates like AND and OR, thus establishing the theoretical basis for digital . Early physical implementations emerged in the late 1930s, including Konrad Zuse's Z1 computer completed in 1938. This mechanical binary computer utilized sliding pins and metal plates to perform arithmetic and logic operations, incorporating rudimentary gate-like mechanisms for addition and control flow in a programmable architecture. Complementing vacuum tube advances, early diode-resistor logic (DRL) appeared as a passive electronic approach in the 1950s, employing diodes for nonlinear switching and resistors for current limiting to realize AND and OR gates with minimal components, as seen in experimental circuits for computation and control.

Modern evolution

The modern evolution of logic gates began in the 1940s with the era, where early electronic computers relied on thousands of to implement basic logic functions. The , completed in 1945, utilized approximately 17,468 to perform logical operations, occupying 1,800 square feet and consuming 150 kilowatts of power. These tube-based gates, functioning as switches for AND, OR, and NOT operations, enabled the first programmable digital computations but were plagued by limitations including high failure rates, excessive heat generation, and enormous physical size, often requiring manual replacement of burnt-out tubes multiple times daily. The transistor revolution, starting in 1947, marked a pivotal shift by replacing vacuum tubes with solid-state devices that could reliably implement logic gates at much smaller scales and lower power. Invented at Bell Laboratories by , Walter Brattain, and , the demonstrated signal amplification and switching capabilities essential for logic operations. This led to the development of the first integrated circuit (IC) in 1958 by at , who fabricated multiple s and components on a single chip to form interconnected logic gates. Robert Noyce independently advanced this in 1959 at , creating a silicon-based monolithic IC with planar technology that allowed for scalable production of gate arrays. Gordon Moore's 1965 observation, later known as , predicted that the number of s—and thus logic gates—on an IC would double approximately every year (revised to every two years in 1975), driving exponential improvements in density and performance. These advancements transitioned logic gates from discrete components to very-large-scale integration (VLSI) by the 1970s, enabling billions of gates on single chips through photolithography and automated design tools, which reduced costs and power consumption while boosting computational speed. Recent trends continue this scaling with sub-10nm semiconductor processes; for instance, TSMC's 3nm FinFET technology entered high-volume production in 2022, packing over 290 million transistors per square millimeter for denser logic gate arrays with 15-25% performance gains over 5nm nodes. As of 2025, TSMC's 2 nm (N2) process, utilizing gate-all-around nanosheet transistors, has entered mass production, delivering up to 15% higher performance or 30% lower power compared to 3 nm while increasing transistor density. Beyond silicon, quantum logic gates operate on qubits using operations like the Pauli X gate for NOT functionality, which flips qubit states in superposition to enable quantum parallelism, as demonstrated in systems like IBM's quantum processors. Neuromorphic computing introduces brain-inspired gates, such as memristor-based synapses that mimic neuronal thresholds for efficient pattern recognition, reducing energy use in edge AI applications compared to traditional CMOS gates. VLSI-scale logic gates now underpin AI accelerators, like tensor processing units, where billions of gates execute matrix multiplications at terascale performance, facilitating advancements in machine learning models.

References

  1. https://www.bu.edu/lernet/artemis/years/2011/slides/logicgates.pdf
  2. http://intrologic.stanford.edu/extras/circuits.html
  3. https://www.academia.edu/87695382/Logic_Gates
  4. https://spectrum.ieee.org/claude-shannon-information-theory
  5. https://pages.hmc.edu/harris/cmosvlsi/4e/cmosvlsidesign_4e_ch1.pdf
  6. https://mathcenter.oxford.emory.edu/site/cs170/gates/
  7. https://webpages.charlotte.edu/~jmconrad/hsed/eleg_1tm.pdf
  8. https://engineering.purdue.edu/~meyer/DDU270/Refs/Pld/pal_guide.pdf
  9. https://bob.cs.sonoma.edu/IntroCompOrg-x64/bookch4.html
  10. https://www.cs.cmu.edu/afs/cs/academic/class/15849c-s02/www/scribe/logic.pdf
  11. https://www.se.rit.edu/~swen-440/reading/Boolean%20Logic%20and%20Digital%20Circuits.pdf
  12. https://bjc.berkeley.edu/bjc-r/cur/programming/6-computers/1-abstraction/09-digital-logic-gates.html
  13. https://people.engr.tamu.edu/djimenez/classes/312/lecture2.html
  14. https://teachersinstitute.yale.edu/curriculum/units/1989/7/89.07.07/4
  15. https://www.findlay.edu/offices/academic/scholarship-symposium/Documents/Poster%20Presentations/Ashley%20Moser-Arash%20Mahmoudian-The%20Practical%20Applications%20of%20Logic%20Gates%20in%20Computer%20Science%20Courses.pdf
  16. https://www.eng.auburn.edu/~niuguof/2210labdev/html/_downloads/66b4e1e312e08367f74f8b6fe2e107b3/ELEC2210%20Expt1.pdf
  17. http://faculty.etsu.edu/tarnoff/ntes2150/ch4_v02.pdf
  18. https://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf
  19. http://wakerly.org/DDPP/DDPP3_pdf/IEEEsyms.pdf
  20. https://spinningnumbers.org/a/logic-gates.html
  21. https://webstore.iec.ch/en/publication/2723
  22. http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/truth.html
  23. https://lms.devry.edu/lms/CourseExport/manual/files/DVU/ecet100/lecture5.html
  24. https://www.utdallas.edu/~dodge/EE2310/lec5.pdf
  25. https://openlab.citytech.cuny.edu/emtlabs/1250-exercises/universal-capability-of-nand-and-nor-gates/
  26. http://homepage.cs.uiowa.edu/~ghosh/02-21-08.pdf
  27. https://cseweb.ucsd.edu/classes/sp18/cse140-a/slides/lec6UniversalSet.pdf
  28. https://zoo.cs.yale.edu/classes/cs201/Fall_2021/lectures/Gates.html
  29. https://www.cs.bu.edu/~best/courses/modules/Transistors2Gates/
  30. https://www.geeksforgeeks.org/digital-logic/implementation-of-xor-gate-from-nand-gate/
  31. https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/logic_gates.html
  32. https://www.geeksforgeeks.org/electronics-engineering/implementation-of-xor-gate-from-nor-gate/
  33. https://myslu.stlawu.edu/~ehar/Spring12/220/appendix_c_2.html
  34. https://circles.math.ucla.edu/circles/lib/data/Handout-3542-3059.pdf
  35. https://american.cs.ucdavis.edu/academic/ecs154a.sum14/postscript/cosc205.pdf
  36. https://www.cs.kent.edu/~pwang/ctblog/nand.pdf
  37. http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/DeMorgan.html
  38. https://www.csee.umbc.edu/courses/undergraduate/CMPE212/labs/lab4/
  39. https://www2.hawaii.edu/~esb/2003fall.ics331/sep08.html
  40. http://cecs.wright.edu/~dkender/bme3512/ReviewBooleanAlgebraLogicGatesS17.pdf
  41. https://www.cs.cmu.edu/~15110-n15/lectures/unit08-1-BooleanLogic.pdf
  42. https://www.ece.ucf.edu/~mingjie/EEE3342/4.pdf
  43. https://home.adelphi.edu/~siegfried/cs371/371hw3.html
  44. https://bob.cs.sonoma.edu/IntroCompOrg-x64/bookch5.html
  45. http://web.mit.edu/6.111/www/f2017/handouts/L08.pdf
  46. https://web.ece.ucsb.edu/~parhami/pubs_folder/parh10-eeee-combinational-circuits.pdf
  47. http://www.cs.columbia.edu/~martha/courses/3827/sp11/slides/3_combinationalCircuits.pdf
  48. https://pages.hmc.edu/harris/class/e85/DDCArv_Ch2.pdf
  49. https://dc.etsu.edu/cgi/viewcontent.cgi?filename=0&article=1037&context=computer-organization-design-oer&type=additional
  50. https://web.stanford.edu/class/archive/ee/ee108a/ee108a.1082/reader/ch14to16.pdf
  51. https://ecelabs.njit.edu/ece294/lab2.php
  52. https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/latch_and_flip_flop.html
  53. https://ocw.mit.edu/courses/6-071j-introduction-to-electronics-signals-and-measurement-spring-2006/d0a578bc6340f91188b1e3ac487b62ab_sequential_logic.pdf
  54. https://www.physics.wisc.edu/courses/home/spring2023/623/lecture_notes/digital/digital-02.html
  55. https://courses.cs.washington.edu/courses/cse390c/15wi/lectures/07-FSMs.pdf
  56. https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/lect_06.pdf
  57. http://watson.latech.edu/book/circuits/circuitsMicrocomputer3.html
  58. http://people.ece.umn.edu/~kia/Courses/EE5323/Slides/Lect_03_Inverter.pdf
  59. https://www.rfwireless-world.com/terminology/ttl-vs-cmos-vs-ecl.html
  60. https://www.classe.cornell.edu/~ib38/teaching/p360/lectures/wk09/l26/EE2301Exp3F10.pdf
  61. https://www.electronics-tutorials.ws/logic/logic_9.html
  62. https://www.build-electronic-circuits.com/7400-series-integrated-circuits/74hc00-74ls00/
  63. https://ntrs.nasa.gov/api/citations/19730002533/downloads/19730002533.pdf
  64. https://www.nature.com/articles/s41467-019-08678-0
  65. https://www.allaboutcircuits.com/worksheets/electromechanical-relay-logic/
  66. https://apps.dtic.mil/sti/tr/pdf/ADA134046.pdf
  67. https://www.spiedigitallibrary.org/journals/optical-engineering/volume-59/issue-11/110901/All-optical-photonic-crystal-logic-gates-for-optical-computing/10.1117/1.OE.59.11.110901.full
  68. https://www.sciencedirect.com/science/article/pii/S0375960125004037
  69. https://www.oejournal.org/data/article/oes/preview/pdf/oes-2022-0010-ShaoLiyang.pdf
  70. https://pubs.acs.org/doi/10.1021/acssynbio.3c00474
  71. https://link.springer.com/chapter/10.1007/978-3-642-03745-0_29
  72. https://www.cambridge.org/core/books/an-investigation-of-the-laws-of-thought/80F323924812F038128653E6097E8953
  73. http://www.computer-timeline.com/wp-content/uploads/2022/08/PeirceArticle.pdf
  74. https://www.historyofinformation.com/detail.php?id=3606
  75. https://dspace.mit.edu/handle/1721.1/11173
  76. https://zuse.zib.de/z1
  77. https://hackaday.com/2016/12/09/diodes-the-switch-you-never-knew-you-had/
  78. https://www.pbs.org/wgbh/aso/databank/entries/dt47tr.html
  79. https://www.computerhistory.org/siliconengine/invention-of-the-point-contact-transistor/
  80. https://www.computerhistory.org/siliconengine/practical-monolithic-integrated-circuit-concept-patented/
  81. https://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf
  82. https://resources.pcb.cadence.com/blog/2020-vlsi-technology-its-history-and-uses-in-modern-technology
  83. https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm
  84. https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm
  85. https://pennylane.ai/qml/glossary/what-is-the-quantum-not-gate
  86. https://onlinelibrary.wiley.com/doi/abs/10.1002/adfm.202305791
  87. https://www.aiacceleratorinstitute.com/improving-ai-inference-performance-with-hardware-accelerators/
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