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Random-access memory
Random-access memory
Random-access memory
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Example of writable volatile random-access memory: Synchronous dynamic RAM modules, primarily used as main memory in personal computers, workstations, and servers.
Computer memory and data storage types
General
Volatile
RAM
Historical
Non-volatile
ROM
NVRAM
Early-stage NVRAM
Analog recording
Optical
In development
Historical
A 64 bit memory chip die, the SP95 Phase 2 buffer memory produced at IBM mid-1960s, versus memory core iron rings
8GB DDR3 RAM stick with a white heatsink

Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code.[1][2] A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks and magnetic tape), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.

In modern technology, random-access memory takes the form of integrated circuit (IC) chips with MOS (metal–oxide–semiconductor) memory cells. RAM is normally associated with volatile types of memory where stored information is lost if power is removed. The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access memory (DRAM).

Non-volatile RAM has also been developed[3] and other types of non-volatile memories allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of ROM and NOR flash memory.

The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their System/360 Model 95 computer, and Toshiba used bipolar DRAM memory cells for its 180-bit Toscal BC-1411 electronic calculator, both based on bipolar transistors. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.[4] In 1966, Dr. Robert Dennard invented modern DRAM architecture in which there's a single MOS transistor per capacitor.[5] The first commercial DRAM IC chip, the 1K Intel 1103, was introduced in October 1970. Synchronous dynamic random-access memory (SDRAM) was reintroduced with the Samsung KM48SL2000 chip in 1992.

History

[edit]
These IBM tabulating machines from the mid-1930s used mechanical counters to store information.

Early computers used relays, mechanical counters[6] or delay lines for main memory functions. Ultrasonic delay lines were serial devices which could only reproduce data in the order it was written. Drum memory could be expanded at relatively low cost but efficient retrieval of memory items requires knowledge of the physical layout of the drum to optimize speed. Latches built out of triode vacuum tubes, and later, out of discrete transistors, were used for smaller and faster memories such as registers. Such registers were relatively large and too costly to use for large amounts of data; generally, only a few dozen or few hundred bits of such memory could be provided.

The first practical form of random-access memory was the Williams tube. It stored data as electrically charged spots on the face of a cathode-ray tube. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the University of Manchester in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the Manchester Baby computer, which first successfully ran a program on 21 June, 1948.[7] In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory.[8][9]

Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible. Magnetic core memory was the standard form of computer memory until displaced by semiconductor memory in integrated circuits (ICs) during the early 1970s.[10]

Prior to the development of integrated read-only memory (ROM) circuits, permanent (or read-only) random-access memory was often constructed using diode matrices driven by address decoders, or specially wound core rope memory planes.[citation needed]

Semiconductor memory appeared in the 1960s with bipolar memory, which used bipolar transistors. Although it was faster, it could not compete with the lower price of magnetic core memory.[11]

MOS RAM

[edit]

In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.[12] Subsequently, in 1960, a team demonstrated a working MOSFET at Bell Labs.[13][14] This led to the development of metal–oxide–semiconductor (MOS) memory by John Schmidt at Fairchild Semiconductor in 1964.[10][15] In addition to higher speeds, MOS semiconductor memory was cheaper and consumed less power than magnetic core memory.[10] The development of silicon-gate MOS integrated circuit (MOS IC) technology by Federico Faggin at Fairchild in 1968 enabled the production of MOS memory chips.[16] MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.[10]

Integrated bipolar static random-access memory (SRAM) was invented by Robert H. Norman at Fairchild Semiconductor in 1963.[17] It was followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964.[10] SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data.[18] Commercial use of SRAM began in 1965, when IBM introduced the SP95 memory chip for the System/360 Model 95.[11]

Dynamic random-access memory (DRAM) allowed replacement of a 4- or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor and had to be periodically refreshed every few milliseconds before the charge could leak away.

Toshiba's Toscal BC-1411 electronic calculator, which was introduced in 1965,[19][20][21] used a form of capacitor bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors.[20][21] Capacitors had also been used for earlier memory schemes, such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.[22]

CMOS 1-megabit (Mbit) DRAM chip, one of the last models developed by VEB Carl Zeiss Jena, in 1989

In 1966, Robert Dennard, while examining the characteristics of MOS technology, found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, and the MOS transistor could control writing the charge to the capacitor. This led to his development of modern DRAM architecture for which there is a single MOS transistor per capacitor.[18] In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.[18][23] The first commercial DRAM IC chip was the Intel 1103, which was manufactured on an 8 μm MOS process with a capacity of 1 kbit, and was released in 1970.[10][24][25]

The earliest DRAMs were often synchronized with the CPU clock and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.[26][27] In 1992 Samsung released KM48SL2000, which had a capacity of 16 Mbit.[28][29] The first commercial double data rate SDRAM was Samsung's 64 Mbit DDR SDRAM, released in June 1998.[30] GDDR (graphics DDR) is a form of SGRAM (synchronous graphics RAM), which was first released by Samsung as a 16 Mbit memory chip in 1998.[31]

Types

[edit]

In general, the term RAM refers solely to solid-state memory devices, and more specifically the main memory in most computers. The two widely used forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state of a memory cell, typically using six MOSFETs. This form of RAM is more expensive to produce, but is generally faster and requires less static power than DRAM. In modern computers, SRAM is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair (typically a MOSFET and MOS capacitor, respectively),[32] which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.

Both static and dynamic RAM are considered volatile, as their state is lost when power is removed from the system. By contrast, read-only memory (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as EEPROM and NOR flash) share properties of both ROM and RAM, enabling data to persist without power and to be updated without requiring special equipment.

ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using parity bits or error correction codes.

Memory cell

[edit]
Main article: Memory cell (computing)

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information. The cell can be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

In SRAM, the memory cell is a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not being accessed, but it is complex, expensive and has low storage density.

A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a 1 or a 0 in the cell. However, the charge in this capacitor slowly leaks away and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM.

SRAM cell (6 transistors)
DRAM cell (1 transistor and one capacitor)

Addressing

[edit]

To be useful, memory cells must be readable and writable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select memory cells. Typically, a RAM device has a set of address lines , and for each combination of bits that may be applied to these lines, a set of memory cells are selected. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two.

Usually, several memory cells share the same address. For example, a 4-bit-wide RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different; For a 32-bit microprocessor, eight 4-bit RAM chips would be needed.

Often, more addresses are needed than can be provided by a single device. In that case, multiple devices are used, with external multiplexors used to select the device assigned to a specific address range. RAM is often byte addressable, although word-addressable RAM also exists.[33][34]

Memory hierarchy

[edit]
Main article: Memory hierarchy

Many computer systems have a memory hierarchy consisting of processor registers, on-die SRAM caches, external caches, DRAM, memory paging systems and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as RAM from a programming perspective. The overall goal of using a memory hierarchy is to obtain the fastest possible average access time while minimizing the total cost of the entire memory system.

Other uses of RAM

[edit]
A SO-DIMM stick of laptop RAM, roughly half the size of desktop RAM

In addition to serving as temporary storage and working space for the operating system and applications, RAM is used in numerous other ways.

Virtual memory

[edit]
Main article: Virtual memory

Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computer's hard drive is set aside for a paging file or a scratch partition, and the combination of physical RAM and the paging file form the system's total memory. (For example, if a computer has 2 GB (10243 B) of RAM and a 1 GB page file, the operating system has 3 GB total memory available to it.) When the system runs low on physical memory, it can "swap" portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM.

RAM disk

[edit]
Main article: RAM drive

Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a RAM disk. A RAM disk loses the stored data when the computer is shut down, unless memory is arranged to have a standby battery source, or changes to the RAM disk are written out to a nonvolatile disk. The RAM disk is reloaded from the physical disk upon RAM disk initialization.

Shadow RAM

[edit]

Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called shadowing, is fairly common in both computers and embedded systems.

As a common example, the BIOS in typical personal computers often has an option called "use shadow BIOS" or similar. When enabled, functions that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the operating system if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs.[35]

Virtual private networks

[edit]

Some virtual private network services utilize RAM servers to keep all runtime state including session metadata and cryptographic material in volatile memory so that a power cycle or reboot clears it, reducing persistent forensic artifacts relative to disk-backed designs.[36][37] In such a design, no data is written to hard drives; all information resides in volatile memory and is erased whenever the server is powered off or rebooted.[38]

Memory wall

[edit]

The memory wall is the growing disparity of speed between CPU and the response time of memory (known as memory latency) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries. From 1986 to 2000, CPU speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance.[39]

Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Modern CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.

CPU speed improvements slowed significantly partly due to major physical barriers and partly because CPU designs have already hit the memory wall in some sense. Intel summarized these causes in a 2005 document.[40]

First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, resistance-capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.

The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"[41] which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.

A different concept is the processor-memory performance gap, which can be addressed by 3D integrated circuits that reduce the distance between the logic and memory aspects that are further apart in a 2D chip.[42] Memory subsystem design requires a focus on the gap, which is widening over time.[43] The main method of bridging the gap is the use of caches; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.[44] There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.[45]

Solid-state hard drives have continued to increase in speed, from ~400 Mbit/s via SATA3 in 2012 up to ~7 GB/s via NVMe/PCIe in 2024, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane DDR5 8000MHz capable of 128 GB/s, and modern GDDR even faster. Fast, cheap, non-volatile solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in server farms - 1 terabyte of SSD storage can be had for $200, while 1 TB of RAM would cost thousands of dollars.[46][47]

Timeline

[edit]
See also: Flash memory § Timeline, Read-only memory § Timeline, and Transistor count § Memory

SRAM

[edit]
Static random-access memory (SRAM)
Date of introduction Chip name Capacity (bits) Access time SRAM type Manufacturer(s) Process MOSFET Ref
March 1963 — 1 ? Bipolar (cell) Fairchild — — [11]
1965 ? 8 ? Bipolar IBM ? —
SP95 16 ? Bipolar IBM ? — [48]
? 64 ? MOSFET Fairchild ? PMOS [49]
1966 TMC3162 16 ? Bipolar (TTL) Transitron ? — [10]
? ? ? MOSFET NEC ? ? [50]
1968 ? 64 ? MOSFET Fairchild ? PMOS [50]
144 ? MOSFET NEC ? NMOS
512 ? MOSFET IBM ? NMOS [49]
1969 ? 128 ? Bipolar IBM ? — [11]
1101 256 850 ns MOSFET Intel 12,000 nm PMOS [51][52][53][54]
1972 2102 1 kbit ? MOSFET Intel ? NMOS [51]
1974 5101 1 kbit 800 ns MOSFET Intel ? CMOS [51][55]
2102A 1 kbit 350 ns MOSFET Intel ? NMOS (depletion) [51][56]
1975 2114 4 kbit 450 ns MOSFET Intel ? NMOS [51][55]
1976 2115 1 kbit 70 ns MOSFET Intel ? NMOS (HMOS) [51][52]
2147 4 kbit 55 ns MOSFET Intel ? NMOS (HMOS) [51][57]
1977 ? 4 kbit ? MOSFET Toshiba ? CMOS [52]
1978 HM6147 4 kbit 55 ns MOSFET Hitachi 3,000 nm CMOS (twin-well) [57]
TMS4016 16 kbit ? MOSFET Texas Instruments ? NMOS [52]
1980 ? 16 kbit ? MOSFET Hitachi, Toshiba ? CMOS [58]
64 kbit ? MOSFET Matsushita
1981 ? 16 kbit ? MOSFET Texas Instruments 2,500 nm NMOS [58]
October 1981 ? 4 kbit 18 ns MOSFET Matsushita, Toshiba 2,000 nm CMOS [59]
1982 ? 64 kbit ? MOSFET Intel 1,500 nm NMOS (HMOS) [58]
February 1983 ? 64 kbit 50 ns MOSFET Mitsubishi ? CMOS [60]
1984 ? 256 kbit ? MOSFET Toshiba 1,200 nm CMOS [58][53]
1987 ? 1 Mbit ? MOSFET Sony, Hitachi, Mitsubishi, Toshiba ? CMOS [58]
December 1987 ? 256 kbit 10 ns BiMOS Texas Instruments 800 nm BiCMOS [61]
1990 ? 4 Mbit 15–23 ns MOSFET NEC, Toshiba, Hitachi, Mitsubishi ? CMOS [58]
1992 ? 16 Mbit 12–15 ns MOSFET Fujitsu, NEC 400 nm
December 1994 ? 512 kbit 2.5 ns MOSFET IBM ? CMOS (SOI) [62]
1995 ? 4 Mbit 6 ns Cache (SyncBurst) Hitachi 100 nm CMOS [63]
256 Mbit ? MOSFET Hyundai ? CMOS [64]

DRAM

[edit]
Dynamic random-access memory (DRAM)
Date of introduction Chip name Capacity (bits) DRAM type Manufacturer(s) Process MOSFET Area Ref
1965 — 1 bit DRAM (cell) Toshiba — — — [20][21]
1967 — 1 bit DRAM (cell) IBM — MOS — [23][50]
1968 ? 256 bit DRAM (IC) Fairchild ? PMOS ? [10]
1969 — 1 bit DRAM (cell) Intel — PMOS — [50]
1970 1102 1 kbit DRAM (IC) Intel, Honeywell ? PMOS ? [50]
1103 1 kbit DRAM Intel 8,000 nm PMOS 10 mm2 [65][66][24]
1971 μPD403 1 kbit DRAM NEC ? NMOS ? [67]
? 2 kbit DRAM General Instrument ? PMOS 13 mm2 [68]
1972 2107 4 kbit DRAM Intel ? NMOS ? [51][69]
1973 ? 8 kbit DRAM IBM ? PMOS 19 mm2 [68]
1975 2116 16 kbit DRAM Intel ? NMOS ? [70][10]
1977 ? 64 kbit DRAM NTT ? NMOS 35 mm2 [68]
1979 MK4816 16 kbit PSRAM Mostek ? NMOS ? [71]
? 64 kbit DRAM Siemens ? VMOS 25 mm2 [68]
1980 ? 256 kbit DRAM NEC, NTT 1,000–1,500 nm NMOS 34–42 mm2 [68]
1981 ? 288 kbit DRAM IBM ? MOS 25 mm2 [72]
1983 ? 64 kbit DRAM Intel 1,500 nm CMOS 20 mm2 [68]
256 kbit DRAM NTT ? CMOS 31 mm2
January 5, 1984 ? 8 Mbit DRAM Hitachi ? MOS ? [73][74]
February 1984 ? 1 Mbit DRAM Hitachi, NEC 1,000 nm NMOS 74–76 mm2 [68][75]
NTT 800 nm CMOS 53 mm2 [68][75]
1984 TMS4161 64 kbit DPRAM (VRAM) Texas Instruments ? NMOS ? [76][77]
January 1985 μPD41264 256 kbit DPRAM (VRAM) NEC ? NMOS ? [78][79]
June 1986 ? 1 Mbit PSRAM Toshiba ? CMOS ? [80]
1986 ? 4 Mbit DRAM NEC 800 nm NMOS 99 mm2 [68]
Texas Instruments, Toshiba 1,000 nm CMOS 100–137 mm2
1987 ? 16 Mbit DRAM NTT 700 nm CMOS 148 mm2 [68]
October 1988 ? 512 kbit HSDRAM IBM 1,000 nm CMOS 78 mm2 [81]
1991 ? 64 Mbit DRAM Matsushita, Mitsubishi, Fujitsu, Toshiba 400 nm CMOS ? [58]
1993 ? 256 Mbit DRAM Hitachi, NEC 250 nm CMOS ?
1995 ? 4 Mbit DPRAM (VRAM) Hitachi ? CMOS ? [63]
January 9, 1995 ? 1 Gbit DRAM NEC 250 nm CMOS ? [82][63]
Hitachi 160 nm CMOS ?
1996 ? 4 Mbit FRAM Samsung ? NMOS ? [83]
1997 ? 4 Gbit QLC NEC 150 nm CMOS ? [58]
1998 ? 4 Gbit DRAM Hyundai ? CMOS ? [64]
February 2001 ? 4 Gbit DRAM Samsung 100 nm CMOS ? [58][84]
June 2001 TC51W3216XB 32 Mbit PSRAM Toshiba ? CMOS ? [85]

SDRAM

[edit]
Part of this section is transcluded from Synchronous dynamic random-access memory. (edit | history)
Synchronous dynamic random-access memory (SDRAM)
Date of
intro-
duction 		Chip
name 		Capacity
(bits)[86] 		SDRAM
type 		Manufac-
turer(s) 		Pro-
cess 		MOS-
FET 		Area
(mm2) 		Ref
1992 KM48SL2000 16 Mbit SDR Samsung ? CMOS ? [87][28]
1996 MSM5718C50 18 Mbit RDRAM Oki ? CMOS 325 [88]
N64 RDRAM 36 Mbit RDRAM NEC ? CMOS ? [89]
? 1024 Mbit SDR Mitsubishi 150 nm CMOS ? [90]
1997 ? 1024 Mbit SDR Hyundai ? SOI ? [91]
1998 MD5764802 64 Mbit RDRAM Oki ? CMOS 325 [88]
Mar 1998 Direct RDRAM 72 Mbit RDRAM Rambus ? CMOS ? [92]
Jun 1998 ? 64 Mbit DDR Samsung ? CMOS ? [93][94][95]
1998 ? 64 Mbit DDR Hyundai ? CMOS ? [91]
128 Mbit SDR Samsung ? CMOS ? [96][94]
1999 ? 128 Mbit DDR Samsung ? CMOS ? [94]
1024 Mbit DDR Samsung 140 nm CMOS ? [90]
2000 GS eDRAM 32 Mbit eDRAM Sony, Toshiba 180 nm CMOS 279 [97]
2001 ? 288 Mbit RDRAM Hynix ? CMOS ? [98]
? DDR2 Samsung 100 nm CMOS ? [95][90]
2002 ? 256 Mbit SDR Hynix ? CMOS ? [98]
2003 EE+GS eDRAM 32 Mbit eDRAM Sony, Toshiba 90 nm CMOS 86 [97]
? 72 Mbit DDR3 Samsung 90 nm CMOS ? [99]
512 Mbit DDR2 Hynix ? CMOS ? [98]
Elpida 110 nm CMOS ? [100]
1024 Mbit DDR2 Hynix ? CMOS ? [98]
2004 ? 2048 Mbit DDR2 Samsung 80 nm CMOS ? [101]
2005 EE+GS eDRAM 32 Mbit eDRAM Sony, Toshiba 65 nm CMOS 86 [102]
Xenos eDRAM 80 Mbit eDRAM NEC 90 nm CMOS ? [103]
? 512 Mbit DDR3 Samsung 80 nm CMOS ? [95][104]
2006 ? 1024 Mbit DDR2 Hynix 60 nm CMOS ? [98]
2008 ? ? LPDDR2 Hynix ?
Apr 2008 ? 8192 Mbit DDR3 Samsung 50 nm CMOS ? [105]
2008 ? 16384 Mbit DDR3 Samsung 50 nm CMOS ?
2009 ? ? DDR3 Hynix 44 nm CMOS ? [98]
2048 Mbit DDR3 Hynix 40 nm
2011 ? 16384 Mbit DDR3 Hynix 40 nm CMOS ? [106]
2048 Mbit DDR4 Hynix 30 nm CMOS ? [106]
2013 ? ? LPDDR4 Samsung 20 nm CMOS ? [106]
2014 ? 8192 Mbit LPDDR4 Samsung 20 nm CMOS ? [107]
2015 ? 12 Gbit LPDDR4 Samsung 20 nm CMOS ? [96]
2018 ? 8192 Mbit LPDDR5 Samsung 10 nm FinFET ? [108]
128 Gbit DDR4 Samsung 10 nm FinFET ? [109]

SGRAM

[edit]
Synchronous graphics random-access memory (SGRAM)
Date of introduction Chip name Capacity (bits)[86] SDRAM type Manufacturer(s) Process MOSFET Area Ref
November 1994 HM5283206 8 Mbit SGRAM (SDR) Hitachi 350 nm CMOS 58 mm2 [110][111]
December 1994 μPD481850 8 Mbit SGRAM (SDR) NEC ? CMOS 280 mm2 [112][113]
1997 μPD4811650 16 Mbit SGRAM (SDR) NEC 350 nm CMOS 280 mm2 [114][115]
September 1998 ? 16 Mbit SGRAM (GDDR) Samsung ? CMOS ? [93]
1999 KM4132G112 32 Mbit SGRAM (SDR) Samsung ? CMOS 280 mm2 [116]
2002 ? 128 Mbit SGRAM (GDDR2) Samsung ? CMOS ? [117]
2003 ? 256 Mbit SGRAM (GDDR2) Samsung ? CMOS ? [117]
SGRAM (GDDR3)
March 2005 K4D553238F 256 Mbit SGRAM (GDDR) Samsung ? CMOS 77 mm2 [118]
October 2005 ? 256 Mbit SGRAM (GDDR4) Samsung ? CMOS ? [119]
2005 ? 512 Mbit SGRAM (GDDR4) Hynix ? CMOS ? [98]
2007 ? 1024 Mbit SGRAM (GDDR5) Hynix 60 nm
2009 ? 2048 Mbit SGRAM (GDDR5) Hynix 40 nm
2010 K4W1G1646G 1024 Mbit SGRAM (GDDR3) Samsung ? CMOS 100 mm2 [120]
2012 ? 4096 Mbit SGRAM (GDDR3) SK Hynix ? CMOS ? [106]
March 2016 MT58K256M32JA 8 Gbit SGRAM (GDDR5X) Micron 20 nm CMOS 140 mm2 [121]
January 2018 K4ZAF325BM 16 Gbit SGRAM (GDDR6) Samsung 10 nm FinFET 225 mm2 [122][123][124]

See also

[edit]

References

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Random-access memory

View on Grokipedia
from Grokipedia
Random-access memory (RAM) is a type of volatile that enables the processor to access data items in nearly constant time, regardless of their sequential or random physical location within the memory, distinguishing it from sequential-access media like magnetic tapes. In computing systems, RAM serves as the primary , temporarily holding the operating system, active software programs, and data being processed by the (CPU) for rapid read and write operations, typically in nanoseconds. Unlike non-volatile storage such as hard drives or , RAM loses all stored information when power is disconnected, necessitating reloading of data upon restart. The concept of random-access memory originated in the late 1940s with the development of the Williams-Kilburn tube, a cathode-ray tube-based storage invented by Frederic C. Williams and Tom Kilburn at the , which enabled the first reprogrammable electronic digital computer, known as the Manchester "Baby," to run its initial program on June 21, 1948. This early innovation paved the way for in the 1950s, which dominated until the late 1960s when semiconductor-based integrated-circuit RAM emerged, including the first commercial dynamic RAM (DRAM) chip, the , released in October 1970. RAM is broadly categorized into two main types: static RAM (SRAM), which uses bistable latching circuitry (typically six transistors per bit) for high-speed operation without periodic refreshing and is commonly employed in CPU caches; and dynamic RAM (DRAM), which stores each bit in a capacitor-transistor pair for higher density and lower cost but requires regular refreshing to maintain , making it the standard for main system memory. Advancements in RAM technology, such as increased capacities (e.g., modern systems often featuring 16–128 GB or more as of ) and faster access speeds, have been crucial for enhancing overall , enabling multitasking, and supporting demanding applications like and gaming.

Fundamentals

Definition and characteristics

Random-access memory (RAM) is a type of volatile that allows data to be read from or written to any in approximately the same amount of time, independent of the physical of the data within the memory. This capability distinguishes RAM from media, such as , where accessing a specific data item requires traversing all preceding items, resulting in access times that vary significantly based on position. In contrast, RAM's uniform access time enables efficient direct addressing, making it ideal for rapid data retrieval and modification in computing systems. Key characteristics of RAM include its volatility, meaning it loses all stored when power is removed, unlike non-volatile storage such as hard drives. It operates at high speeds relative to secondary storage devices, with access times typically in the nanosecond range, facilitating quick CPU interactions. RAM is generally byte-addressable, allowing the (CPU) to access individual bytes of by specifying their unique addresses, which supports granular manipulation. Primarily used for temporary storage of active programs, instructions, and , RAM serves as the in most devices, from personal computers to servers. In the , which forms the basis of most modern computers, RAM plays a central role by storing both program instructions and in a single, unified accessible by the CPU. This model allows the processor to fetch and execute instructions while simultaneously reading or writing , enabling the dynamic execution of programs. in RAM is organized into fundamental units called bits (binary digits), with groups of eight bits forming a byte, the standard unit for addressable storage. Capacities in modern systems range from several gigabytes in consumer devices to terabytes in high-end servers, reflecting the scalability of technology. Examples of RAM implementations include static RAM (SRAM) and dynamic RAM (DRAM), which differ in design but share these core properties.

Random access principle

The random access principle in (RAM) enables direct retrieval or modification of at any storage using a unique , without the need to scan or traverse preceding locations sequentially. This contrasts with media, such as magnetic tapes, where accessing a specific item requires physically or logically progressing through all prior content, leading to access times that scale with the distance from the current position. In RAM, the specifies the exact , allowing uniform and independent access to any cell, which is fundamental to efficient computing operations. Logically, RAM operates as a two-dimensional of addressable storage locations, where each position is identified by row and column coordinates derived from the input address bits. An interprets these bits to generate enable signals that activate the selected row and column lines, isolating the target location for read or write operations while keeping others inactive. This model ensures that data transfer occurs only at the addressed site, with control signals like chip enable, read/write select, and output enable coordinating the process to prevent conflicts. cells serve as the basic storage units that implement this principle by holding the bit values at each addressable location. Access time in RAM encompasses several key components that determine the overall latency for an operation. It begins with the address setup time (t_address), the duration required to stabilize the address lines on the inputs. This is followed by the decoding time (t_decode), during which the propagates signals to select the appropriate memory cell, influenced by gate delays in the logic circuitry. Finally, the data transfer time (t_data_transfer) covers the delay for reading data from the cell to the output or writing new data into it, including settling or bit line charging. The cycle time represents the minimum interval between consecutive read or write operations, typically exceeding the access time to allow for signal recovery and setup for the next cycle. This uniform latency assumption underpins addressing mechanisms, as it guarantees consistent performance regardless of location. In an idealized model, the total access time can be expressed as: taccess=taddress+tdecode+tdata transfert_{\text{access}} = t_{\text{address}} + t_{\text{decode}} + t_{\text{data transfer}} This equation derives from the sequential signal paths in the memory system: the address must first settle before decoding can begin, which in turn must complete before data can be transferred along the bit lines. Propagation delays accumulate along these paths, setting the fundamental limit on operation speed in the logical framework.

Historical development

Early technologies

The development of random-access memory in the mid-20th century began with innovative but imperfect technologies that bridged the gap from mechanical storage to electronic systems, primarily relying on acoustic, electrostatic, and magnetic principles. These early approaches addressed the need for faster, more reliable data access in computing machines, though they often approximated true through sequential recirculation or scanning mechanisms. Key inventions emerged during and the immediate postwar period, driven by efforts to create stored-program computers. One of the earliest forms was , which utilized to store as ultrasonic pulses propagating through a medium like mercury or magnetostrictive wire, allowing recirculation for repeated access. Developed from signal delay techniques, it was first applied in computers such as the design proposed in 1945 and implemented in machines like the in 1951, where each delay-line unit stored up to 1,024 bits with an average access time of about 222 microseconds. In the computer, completed in 1949 at the , 32 mercury-filled tubes provided a total capacity of 512 35-bit words (approximately 18,000 bits), with a cycle time of 1.5 milliseconds; data was serialized and recirculated, offering that simulated by buffering words in registers for near-immediate retrieval. However, this technology required physical transducers and lengthy tubes—up to 5 feet long—making systems bulky and heavy, with units weighing nearly 800 pounds each. A breakthrough in true electronic random-access memory came with the Williams-Kilburn tube in 1946, invented by Frederic C. Williams and Tom Kilburn at the , who demonstrated a cathode-ray tube (CRT) capable of storing one bit as a charged spot on a phosphor-coated screen, refreshed by an electron beam to prevent decay. By 1947, they demonstrated a tube storing 2,048 bits. This enabled the —the world's first stored-program electronic computer—to run its inaugural program on June 21, 1948, using one such tube for a capacity of 32 words of 32 bits (1,024 bits total). This electrostatic storage allowed direct addressing of any bit without sequential scanning, marking the first practical read-write random-access device and influencing subsequent machines like the Mark I. Despite its innovation, the suffered from low reliability, as phosphor spots faded quickly and tubes burned out frequently, limiting density to around 1,000-2,000 bits per tube and requiring high voltage for operation. By the early 1950s, emerged as a more robust alternative, using tiny rings (cores) of ferrite material—typically 0.05-inch diameter donuts—magnetized to represent bits, threaded by wires for read/write currents. Invented by in 1951 and first implemented in the MIT computer in 1953, it provided non-volatile, random-access storage with cycle times under 20 microseconds and initial capacities of 1,024 words, expandable to 4,096 words in later systems. The 's core plane, operational from August 1953, stored data reliably without constant refreshing, becoming a standard in military and commercial computers due to its durability under vibration. Nonetheless, core memory demanded meticulous hand-wiring of thousands of cores per plane, driving high fabrication costs and labor, while early versions consumed significant power for switching. These pre-semiconductor technologies—delay lines, CRT tubes, and core memory—laid the groundwork for modern RAM but were hampered by inherent drawbacks, including excessive power consumption (often kilowatts for entire systems), physical bulk that filled rooms, and prohibitive costs exceeding thousands of dollars per kilobit. Their limitations in speed, density, and scalability ultimately spurred the transition to metal-oxide-semiconductor (MOS) integrated circuits in the for more efficient electronic memory.

Semiconductor era

The semiconductor era of random-access memory began in the mid-1960s with the transition from technology to integrated circuit-based designs, marking a pivotal shift toward higher performance and scalability in computing systems. Early efforts focused on bipolar transistor implementations for static RAM (SRAM), exemplified by IBM's SP95 chip introduced in 1965. This 16-bit bipolar SRAM was deployed in the System/360 Model 95 mainframe, providing faster access times suitable for high-speed computing applications and representing IBM's initial foray into production. The advent of metal-oxide-semiconductor (MOS) technology accelerated RAM development, enabling denser and more cost-effective chips. Fairchild Semiconductor developed MOS RAM in 1968 using 64-bit p-channel SRAM chips assembled into hybrid modules to achieve 1,024-bit capacities, leveraging silicon-gate MOS processes for greater integration. This was followed by Intel's 1103 in 1970, the first commercially successful 1K-bit (1,024 bits) dynamic RAM (DRAM) chip, which used p-channel MOS transistors and quickly gained adoption in systems like the HP 9800 series. These MOS innovations offered significant advantages over magnetic core memory, including smaller physical size, lower power consumption, reduced susceptibility to magnetic interference, and shock resistance, while matching or exceeding core's reliability in smaller capacities. MOS scaling, guided by Gordon Moore's 1965 observation that transistor density would double approximately every year (later revised to every two years), drove exponential increases in RAM density and affordability, fundamentally transforming memory manufacturing. A key divergence emerged between SRAM and DRAM architectures during this period, shaping their distinct roles in computing. SRAM employed bistable latching circuitry with multiple s per cell to store data without periodic refresh, ensuring faster access but limiting density due to higher counts. In contrast, DRAM utilized a single paired with a for each bit, enabling much higher densities—up to four times that of early SRAM—but necessitating periodic refreshing to counteract charge leakage from the s. This trade-off positioned SRAM for speed-critical applications like caches and DRAM for bulk main memory. The commercial impact of these semiconductor breakthroughs was profound, as RAM prices plummeted from approximately 1 cent per bit for the in 1970 to fractions of a cent by the early , driven by volume production and scaling efficiencies. This dramatic cost reduction—from over $1 per bit in early prototypes to under $0.01 per bit by 1980—made affordable memory viable for personal computers, fueling the rise of microcomputing and widespread .

Key milestones

One of the earliest milestones in random-access memory development occurred in 1947, when Freddie Williams and Tom Kilburn demonstrated the Williams-Kilburn tube at the , marking the first practical form of electronic random-access memory using a cathode-ray tube to store binary data as charged spots on its screen. A pivotal shift to semiconductor-based RAM came in 1970 with Intel's introduction of the 1103, the first commercially successful (DRAM) chip, featuring a 1 Kbit capacity and replacing bulkier in computing systems. Synchronous DRAM (SDRAM) emerged in the early to synchronize access with the clock for improved ; released the first commercial 16 Mbit SDRAM chip (KM48SL2000) in 1993, enabling faster data transfer rates up to 200 MHz. The 2000s saw rapid evolution in ( variants: DDR2 was introduced in 2003, doubling the prefetch buffer size to 4 bits and achieving transfer rates up to 1,066 MT/s while reducing power consumption to 1.8 V. DDR3 followed in 2007, further lowering voltage to 1.5 V and boosting speeds to 1,866 MT/s with an 8-bit prefetch, becoming the standard for consumer PCs and servers through the early . High-bandwidth memory (HBM) addressed bandwidth demands for graphics processing units (GPUs) with HBM1's debut in 2013 by , stacking up to eight DRAM dies using through-silicon vias (TSVs) to deliver up to 128 GB/s per stack at 1 Gbps per pin. The and brought continued scaling: DDR4 launched in 2014 with initial speeds of 2,133 MT/s and support for up to 3.2 V operation, emphasizing higher densities and efficiency for mainstream . Low-power DDR5 (LPDDR5) arrived in 2019 for mobile devices, offering transfer rates up to 6,400 MT/s at 1.05 V to support and AI features in smartphones. DDR5 debuted in 2020, starting at 4,800 MT/s and scaling to 8,400 MT/s with on-die error correction and dual 32-bit sub-channels for enhanced reliability and bandwidth. HBM3 was standardized in 2022, providing up to 819 GB/s bandwidth per stack at 6.4 Gbps per pin, optimized for and AI accelerators. HBM3E, an extension, was introduced in 2024, offering up to 9.6 Gbps per pin for 1.2 TB/s bandwidth. By 2025, DDR5 achieved widespread adoption in mainstream PCs, driven by and platforms supporting speeds up to 8,000 MT/s and becoming the default for new consumer systems. Concurrently, 3D-stacked DRAM technologies, including advanced HBM variants and capacitorless designs, gained traction for AI workloads, enabling higher densities and bandwidth in data centers without relying solely on traditional HBM stacks. Throughout these developments, RAM chip density has grown exponentially, from the 1 Kbit in 1970 to 32 Gbit single-die DRAM chips as of 2025, with ongoing development toward higher densities via 3D integration techniques.

Memory types

Static RAM (SRAM)

(SRAM) is a type of that stores data using bistable latching circuitry, enabling fast and reliable access without the need for periodic refreshing. Unlike dynamic RAM, which relies on capacitors that leak charge over time, SRAM maintains its state as long as power is supplied, making it ideal for applications requiring high-speed performance. The fundamental building block of SRAM is the memory cell, typically consisting of six transistors arranged in a configuration that provides stable . The most common SRAM cell is the 6-transistor (6T) structure, which employs two cross-coupled inverters to form a flip-flop for bistable storage of a single bit, along with two access transistors connected to bit lines. This flip-flop design ensures that the stored value remains stable due to the between the inverters, holding either a logic '0' or '1' indefinitely under (DC) power. Variants include the 4-transistor (4T) cell, which replaces the load transistors with high-resistance polysilicon resistors to reduce size, though it demands additional fabrication steps and exhibits higher power during reads. An 8-transistor (8T) configuration adds separate read ports to mitigate read disturbances, enhancing stability in low-power scenarios. In operation, SRAM cells maintain their state through continuous DC power to the inverters, eliminating the refresh cycles required in other memory types. Reading involves activating the word line to turn on the access transistors, allowing the differential voltage on the bit lines to be sensed by a without altering the stored data. Writing occurs by driving the bit lines with the new data value while the word line is asserted, overpowering the flip-flop to set the desired state. This process enables sub-nanosecond access times in modern implementations, supporting rapid data retrieval critical for performance-sensitive systems. In contrast to dynamic RAM, SRAM's design avoids refresh overhead, ensuring consistent latency. SRAM offers key advantages including exceptionally fast access speeds, often below 1 ns in advanced nodes, and immunity to from charge leakage since no capacitors are involved. It also provides higher stability against single-event upsets in certain configurations due to the regenerative nature of the flip-flop, though susceptibility to soft errors increases with scaling. However, these benefits come with drawbacks: SRAM consumes significantly more static power than alternatives because each bit requires six s, leading to lower density—typically around 6 transistors per bit compared to one and one in other designs. This results in larger chip area and higher costs for high-capacity storage. SRAM finds primary applications in speed-critical environments, such as level-1 (L1) and level-2 (L2) CPU caches, where low latency directly impacts processor performance, and in register files for temporary data holding during computations. In embedded systems, it serves as on-chip memory for microcontrollers and DSPs, providing reliable, non-volatile-like retention without external components. Modern processors integrate 10-20 MB of SRAM-based caches, often in multi-level hierarchies to balance speed and capacity. The evolution of SRAM began in the 1960s with bipolar transistor implementations, which offered high speed but suffered from high power consumption; introduced its first 64-bit bipolar SRAM in 1969. By the , the shift to technology reduced power and improved density, enabling widespread adoption in integrated circuits as CMOS processes scaled. Today, SRAM is fabricated at advanced nodes like 7 nm, supporting larger cache sizes while maintaining sub-nanosecond access for .

Dynamic RAM (DRAM)

Dynamic random-access memory (DRAM) stores each bit of data as an electrical charge in a capacitor within a one-transistor, one-capacitor (1T1C) cell structure. The capacitor holds the charge representing the binary value—high for a logic 1 and low for a logic 0—while the transistor acts as a switch to access the cell during read or write operations. This design enables DRAM to achieve higher storage density compared to alternatives like static RAM, as it requires only one transistor per bit. Reading data from a DRAM cell is destructive, meaning the process discharges the and alters the stored charge, necessitating restoration via a write-back operation. Sense amplifiers detect the small voltage difference on the bit line caused by the charge sharing between the and the line, amplifying it to determine the bit value and then rewriting it to the cell. Due to inherent leakage in the , DRAM cells lose charge over time, requiring periodic refresh cycles to recharge them and prevent ; the standard retention time mandates refreshing all cells within 64 milliseconds. Early DRAM implementations operated asynchronously, responding to address and control signals without to a system clock, which suited initial personal computing applications but limited performance in faster systems. Synchronous DRAM (SDRAM) addressed this by aligning operations with an external clock signal, enabling pipelined bursts and higher throughput, as seen in standards like PC100. Unlike static RAM, which retains data without refresh using bistable circuits, DRAM's capacitor-based approach trades stability for greater capacity at lower cost. DRAM's primary advantages include its high density and low cost per bit, making it ideal for main memory in computing systems where large capacities are essential. However, the need for refresh operations consumes power and bandwidth, and access latencies typically range from 10 to 50 nanoseconds, higher than static alternatives due to the sensing and restoration steps. Modern DRAM evolution includes DDR5, standardized in 2020, which incorporates on-die error-correcting code (ECC) for improved reliability and supports module capacities up to 256 gigabytes or more in registered DIMM configurations, as of 2025. The DRAM chip market is an oligopoly controlled by three main manufacturers—Samsung Electronics, SK Hynix, and Micron Technology—which collectively hold approximately 93% of the market share as of Q3 2025, with minor players such as CXMT (5%), Nanya (2%), and Winbond holding smaller shares; most RAM module brands assemble modules using chips sourced primarily from these three. Samsung is strong in mobile and server DRAM, SK Hynix dominant in high-bandwidth memory for AI, and Micron known for cost-effective high-capacity solutions.

Specialized variants

Synchronous Graphics RAM (SGRAM) is a variant of synchronous dynamic random-access memory (SDRAM) optimized for graphics applications, incorporating features such as on-chip buffers and block write capabilities to accelerate pixel data transfers and screen refreshes. Developed in the 1990s, SGRAM was commonly used in video cards for mid-range personal computers, enabling efficient handling of graphics workloads that required bandwidth exceeding 200 MB/s despite varying data sizes from 1 to 16 MB. Modern iterations, such as Graphics Double Data Rate 6 (GDDR6) SGRAM and the newer GDDR7 (introduced in 2025 with speeds up to 32 Gbps), maintain high bandwidth and low latency interfaces tailored for graphics processing units (GPUs), though GDDR7 faces production shortages as of late 2025. Rambus DRAM (RDRAM), introduced in the late 1990s, employs a high-speed serial interface to achieve significantly greater bandwidth than traditional parallel DRAM architectures. Direct RDRAM (DRDRAM) operates at 400 MHz with a 3-byte-wide channel (two bytes for data and one for addresses/commands), delivering up to three times the bandwidth of 66-MHz SDRAM subsystems while integrating seamlessly into existing module designs. Despite initial adoption in , RDRAM was largely phased out by the early due to high costs, power consumption, and competition from . High Bandwidth Memory (HBM) represents a 3D-stacked DRAM technology designed for ultra-high-throughput applications in GPUs and AI accelerators, where multiple DRAM dies are vertically integrated using through-silicon vias for enhanced inter-chip communication. The latest variant, HBM3e released in 2023, achieves a maximum bandwidth of 1.2 TB/s per stack, enabling the processing of over 230 Full-HD movies per second and supporting the data-intensive demands of workloads. HBM3e builds on prior generations by increasing I/O bandwidth to 1280 GB/s while maintaining pin efficiency through advanced signaling for 1024 data lines. Error-Correcting Code (ECC) RAM extends standard DRAM or SRAM by incorporating additional parity bits to detect and correct errors, primarily targeting single-bit errors in mission-critical environments. Using algorithms like Hamming or Hsiao codes for single-error correction and double-error detection (SEC-DED), ECC RAM automatically corrects correctable errors without system intervention, with uncorrectable errors triggering alerts or halts based on reliability configurations. This feature is standard in server-grade memory modules, where it enhances for workloads involving large datasets, such as database management and scientific computing. Low-Power Double Data Rate 5 (LPDDR5) is a mobile-optimized DRAM standard that prioritizes energy efficiency alongside performance, achieving data rates up to 6.4 Gbps—50% higher than LPDDR4—through advancements in I/O signaling and voltage scaling. Standardized in 2019, LPDDR5 supports configurations like 12 Gb densities in 10 nm-class processes, enabling 12 GB packages to transfer 44 GB/s, equivalent to 12 Full-HD movies per second, while reducing power draw for battery-constrained devices such as smartphones and tablets. The successor, LPDDR6, standardized in July 2025, increases speeds to 10.7 Gbps (with plans for 14 Gbps) for enhanced AI and mobile performance. Video RAM (VRAM) is a dual-ported DRAM specialized for display systems, allowing simultaneous read and write operations through separate ports to support real-time frame buffer updates without contention. This includes a conventional DRAM array paired with a static for serial data output, facilitating high-speed streaming to video displays in the and . VRAM's dual-port capability significantly improves throughput for rendering compared to single-ported alternatives, though it has been largely superseded by integrated GPU memory solutions.

Internal components

Memory cell structures

Memory cells in random-access memory (RAM) form the fundamental storage units, where each cell holds a single bit of through electrical means, enabling direct access without sequential traversal. These cells vary by RAM type, balancing density, speed, and power efficiency, with designs evolving to counter scaling limits in fabrication. The core structures rely on transistor-capacitor or transistor-only configurations to maintain binary states ('0' or '1') against leakage and . In static RAM (SRAM), the standard memory cell employs a 6-transistor (6T) configuration consisting of two cross-coupled inverters for storage and two access transistors for read/write operations. The cross-coupled inverters create a bistable that holds the state indefinitely as long as power is supplied, with the access transistors connecting the cell to bit lines under word-line control. Stability in this design is governed by the beta ratio, defined as the width ratio of pull-down to pass-gate transistors, which ensures robust noise margins during reads by preventing state flips. Dynamic RAM (DRAM) cells, in contrast, use a simpler 1-transistor-1-capacitor (1T1C) structure, where a single access controls charge storage on a representing the bit value—high charge for '1' and low for '0'. The can be implemented as a type, etched deeply into the substrate to maximize within a compact footprint, or a stacked type, built vertically above the using layered dielectrics and electrodes for increased surface area. During a read operation, charge sharing occurs between the storage and the bit line, partially discharging the cell and necessitating a restore write-back to maintain . As feature sizes scale below 20 nm, memory cell designs face challenges from increased leakage currents and variability, addressed by advanced 3D transistor architectures—such as FinFETs in SRAM cells starting at the 14–22 nm nodes and buried or vertical channel transistors in DRAM arrays—to better control short-channel effects and subthreshold leakage. To boost density, 3D cell architectures—such as vertical trench extensions or multi-layered stacked capacitors—enable smaller footprints, with modern DRAM cells achieving areas around 6F² (where F is the minimum feature size). For DRAM, data retention time, the duration a cell holds charge without refresh, is approximated by the equation tret=C⋅VIleakt_{\text{ret}} = \frac{C \cdot V}{I_{\text{leak}}} where CC is the storage capacitance, VV is the initial voltage, and IleakI_{\text{leak}} is the leakage current; typical retention under JEDEC standards is 64 ms at room temperature.

Addressing mechanisms

Random-access memory (RAM) employs a two-dimensional organization to store , where memory cells are arranged in rows and columns. Each row is associated with a word line that activates the cells within it, while each column connects to bit lines for transfer. Row decoders select the appropriate word line based on the row , and column multiplexers route the bit lines to sense amplifiers for reading or writing . This structure enables efficient access to any cell by specifying its row and column coordinates, with the word line briefly activating the targeted row to connect cells to their bit lines. In dynamic RAM (DRAM), addresses are multiplexed to minimize the number of pins required on the chip. The full address is divided into row and column portions, which are transmitted sequentially over the same address bus. The row address is latched when the Row Address Strobe (RAS) signal is asserted, activating the corresponding row via the word line. Subsequently, the column address is latched upon assertion of the Column Address Strobe (CAS) signal, which selects the specific bit lines from the activated row for data access. This RAS/CAS protocol, standard in synchronous DRAM variants like DDR4, supports sequential input while allowing the memory controller to manage timing delays such as tRCD (row-to-column delay). To enhance performance and enable pipelining, modern DRAM chips incorporate multiple independent banks, each functioning as a separate subarray with its own row and column decoders. Bank interleaving distributes consecutive addresses across these banks, allowing parallel or overlapped operations; for instance, while one bank processes a row and precharge, another can initiate access to a different . In DDR4 DRAM, configurations typically feature 16 banks organized into 4 bank groups, with interleaving at the bank or bank-group level to read/write bursts and mitigate access latency. This parallelism increases effective bandwidth without increasing the interface width. The total storage capacity of a DRAM chip is determined by the product of its structural dimensions: the number of rows, columns per row, , and width per column access. For example, in a DDR4 device with 32K rows, 1K columns, 16 , and an 8-bit width, the capacity calculates as follows: Total bits=rows×columns×banks×width=215×210×16×8=232 bits (4 Gbit).\text{Total bits} = \text{rows} \times \text{columns} \times \text{banks} \times \text{width} = 2^{15} \times 2^{10} \times 16 \times 8 = 2^{32} \text{ bits (4 Gbit)}. This formula accounts for the , where each contributes independently to the overall density. Power management in addressing involves precise timing for precharge and sense amplification to maintain and minimize energy use. After a row access, bit lines must be precharged to an intermediate voltage (typically VDD/2) via the precharge command, ensuring balanced conditions for the next ; this phase, governed by tRP (precharge time, e.g., 11 clock cycles in DDR4), restores the bit lines while deactivating the word line. Sense amplifiers then detect and amplify the small voltage differentials on the bit lines during row , latching the row into a buffer for column access; their timing, integrated into tRCD, prevents leakage and supports efficient refresh operations across banks. These mechanisms balance speed and power, with interleaving further reducing idle times in precharge phases.

System-level aspects

Memory hierarchy

The memory hierarchy in modern computer systems organizes storage levels to optimize performance, cost, and capacity by providing faster access to frequently used while maintaining larger, slower storage for less active information. Random-access memory (RAM), primarily in the form of dynamic RAM (DRAM), occupies the main memory level, bridging the gap between high-speed, low-capacity processor caches and persistent secondary storage devices. This structure allows processors to operate as if they have access to a vast, uniform memory space, masking the inherent speed disparities between components. The hierarchy progresses from registers, which are the fastest and smallest storage (on the order of tens of bytes directly within the CPU), to multilevel caches (L1, L2, L3) constructed from static RAM (SRAM) for rapid access, then to main RAM using DRAM for bulk storage (gigabytes to terabytes), and finally to secondary storage such as solid-state drives (SSDs) or hard disk drives (HDDs) for massive, non-volatile capacity. Each successive level increases in size and cost-effectiveness per bit but decreases in access speed, with data from lower levels cached in upper levels as needed to minimize average access time. Registers and caches hold subsets of main contents, while main subsets secondary storage, creating an inclusive pyramid that exploits program behavior for efficiency. The hierarchy's success depends on locality of reference, a principle observed in typical programs where data access patterns exhibit temporal locality—recently used data is likely to be referenced again soon—and spatial locality—data near a recently accessed location tends to be accessed next. Caches leverage these properties through techniques like prefetching adjacent blocks for spatial locality and retaining recent data for temporal reuse, reducing the need to fetch from slower main RAM or beyond. Without such locality, the performance benefits of the hierarchy would diminish significantly. In multiprocessor systems, cache coherence maintains data consistency across multiple caches sharing the same main RAM by using protocols like MESI, which tracks cache line states as Modified (locally changed and exclusive), Exclusive (clean and unique), Shared (readable by multiple caches), or Invalid (stale and unusable). The MESI protocol coordinates bus snooping or directory-based invalidations and updates to prevent processors from reading outdated values, ensuring a unified view of memory despite distributed caching. This coherence overhead is a key trade-off in parallel architectures but is essential for correct operation. Virtual memory extends the effective size of main RAM by integrating it with secondary storage through paging, where fixed-size blocks (pages) of virtual address space are mapped to physical RAM frames, and swapping, which moves inactive pages to disk when RAM is full. This allows programs to use more memory than physically available, with the operating system handling page faults by loading needed pages from disk into RAM as required. Main memory thus acts as a cache for the virtual address space backed by disk. Performance trade-offs across the hierarchy are stark, with main RAM (DRAM) providing aggregate bandwidths of 50-100 GB/s in typical dual-channel configurations and access latencies of 50-100 ns, in contrast to L1 cache latencies around 1 ns and higher per-core bandwidths exceeding 100 GB/s due to proximity to the processor. These metrics highlight RAM's role in sustaining high-throughput workloads while introducing delays for uncached accesses, motivating ongoing optimizations in the hierarchy. variants dominate main memory implementations for their balance of and speed.

Common applications and uses

Random-access memory (RAM) serves as the primary in personal computers and servers, enabling multitasking, operating system buffering, and rapid data access for running applications. In typical personal computers, configurations range from 8 GB for basic tasks to 128 GB or more for demanding workloads like or , with 16 GB established as a standard minimum in 2025 for optimal performance, particularly in multitasking scenarios such as opening multiple browser tabs alongside office applications, where it prevents lagging and performance issues by providing sufficient capacity to handle simultaneous loads without excessive swapping to slower storage. Servers often employ error-correcting code (ECC) RAM in capacities starting at 8-32 GB for standard operations, scaling up to hundreds of gigabytes or terabytes to handle multiple virtual machines and large-scale . RAM disks provide a virtual storage solution by utilizing RAM to create high-speed, temporary file systems, significantly outperforming traditional disk-based drives for short-term data operations. In Linux systems, the tmpfs filesystem implements this by storing files entirely in virtual memory, allowing for quick read/write access while ensuring data is lost upon system reboot or unmounting, which is ideal for caching or temporary computations. This approach leverages the full speed of RAM, making it suitable for applications requiring minimal latency, such as compiling code or processing transient datasets. Shadow RAM, a legacy technique from early BIOS implementations, involves copying firmware code from slower read-only memory (ROM) to faster RAM during system initialization to accelerate execution of boot processes and hardware initialization routines. This method was common in pre-UEFI systems to mitigate performance bottlenecks in video and peripheral initialization, though modern Unified Extensible Firmware Interface (UEFI) environments have largely phased it out in favor of more efficient firmware architectures. In embedded systems, particularly for (IoT) devices, static RAM (SRAM) is integrated directly into microcontrollers to provide on-chip memory for real-time processing and low-power operations. This embedded SRAM enables efficient handling of sensor data, control algorithms, and firmware execution in resource-constrained environments like smart sensors or wearables, where its fast access times and non-volatility during active operation support seamless connectivity and responsiveness. High-capacity RAM variants like DDR5 and high-bandwidth memory (HBM) find extensive use in gaming and applications, where they manage large datasets such as textures, procedural generations, and models. In gaming PCs and consoles, DDR5 modules support immersive rendering by delivering high throughput for dynamic scene loading, often in configurations exceeding 32 GB. For AI accelerators, HBM's stacked architecture provides the bandwidth and needed for training neural networks, enabling parallel processing of massive models without bottlenecks. Some (VPN) servers employ RAM-only configurations to handle temporary secure data, storing session logs, encryption keys, and traffic metadata exclusively in that erases upon reboot. This design enhances privacy by preventing persistent storage of sensitive information, making it particularly useful for high-security environments where must be minimized after processing. Providers implement this through full RAM-based operating systems, ensuring no disk writes occur during operation.

Challenges and future directions

The memory wall

The memory wall describes the widening performance gap between rapidly advancing processor speeds and the comparatively stagnant improvements in random-access memory access times, a phenomenon first articulated by William A. Wulf and Sally A. McKee in their 1995 paper. They observed that from the mid-1980s onward, performance was increasing at an annual rate of approximately 80%, driven by advances in fabrication and architecture, while DRAM access times improved by only about 7% per year due to physical and scaling limitations in memory technology. This disparity results in processor stalls, where the CPU idles while awaiting data from memory, increasingly dominating execution time as consumes a growing number of CPU cycles—projected to reach hundreds of cycles per access by the early if trends persisted. The impacts of the memory wall are particularly pronounced in parallel computing environments, where Amdahl's law—stating that overall speedup is limited by the serial fraction of a workload—is amplified by memory-bound portions that resist parallelization. For instance, if a fraction fmemf_{mem} of instructions involves memory accesses, the effective speedup SS from faster processors or more cores can be modeled as S=11+fmem⋅(tmemtcpu),S = \frac{1}{1 + f_{mem} \cdot \left( \frac{t_{mem}}{t_{cpu}} \right)}, where tmemt_{mem} is the memory access time and tcput_{cpu} is the CPU cycle time; as tmem/tcput_{mem}/t_{cpu} grows, even parallelizable workloads see diminishing returns due to synchronized stalls at interfaces. Historical data underscores this: DRAM latencies decreased from around 100 ns in 1980 to approximately 60 ns in the , yet relative to CPU cycles, the gap widened from tens of cycles per access to over 200, bottlenecking applications like scientific simulations and data analytics. To mitigate the memory wall, computer architects have employed multilevel caching hierarchies to bridge the latency gap, with on-chip L1 and L2 caches providing sub-10 ns access for frequently used data and reducing main memory traffic by orders of magnitude. Hardware prefetching mechanisms further alleviate stalls by speculatively loading anticipated data into caches based on access patterns, improving hit rates in sequential or strided workloads without excessive bandwidth overhead. Additionally, multi-channel memory interfaces, such as the quad-channel configurations supported in modern systems with DDR5, enhance aggregate bandwidth to sustain higher throughput, though they address bandwidth more directly than raw latency. These techniques collectively extend processor utilization but cannot fully eliminate the underlying physical constraints of off-chip RAM.

Security considerations

Random-access memory (RAM), particularly dynamic RAM (DRAM), is susceptible to various security vulnerabilities that exploit its physical and operational characteristics. One prominent threat is the Rowhammer attack, first demonstrated in , where repeated access to a single row of DRAM cells induces bit flips in adjacent rows due to electrical interference between densely packed cells. This vulnerability arises from the aggressive scaling of DRAM cell density, which exacerbates cell-to-cell coupling and makes high-density modules more prone to such disturbances. To counter Rowhammer, several mitigations have been developed and deployed. Target Row Refresh (TRR) identifies frequently accessed "aggressor" rows and proactively refreshes neighboring victim rows to prevent bit flips, a technique integrated into modern DRAM controllers. Error-correcting code ( detects and corrects single-bit errors, providing partial protection against Rowhammer-induced flips, though multi-bit errors can evade it. Additional strategies include voltage adjustments to reduce cell interference and hardware-specific defenses, such as Intel's mechanisms that monitor access patterns in DDR5 systems. Another physical attack vector is the , which leverages in DRAM—the temporary retention of charge in cells after power loss, especially at low temperatures. By cooling the (e.g., to near-freezing levels) and rapidly rebooting into a malicious environment, attackers can extract residual data, such as encryption keys, within seconds to minutes post-power-off. Mitigations include immediate upon shutdown and hardware designs that accelerate data decay, though these do not fully eliminate the risk in all scenarios. Side-channel attacks, such as Spectre and Meltdown disclosed in 2018, exploit timing differences in cache and RAM access during to leak sensitive data across security boundaries. These vulnerabilities allow unauthorized reading of kernel or other privileged memory by measuring access latencies, bypassing isolation mechanisms like . Defenses include architectural changes like serializing fences (e.g., LFENCE instructions) to halt speculation and software patches that restrict indirect branches, though they introduce performance overhead. As of 2025, security enhancements in RAM have advanced significantly, with widespread adoption of on-die ECC in DDR5 modules, which corrects errors at the chip level to bolster resilience against both random faults and targeted attacks like . Ongoing research focuses on developing error-resistant DRAM cells, such as those with improved read-disturbance tolerance through modified capacitor structures and fault-tolerant architectures, to address vulnerabilities in next-generation high-density memory.

Supply shortages and price surges

In late 2025 and into 2026, random-access memory (RAM) prices experienced significant surges due to a global shortage driven by the AI boom, particularly high demand for powerful AI chips from Nvidia, AMD, and Google, and heightened demand for graphics processing units (GPUs). Supply-side dynamics featured manufacturers prioritizing higher-margin AI high-end products, such as server-grade DDR5 and LPDDR5X, which reduced supply for consumer-grade storage used in phones and PCs. Major DRAM producers, including Samsung Electronics, SK Hynix, and Micron Technology, prioritized these over consumer-grade DDR4 and DDR5 modules; this reallocation reduced available supply for the PC and laptop markets, with depleted inventories and vendors adopting aggressive pricing amid slower phone and PC shipments unable to offset strong pull from AI servers, and some phasing out consumer-focused production, such as Micron's exit from its Crucial consumer brand by early 2026. This shift was fueled by demand from hyperscalers such as Microsoft, Google, Meta, and Amazon for AI servers requiring substantial memory per system. IDC forecasts DRAM supply growth at only 16% year-over-year in 2026, below historical norms, exacerbating the imbalance. This prioritization has resulted in a declining relative share of PC sales in DRAM manufacturers' revenue, as AI and server demand—particularly for HBM—accounts for a growing portion of total DRAM sales due to its rapid expansion and high margins, while the PC market remains mature with low growth. Supply restrictions have led to stagnant or decreasing absolute PC volumes amid explosive overall revenue growth from AI applications, with server and data center segments emerging as the largest market. Specific price increases included a 314% year-over-year jump for DDR5 DRAM chips in the fourth quarter of 2025, according to TrendForce data cited in industry reports; DDR4 prices rose less severely as the shortage impacted DDR5 more due to production shifts favoring advanced memory aligned with AI needs. This made DDR4 a relatively better price/performance option for consumers. Contract prices for conventional DRAM were projected to rise 55-60% quarter-over-quarter in the first quarter of 2026, with expectations of over 50% increases compared to Q4 2025 due to persistent supply shortages for AI applications. Raja Koduri, an industry expert, predicted that if the DRAM/SRAM price-per-byte ratio drops below 5x due to irrational DRAM pricing, AI designs may shift to SRAM-based architectures, a change that could take 3-4 years given long design cycles. These shortages led to higher costs for consumer electronics, with anticipated 15-20% price hikes for PCs and 3-8% increases in average selling prices for smartphones, potentially contracting those markets. Despite challenges for end-users, the trends positively impacted the memory industry, boosting profits for manufacturers like Samsung, which reported a 160% jump in fourth-quarter 2025 operating profit.

Emerging technologies

Emerging technologies in random-access memory (RAM) are addressing the limitations of conventional volatile memories by prioritizing non-volatility, higher densities, and reduced data movement bottlenecks through novel materials and architectures. (MRAM) stores data in the magnetic orientation of ferromagnetic layers, providing non-volatile retention without power and exceeding 101510^{15} cycles. Spin-transfer torque MRAM (STT-MRAM), a prominent variant, switches states using spin-polarized electron currents for efficient, low-power operation at speeds. Everspin Technologies introduced a 1 Gb STT-MRAM device in 2016, optimized for last-level cache applications in processors. By 2025, STT-MRAM has advanced to 14 nm embedded processes by manufacturers such as , enabling integration into system-on-chips for automotive and ; Everspin's EM128LX high-reliability offerings, produced at 28 nm with densities up to 128 Mb, support these applications. Resistive RAM (ReRAM) relies on voltage-induced resistance changes in metal-oxide layers to encode , facilitating compact crossbar configurations that support 3D stacking for terabit-scale densities. These minimize interconnect overhead and enable selector devices to suppress sneak currents, achieving cell sizes as small as 4F². ReRAM exhibits high endurance, with optimized oxide-based devices demonstrating over 101210^{12} write cycles while maintaining multi-level states for analog . Post-2020 has emphasized disturbance-resilient 3D ReRAM crossbars for in-memory , where parallel weight updates in accelerators yield up to 90% accuracy retention in training tasks. 3D XPoint, a phase-change co-developed by and Micron, utilized chalcogenide materials to toggle between amorphous and crystalline states for non-volatile storage with DRAM-comparable latencies around 100 ns. This hybrid approach bridged the performance gap between volatile RAM and flash, offering 1000× faster reads than NAND and endurance beyond 10810^8 cycles per cell. Despite enabling Optane modules for data-centric workloads, production ceased with Micron's exit in 2021 and Intel's Optane discontinuation in 2022, influenced by cost and market dynamics. Compute-in-memory architectures perform operations directly within memory structures to circumvent the memory wall, slashing data transfer energy by orders of magnitude in bandwidth-constrained systems. Processing-in-memory (PIM) variants embed simple accelerators, such as multiply-accumulate units, into high-bandwidth memory (HBM) stacks for AI matrix computations. Samsung's HBM-PIM, commercialized from 2021, integrates 16-bit floating-point processing to boost deep inference by up to 2.4× in power efficiency compared to GPU offloading. Through 2025, PIM extensions to HBM3E target large language models, with prototypes showing 4× throughput gains in decoding. In 2025, (CXL) standardizes coherent memory pooling over PCIe, allowing disaggregated RAM resources to be shared across servers with latencies typically in the 200–600 ns range and up to 64 TB capacities per fabric. CXL 3.0 enhancements support dynamic allocation for AI training, reducing idle memory by 50% in hyperscale environments. Concurrent trends explore quantum-resistant RAM designs, embedding post-quantum lattice-based encryption primitives to safeguard data against vulnerabilities in future quantum threats.

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